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  • Hardware Modeling Using Verilog: Course Outline

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    This document provides information about a course on hardware modeling using Verilog. The 8-week course will introduce participants to the Verilog hardware description language and teach them how to model digital circuits using Verilog, write test benches, and study some case studies. The course is intended for students of CSE, ECE, and EE and will be useful for careers in companies like Intel, Cadence, and Xilinx. The course will be taught by Prof. Indranil Sengupta, who has over 28 years of experience in teaching and researching CSE and has guided 22 PhD students.

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    This document provides information about a course on hardware modeling using Verilog. The 8-week course will introduce participants to the Verilog hardware description language and teach them how to model digital circuits using Verilog, write test benches, and study some case studies. The course is intended for students of CSE, ECE, and EE and will be useful for careers in companies like Intel, Cadence, and Xilinx. The course will be taught by Prof. Indranil Sengupta, who has over 28 years of experience in teaching and researching CSE and has guided 22 PhD students.

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    43 views1 page

    Hardware Modeling Using Verilog: Course Outline

    Uploaded by

    arunika pal
    This document provides information about a course on hardware modeling using Verilog. The 8-week course will introduce participants to the Verilog hardware description language and teach them how to model digital circuits using Verilog, write test benches, and study some case studies. The course is intended for students of CSE, ECE, and EE and will be useful for careers in companies like Intel, Cadence, and Xilinx. The course will be taught by Prof. Indranil Sengupta, who has over 28 years of experience in teaching and researching CSE and has guided 22 PhD students.

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    of 1

    HARDWARE MODELING

    USING VERILOG

    PROF. INDRANIL SENGUPTA TYPE OF COURSE : Rerun | Elective | UG


    Dept. of Computer Science and Engineering COURSE DURATION : 8 weeks (26 Aug’19 - 18 Oct’19)
    IIT Kharagpur
    EXAM DATE : 16 Nov 2019

    INTENDED AUDIENCE : CSE, ECE, EE


    PRE-REQUISITES : Basic concepts in digital circuit design, Familiarity with a programming language like
    C or C++
    INDUSTRIES APPLICABLE TO : Intel, Cadence, Mantor Graphics, Synopsys, Xilinx

    COURSE OUTLINE :
    The course will introduce the participants to the Verilog hardware description language. It will help them to learn
    various digital circuit modeling issues using Verilog, writing test benches, and some case studies.

    ABOUT INSTRUCTOR :
    Prof. Indranil Sengupta has obtained his B.Tech., M.Tech. and Ph.D. degrees in Computer Science and Engineering
    (CSE) from the University of Calcutta. He joined the Indian Institute of Technology, Kharagpur, as a faculty member in
    1988, in the Department of CSE, where he is presently a full Professor. He had been the former Heads of the
    Department of Computer Science and Engineering and also the School of Information Technology of the Institute.
    He has over 28 years of teaching and research experience. He has guided 22 PhD students, and has more than 200
    publications to his credit in international journals and conferences.

    COURSE PLAN :
    Week 01 : Introduction to digital circuit design flow
    Week 02 : Verilog variables, operators and language constructs
    Week 03 : Modeling combinational circuits using Verilog
    Week 04 : Modeling sequential circuits using Verilog
    Week 05 : Verilog test benches and design simulation
    Week 06 : Behavioral versus structural design modeling
    Week 07 : Behavioral versus structural design modeling
    Week 08 : Processor design using Verilog

    134

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