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Product Description AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32
Product Description AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32
com
Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
• Internal High-speed Flash
– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual
Plane (AT91SAM7SE512)
– 256 Kbytes (AT91SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes Product
Single Plane (AT91SAM7SE256)
– 32 Kbytes (AT91SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes Description
Single Plane (AT91SAM7SE32)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed AT91SAM7SE512
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, AT91SAM7SE256
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production AT91SAM7SE32
• 32 Kbytes (AT91SAM7SE512/256) or 8 Kbytes (AT91SAM7SE32) of Internal
High-speed SRAM, Single-cycle Access at Maximum Speed
• One External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash® and
ECC-enabled NAND Flash
• Memory Controller (MC) Advance
– Embedded Flash Controller
– Memory Protection Unit Information
– Abort Status and Misalignment Detection
• Reset Controller (RSTC) Summary
– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout
Detector
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL
• Power Management Controller (PMC)
– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and
Idle Mode
– Three Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
Protected
• Debug Unit (DBGU)
– Two-wire UART and Support for Debug Communication Channel interrupt, NOTE: This is a summary document.
Programmable ICE Access Prevention The complete document is available on
• Periodic Interval Timer (PIT) the Atmel website at www.atmel.com.
– 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System 6222AS–ATARM–23-Oct-06
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– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
• Three Parallel Input/Output Controllers (PIO)
– Eighty-eight Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– Schmitt Trigger on All inputs
• Eleven Peripheral DMA Controller (PDC) Channels
• One USB 2.0 Full Speed (12 Mbits per second) Device Port
– On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1
• One Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• One Two-wire Interface (TWI)
– Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported
– General Call Supported in Slave Mode
• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA™
– Default Boot program
– Interface with SAM-BA Graphic User Interface
• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins
• Four High-current Drive I/O lines, Up to 16 mA Each
• Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
– 1.8V or 3,3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
– 1.8V VDDCORE Core Power Supply with Brownout Detector
• Fully Static Operation: Up to 48 MHz at 1.65V and 85°C Worst Case Conditions
• Available in a 128-lead LQFP Green Package, or a 144-ball LFBGA Green Package
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1. Description
Atmel's AT91SAM7SE Series is a member of its Smart ARM Microcontroller family based on the
32-bit ARM7™ RISC processor and high-speed Flash memory.
• AT91SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM.
• AT91SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM.
• AT91SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM.
It also embeds a large set of peripherals, including a USB 2.0 device, an External Bus Interface
(EBI), and a complete set of system functions minimizing the number of external components.
The EBI incorporates controllers for synchronous DRAM (SDRAM) and Static memories and
features specific circuitry facilitating the interface for NAND Flash, SmartMedia and
CompactFlash.
The device is an ideal migration path for 8/16-bit microcontroller users looking for additional per-
formance, extended memory and higher levels of system integration.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to mounting. Built-in lock bits and a secu-
rity bit protect the firmware from accidental overwrite and preserve its confidentiality.
The AT91SAM7SE Series system controller includes a reset controller capable of managing the
power-on sequence of the microcontroller and the complete system. Correct device operation
can be monitored by a built-in brownout detector and a watchdog running off an integrated RC
oscillator.
By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of
peripheral functions, including USART, SPI, External Bus Interface, Timer Counter, RTT and
Analog-to-Digital Converters on a monolithic chip, the AT91SAM7SE512/256/32 is a powerful
device that provides a flexible, cost-effective solution to many embedded control applications.
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2. Block Diagram
Figure 2-1. AT91SAM7SE512/256/32 Block Diagram Signal Description
TDI ICE
TDO JTAG ARM7TDMI
TMS Processor
TCK
SCAN
JTAGSEL
1.8V VDDIN
Voltage GND
System Controller Regulator VDDOUT
TST
FIQ
Memory Controller VDDCORE
AIC
PIO
IRQ0-IRQ1 Embedded SRAM VDDIO
Address
Flash 32 Kbytes (SE512/256)
Controller Decoder or
DRXD PDC 8 Kbytes (SE32)
DTXD DBGU
PDC Abort Misalignment
Status Detection
PCK0-PCK2
Flash VDDFLASH
PLLRC PLL Memory Protection 512 Kbytes (SE512)
Unit 256 Kbytes (SE256) ERASE
XIN OSC PMC 32 Kbytes (SE32)
XOUT
RCOSC
Peripheral Bridge
VDDFLASH
BOD ROM
VDDCORE Reset Peripheral DMA
POR Controller Controller
VDDCORE PGMRDY
11 Channels PGMNVALID
Fast Flash PGMNOE
NRST Programming PGMCK
Interface PGMM0-PGMM3
PGMD0-PGMD15
PIT APB PGMNCMD
PGMEN0-PGMEN1
WDT
SAM-BA
RTT
PIOA PIOC
D[31:0]
A0/NBS0
PIOB EBI A1/NBS2
A[15:2], A[20:18]
A21/NANDALE
A22/REG/NANDCLE
A16/BA0
RXD0 PDC A17/BA1
TXD0
SCK0 USART0 NCS0
RTS0 CompactFlash NCS1/SDCS
CTS0 PDC NAND Flash NCS2/CFCS1
RXD1 PDC NCS3/NANDCS
TXD1 PIO NRD/CFOE
SCK1 NWR0/NWE/CFWE
RTS1 USART1 NWR1/NBS1/CFIOR
CTS1 SDRAM NBS3/CFIOW
DCD1 SDCKE
Controller RAS
DSR1
DTR1 CAS
RI1 PDC SDWE
NPCS0 PDC SDA10
NPCS1 CFRNW
NPCS2 SPI Static Memory NCS4/CFCS0
PIO
NPCS3 NCS5/CFCE1
MISO Controller NCS6/CFCE2
MOSI NCS7
SPCK PDC NANDOE
NANDWE
TCLK0 NWAIT
TCLK1
Timer Counter ECC
TCLK2 Controller SDCK
TIOA0 TC0
TIOB0
Transciever
ADTRG PDC
AD0 PWM0
AD1 PWM1
AD2
PWMC PWM2
AD3 PWM3
ADC PDC TF
PIO
AD4
AD5 TK
AD6 TD
SSC RD
AD7
RK
ADVREF PDC RF
TWI TWD
TWCK
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3. Signal Description
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4. Package
The AT91SAM7SE512/256/32 is available in:
• 20 x 14 mm 128-lead LQFP package with a 0.5 mm lead pitch.
• 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch
102 65
103 64
128 39
1 38
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11
10
9
8
7
6
5
4
3
2
1
A B C D E F G H J K L M
Ball A1
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5. Power Considerations
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• One external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and
GND as close to the chip as possible.
• One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and
GND.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source voltage drop. The input decoupling capacitor should be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
VDDFLASH
3.3V Voltage
Regulator
VDDOUT
VDDCORE
VDDPLL
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8. Memories
• 512 Kbytes of Flash Memory (AT91SAM7SE512)
– dual plane
– two contiguous banks of 1024 pages of 256 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming time: 6 ms, including page auto-erase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 write cycles, 10-year data retention capability
– 32 lock bits, each protecting 32 lock regions of 64 pages
– Protection Mode to secure contents of the Flash
• 256 Kbytes of Flash Memory (AT91SAM7SE256)
– single plane
– one bank of 1024 pages of 256 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming time: 6 ms, including page auto-erase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 cycles, 10-year data retention capability
– 16 lock bits, each protecting 16 lock regions of 64 pages
– Protection Mode to secure contents of the Flash
• 32 Kbytes of Flash Memory (AT91SAM7SE32)
– single plane
– one bank of 256 pages of 128 bytes
– Fast access time, 30 MHz single-cycle access in Worst Case conditions
– Page programming time: 6 ms, including page auto-erase
– Page programming without auto-erase: 3 ms
– Full chip erase time: 15 ms
– 10,000 cycles, 10-year data retention capability
– 8 lock bits, each protecting 8 lock regions of 32 pages
– Protection Mode to secure contents of the Flash
• 32 Kbytes of Fast SRAM (AT91SAM7SE512/256)
– Single-cycle access at full speed
• 8 Kbytes of Fast SRAM (AT91SAM7SE32)
– Single-cycle access at full speed
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A first level of address decoding is performed by the Memory Controller, i.e., by the implementa-
tion of the Advanced System Bus (ASB) with additional features.
Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are
directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The
area 0 is reserved for the addressing of the internal memories, and a second level of decoding
provides 1M byte of internal memory area. The area 15 is reserved for the peripherals and pro-
vides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
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0x0000 0000
ROM Before Remap
1 M Bytes
0x000F FFFF SRAM After Remap
0x0010 0000
Internal FLASH 1 M Bytes
0x001F FFFF
0x0020 0000
256M Bytes Internal SRAM 1 M Bytes
0x002F FFFF
0x0030 0000
Internal ROM 1 M Bytes
0x003F FFFF
0x0040 0000
252 M Bytes
Undefined Areas
(Abort)
0x0FFF FFFF
0x0000 0000
Flash Before Remap 1 M Bytes
0x000F FFFF SRAM After Remap
0x0010 0000
Internal FLASH 1 M Bytes
0x001F FFFF
0x0020 0000
256M Bytes Internal SRAM 1 M Bytes
0x002F FFFF
0x0030 0000
Internal ROM 1 M Bytes
0x003F FFFF
0x0040 0000
252 M Bytes
Undefined Areas
(Abort)
0x0FFF FFFF
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The Flash benefits from the integration of a power reset cell and from the brownout detector.
This prevents code corruption during power supply changes, even in the worst conditions.
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The security bit can only be enabled through the Command “Set Security Bit” of the EFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and
after a full flash erase is performed. When the security bit is deactivated, all accesses to the
flash are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal
operation. However, it is safer to connect it directly to GND for the final application.
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9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power,
time, debug and reset.
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space,
between addresses 0xFFFF F000 and 0xFFFF FFFF.
Figure 9-1 on page 29 shows the System Controller Block Diagram.
Figure 8-1 on page 22 shows the mapping of the User Interface of the System Controller periph-
erals. Note that the Memory Controller configuration user interface is also mapped within this
address space.
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nirq
irq0-irq1
Advanced nfiq
fiq
Interrupt
proc_nreset ARM7TDMI
periph_irq[2..18] Controller
PCK
int
pit_irq debug
rtt_irq
wdt_irq
dbgu_irq
pmc_irq power_on_reset
rstc_irq
force_ntrst
MCK dbgu_irq
periph_nreset
Debug
Unit force_ntrst
dbgu_rxd dbgu_txd
security_bit
MCK Periodic
debug Interval pit_irq
periph_nreset Timer
SLCK flash_poe
Real-Time rtt_irq
Embedded
periph_nreset Timer flash_wrdis Flash
cal
SLCK
debug Watchdog wdt_irq gpnvm[0..2]
idle Timer
proc_nreset
cal wdt_fault
gpnvm[0] gpnvm[1]
WDRPROC
MCK
en flash_wrdis bod_rst_en Memory
BOD proc_nreset Controller
power_on_reset
jtag_nreset Reset periph_nreset
Controller proc_nreset Voltage
POR flash_poe Regulator standby
Mode Voltage
rstc_irq Controller Regulator
NRST
cal
SLCK
SLCK
RCOSC periph_clk[2..18] UDPCK
pck[0-3] periph_clk[11]
USB Device
XIN Power
OSC MAINCK periph_nreset Port
Management PCK
XOUT Controller UDPCK periph_irq[11]
MCK
usb_suspend
PLLRC PLL PLLCK
pmc_irq
int
periph_nreset idle
periph_clk[4..18]
usb_suspend
periph_nreset
Embedded
Peripherals
periph_nreset periph_irq{2-3]
periph_clk[2-3] irq0-irq1
periph_irq[4..18]
dbgu_rxd PIO fiq
Controller dbgu_txd
in
PA0-PA31
out
PB0-PB31 enable
PC0-PC29
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Clock Generator
XIN
Main Main Clock
Oscillator MAINCK
XOUT
Status Control
Power
Management
Controller
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Processor PCK
Clock
Controller
int
Master Clock Controller
Idle Mode
SLCK
MAINCK Prescaler
/1,/2,/4,...,/64 MCK
PLLCK
Peripherals periph_clk[2..14]
Clock Controller
ON/OFF
SLCK
MAINCK Prescaler
pck[0..2]
PLLCK /1,/2,/4,...,/64
Divider
PLLCK UDPCK
/1,/2,/4
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• Synchronous output, provides Set and Clear of several I/O lines in a single write
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10. Peripherals
6 US0 USART 0
7 US1 USART 1
8 SSC Synchronous Serial Controller
12 TC0 Timer/Counter 0
13 TC1 Timer/Counter 1
14 TC2 Timer/Counter 2
(1)
15 ADC Analog-to Digital Converter
16-28 reserved
Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The Sys-
tem Controller is continuously clocked. The ADC clock is automatically started for the first
conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
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10.9 USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode
– 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB or LSB first
– Optional break generation and detection
– By 8 or by 16 over-sampling receiver frequency
– Hardware handshaking RTS - CTS
– Modem Signals Management DTR-DSR-DCD-RI on USART1
– Receiver time-out and transmitter timeguard
– Multi-drop Mode with address generation and detection
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
– NACK handling, error counter with repetition and iteration limit
• IrDA® modulation and demodulation
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
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Revision History
Change Request
Doc. Rev Comments Ref.
First issue
622AS Revised Memories with condensed mapping.
#2709
Added Package Outlines and 144-ball LFBGA pin and ordering information.
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Literature Requests
www.atmel.com/literature
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