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MICROFABRICATION PROCESSES
MEMS fall into three general classifications; bulk micromachining, surface micromachining and high-aspect-ratio
micromachining (HARM), which includes technology such as LIGA (a German acronym from Lithographie,
Galvanoformung, Abformung translated as lithography, electroforming and moulding).
MEMS fabrication, by comparison, uses high volume IC style batch processing that involves the addition or
subtraction of two dimensional layers on a substrate (usually silicon) based on photolithography and chemical
etching. As a result, the 3D aspect of MEMS devices is due to patterning and interaction of the 2D layers. Additional
layers can be added using a variety of thin-film and bonding techniques as well as by etching through sacrificial
‘spacer layers’. Figure 1.1 shows the potential complexity of a MEMS system by the addition of independent
structural layers.

Figure 1.1 MEMS device complexity by structural layers

1.1 Bulk Micromachining
Bulk micromachining involves the removal of part of the bulk substrate. It is a subtractive process that uses wet
anisotropic etching or a dry etching method such as reactive ion etching (RIE), to create large pits, grooves and
channels. Materials typically used for wet etching include silicon and quartz, while dry etching is typically used with
silicon, metals, plastics and ceramics.
1.2 Surface Micromachining
Surface micromachining involves processing above the substrate, mainly using substrate as a foundation layer on
which to build. It was initiated in the 1980’s and is the newest MEMS production technology. Material is added to
the substrate in the form of layers of thin films on the surface of the substrate (typically again a silicon wafer). These
layers can either be structural layers or act as sacrificial layers which are later to be removed.
1.3 Materials for Micromachining
a) Substrates
The most common substrate material for micromachining is silicon. It has been successful in the microelectronics
industry and will continue to be in areas of miniaturization for several reasons:

i) Silicon is abundant, inexpensive, and can be processed to unparalleled purity

ii) Silicon’s ability to be deposited in thin films is very amenable to MEMS

iii) High definition and reproduction of silicon device shapes using photolithography are perfect for high
levels of MEMS precision
iv) Silicon microelectronics circuits are batch fabricated (a silicon wafer contains hundreds of identical chips
not just one)

Other crystalline semiconductors including germanium (Ge) and gallium arsenide (GaAs) are used as substrate
materials due to similar inherent features, but silicon is distinguished from other semiconductors in that it can be
readily oxidized to form a chemically inert and electrically insulating surface layer of SiO2 on exposure to steam.

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Following are the bulk & surface machining process used in MEMS:
1.4 Photolithography
The goal of photolithography is to produce fine features on wafer surfaces. A most common lithography process
involves depositing photo-sensitive chemicals (called photo resists, or simply resists) on a silicon wafer, exposing it
with light through a mask, and removing (develop) photo resist material that has been modified by light. Following
are the steps in lithography:
Step A: Coating of a wafer with photo resist through spin coating (Figure1.2)
A wafer is held on a rotating stage. Photo resist is applied to the center of the wafer at rest position. The wafer is
then spun at high speed, causing the photo resist to move towards the edge of the wafer under centrifugal forces.
After the wafer spinning is stopped, a uniform thin layer of photo resist is coated on the front surface of a wafer.
Process variables include the wafer spinning speed, the viscosity of the resist, and the types of resists. Typical
thickness of photo resist is generally 1–10 mm.
Step B: Preparation of a mask with opaque layers (Figure1.3)
A mask, consisting of a transparent substrate (e.g.,glass or quartz) with opaque features, are brought close to the
resist-coated wafer (step a). High energy, collimated light rays strikes the mask-wafer assembly. Resist regions that
are not covered by opaque features are exposed, changing the chemical composition of the resist.
Step C: Selective removal of photo resist
For positive resist, the exposure by light causes the resist to be more soluble in a wet chemical developer such as
hydrochloric acid (step c). This allows the opaque features on the mask to be faithfully transferred to the wafer (step
d). For negative photo resist, areas exposed to light are retained while the areas under opaque layer are dissolved in
the chemical. The resulting photo resist pattern is either the positive or negative image of the original pattern of the
photo mask.

Figure 1.2: Process steps of photoresist spin coating. Figure 1.3 Process flow for patterning photoresist with
a photomask.:
1.5 Thin Film Deposition
Functional materials, conductors and insulators can be incorporated on a wafer through additive deposition process.
One such deposition process is direct transfer of the material from a source to the wafer surface in an atom-by-atom,
layer-by-layer fashion (Figure 1.4). Examples include metal evaporation and metal sputtering. Both the process are
generally conducted in a low pressure environment so that atoms may travel from the source to the wafer surface
without interruptions caused by air molecules.

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The materials to be applied can be pure atomic elements including both metals and non metals, or can be molecules
such as oxides and nitrides. The object(Si wafer in this case) to be coated is referred to as the substrate. Metal
Evaporation involves heating a solid material inside a high vacuum chamber, taking it to a temperature which
produces some vapor pressure inside the vacuum. This evaporated material now constitutes a vapor stream, which
traverses the chamber and hits the substrate, sticking to it as a coating or film.Since, in most instances of Thermal
Evaporation processes the material is heated to its melting point and is liquid, it is usually located in the bottom of
the chamber in crucible. The vapor then rises above this bottom source, and the substrates are held inverted with
appropriate fixtures at the top of the chamber. The surfaces intended to be coated are thus facing down toward the
heated source material to receive their coating. The metal can be transferred either by heating it (evaporation) or by
bombarding it with high-energy ions (sputtering).The achieved thickness is proportional to the power and time.

Figure 1.4: A schematic diagram of the metal evaporation equipment.

1.5.2 Thin Film Deposition by Chemical Vapor Deposition

The working principle of CVD involves the flow of a gas with diffused reactants over a hot substrate surface. The
gas that carries the reactants is called the carrier gas. Two or more active species arrive at the vicinity of the wafer
surface (step a). They react under favorable conditions (with energy provided by heating or plasma).The reaction of
these species produces a solid phase, which is absorbed onto the nearby wafer surface (step b). The byproducts of
the reaction (if any) may be removed by the surrounding media. Continuous reaction causes a layer of material to be
built on the wafer surface (step c).Typically the average thickness of thin film deposited by CVD, evaporation or
sputtering is below 1 mm.
Thin silicon-di-oxide films can be produced at the surface of silicon by the CVD process.There are a number of
chemical reactants that could be used to deposit silicon-di-oxide films on the silicon substrates. These include SiCl4,
SiBr4 & SiH2Cl2.The carrier gases include O2, NO, NO2 and CO2 with H2.The chemical reaction in the process can
be 𝑆𝑖𝐻𝟒 + 𝑂2 → 𝑆𝑖𝑂2 + 2𝐻2.

Figure 1.5: A process of chemical reactive deposition

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Ammonia is the common carrier gas for depositing silicon nitride on silicon substrates. Reactions include:
3𝑆𝑖𝐻4 + 4𝑁𝐻3 → 𝑆𝑖3𝑁4 + 12𝐻2
3𝑆𝑖𝐶𝑙4 + 4𝑁𝐻3 → 𝑆𝑖3𝑁4 + 12𝐻𝐶𝑙
1.6 Thermal Oxidation of Silicon
Silicon dioxide is an important insulating layer for microelectronics and MEMS. One prominent
method of forming a high-quality silicon-dioxide layer is by reacting silicon wafers with oxygen atoms at high
temperatures (e.g., 900°C and above).Wafers are often placed inside a heated quartz tube (Figure 1.6). On the
surface of the wafer, a layer of oxide is formed and separates the interior silicon from the oxygen atoms. Following
are steps in process of thermal oxidation explained at the atomic level (Figure 1.7).
(a) Oxygen atoms arrive at the surface of bare silicon.
(b) Reaction between oxygen and silicon turns part of the surface into silicon dioxide.
(c) Gradually, a continuous layer of silicon dioxide is formed, separating the oxygen atmosphere with the silicon
substrate.
(d) Newly arrived oxygen species must diffuse across the oxide layer in order to react with silicon atoms on the
other side of the oxide. The reaction rate is limited by the diffusion process.

Figure 1.6 : Thermal Oxidation of Silicon Figure 1.7: Thermal oxidation at atomic
level
1.7 Etching Methods
In order to form a functional MEMS structure on a substrate, it is necessary to etch the thin films previously
deposited on the substrate itself. In general, there are two classes of etching processes:
a) Wet etching where the material is dissolved when immersed in a chemical solution
b) Dry etching where the material is sputtered or dissolved using reactive ions or plasma.

1.7.1 Wet etching : Wet etching describes the removal of material by immersing it (typically a silicon wafer) in a
liquid bath of a chemical etchant. These etchants can be isotropic or anisotropic.

Isotropic etchants etch the material at the same rate in all directions, and consequently remove material under the
etch masks at the same rate as they etch through the material; this is known as undercutting (Figure 1.8). Example of
isotropic silicon etch is HNA, which comprises a mixture of hydrofluoric acid (HF), nitric acid (HNO 3) and acetic
acid (CH3 COOH).

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Anisotropic etchants etch faster in a preferred direction. Potassium hydroxide (KOH) is the most common
anisotropic etchant as it is relatively safe to use. Structures formed in the substrate are dependent on the crystal
orientation of the substrate or wafer. Anisotropic etchants progress rapidly in the crystal direction perpendicular to
the (110) plane and less rapidly in the direction perpendicular to the (100) plane leading to different etch rates in
different directions.
A thin film with a starting thickness of tf0 is covered by a masking material with an initial
thickness of tm0. The wafer is exposed to an etchant. At a given intermediate time t, the thickness of the film
becomes tf, and the thickness of the mask becomes tm. Hence
tf0 - tf = t * etch-rate-on-film
tm0 - tm = t * etch-rate-on-mask.

Figure 1.8: Wet etching on a thin film.

1.7.2 Dry etching: Plasma Etching and Reactive Ion Etching

Since the process does not involve wet chemicals, Plasma etching is often referred to as dry etching. The etching is
carried out in specialized process equipment called the plasma etcher. A chamber with two opposing electrodes is
filled with a chemically active gas species. The process pressure is very low (perhaps 1/2000th of atmosphere
pressure). Inside the plasma etcher,a plasma is struck in the gas mixture using a power source, breaking the gas
molecules into ions.
The ions are accelerated towards, and react at the surface of the material being etched, forming another gaseous
material. This is known as the chemical part of reactive ion etching.
There is also a physical part which is similar in nature to the sputtering deposition process. If the ions have high
enough energy, they can knock atoms out of the material to be etched without a chemical reaction. Both physical
and chemical processes may be present at the same time. In general, physical etching is more directional and
anisotropic whereas chemical etching is isotropic.
If the electrode holding the wafer is grounded, the etching is called plasma etching. If the wafer is fixed to an
electrode on which AC bias is applied, the etching is called reactive ion etching.
Compared with plasma etching, reactive ion etching is more physical in nature and its etch rate
distribution is more anisotropic.

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Figure: 1.9 A schematic diagram of plasma etching.

1.8 Doping
Doping is the process of adding dopant atoms into the semiconductor substrate in order to
change the electrical characteristics of the substrate. The dopants can be placed on the surface of the wafer or
precisely injected into the silicon lattice using the ion implantation method. A schematic diagram of the process used
for doping selective regions of silicon with dopant atoms is shown in Figure 1.10. The desired shape of the resistor
is shown in the top-most figure. The resistor should be moderately where as the two contact ends of the resistor
should be heavily doped in order to form ohmic contacts with metal leads. A mask shield is first deposited in step(a)
and patterned to form windows. The wafer is exposed to a source of dopant, which cannot penetrate the mask shield
layer but can enter the silicon via the open windows. The arms of the resistor are then patterned (in step b) for
performing a lower dose doping. Finally, metal leads are deposited and patterned to connect with the resistor (step c).
Though the movement of individual dopant atoms is random, the overall population of dopant atoms moves from
high-concentration regions to low concentration ones. This process is called thermal diffusion. The diffusion of
dopants in silicon follows Fick’s diffusion law for unsteady state, which states that the concentration, “C”, is a
𝑑𝑐 𝑑2 𝑐
function of the time (t) and spatial location (x). = 𝐷( )
𝑑𝑡 𝑑2 𝑥

Figure 1.10 Two step diffusion doping.

Limitations in the process are: (1) existing doping procedure can only be performed on top surfaces of wafers; (2)
high temperature encountered by a wafer during a process after the doping process, can cause dopant redistribution
and changes of electrical characteristics.
1.9 Wafer Dicing

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Wafer dicing is the process by which die are separated from a wafer of semiconductor following the processing of
the wafer. A high-speed rotating dicing saw blade is used to cut trenches in silicon wafer. The cutting process, being
mechanical in nature, produces particles. Water is sprayed onto the wafer to lubricate and remove heat. The thinned
trenches allow silicon to be broken off easily without fracturing. This method can damage almost all MEMS
mechanical components because of the particles, vibration, and water.
Laser ablation has also been used to dice wafers instead of dicing saw which uses laser permeable to the silicon
wafer to create internal modified lines invisible on the surface. This technology would benefit MEMS device
package immensely. All methods are typically automated to ensure precision and accuracy.

Figure 1.11 A dicing saw blade cutting trenches in silicon wafer to facilitate die separation.
1.10 Wafer Bonding
Wafer bonding is a micromachining method that is analogous to welding in the macroscale world and involves the
joining of two (or more) wafers together to create a multi-wafer stack. There are three basic types of wafer bonding
including: direct or fusion bonding; anodic bonding; and bonding using an intermediate layer.
In general, all bonding methods require substrates that are very flat, smooth, and clean, in order for the wafer
bonding to be successful and free of voids.
Direct or fusion bonding is typically used to mate two silicon wafers together or alternatively to mate one silicon
wafer to another silicon wafer that has been oxidized. Direct wafer bonding can be performed on other combinations,
such as bare silicon to a silicon wafer with a thin-film of silicon nitride on the surface as well.
In anodic bonding a silicon wafer is bonded to a Pyrex wafer using an electric field and elevated temperature. The
two wafers can be pre-processed prior to bonding and can be aligned during the bonding procedure.
In intermediate layer bonding, various polymers can be used as intermediate layers to bond wafers including epoxy
resins, photoresists, polyimides, silicones, etc. This technique is commonly used during various fabrication steps in
MEMS such as when the device wafer becomes too fragile to handle without mechanical support.
(Extra Information:The mechanism by which anodic bonding works is based on the fact that Pyrex has a high
concentration of Na+ ions; a positive voltage applied to the silicon wafer drives the Na+ ions from the Pyrex glass
surface, thereby creating a negative charge at glass surface. The elevated temperature during the bonding process
allows the Na+ ions to migrate in the glass with relative ease. When the Na+ ions reach the interface, a high field
results between silicon and glass, and this combined with the elevated temperatures fuses the two wafers together.
As with direct wafer bonding, it is imperative that the wafers are flat, smooth, and clean and that the anodic bonding
process is performed in a very clean environment. An advantage of this process is that Pyrex 7740 has a thermal

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expansion coefficient nearly equal to silicon and therefore there is a low value of residual stress in the layers.
Anodic bonding is a widely used technique for MEMS packaging.)
1.11 THE MICROELECTRONICS FABRICATION PROCESS FLOW
A basic understanding of the fabrication technology for integrated circuit, which precedes that
of MEMS in history, is necessary to understanding the micromachining process.
A fabrication process for integrated circuits generally involves many steps of material deposition, material removal,
and patterning, as illustrated in the following example. A generic micro fabrication process for a transistor, the
building block of modern integrated circuits, is illustrated in Figure 1.12. The cycles of deposition-lithography-
etching are repeated to build the IC. In this particular case, six major cycles transforms a bare silicon wafer to one
with a metal-oxide-semiconductor (MOS) transistor on the front surface. Steps 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, and
8.0, on the left most column, are major milestones in the process, whereas process steps x.y are steps that leads to the
next major milestone.
The nature of each step is clearly marked. Letters D, L, E, and M denotes deposition, lithography
(photo exposure and development), etching, and modification/treatment of materials.
A brief description of each step is presented below:
Step 1.0. The figure depicts the cross section of a starting bare silicon wafer. The wafer thickness is not drawn to
scale.
Step 2.0. A layer of oxide is deposited. The oxide is patterned using the following subsequent
steps (2.1 through 2.3).This oxide layer is here only to serve a transitional purpose.
(This point will become obvious later.)
2.1. A photosensitive resist layer is deposited on top of the oxide by spin coating.
2.2. The photosensitive resist is lithographically exposed and developed.
2.3. The photo resist is used as a mask for etching the oxide.
Step 3.0. The photo resist is removed using organic solvents. The patterned oxide is used as a mask against impurity
doping performed in step 3.1 through 3.3.
3.1. A layer of material containing dopant impurities is deposited.
3.2. The wafer is thermally treated, causing the dopant to diffuse into silicon in areas not covered by the oxide.
3.3. The dopant-source layer deposited in step 3.1 is removed.
Step 4.0. The oxide is removed. Note that many steps and layers of materials are involved to transform a bare wafer
(step 1.0) to a wafer with dopant in selective places (step 4.0).
Additional processes (steps 4.1 through 4.4) are then performed to produce another layer
of patterned oxide.
4.1. Another layer of silicon oxide is grown.
4.2. A photosensitive resist is deposited.
4.3. The resist is lithographically patterned.
4.4. Using the resist as a mask, the oxide is etched.
Step 5.0. The resist deposited in step 4.2 is removed. From Step 4.0 to 5.0, the major difference
is oxide cover in undoped regions. An oxide layer is then deposited and patterned (5.1. through 5.4).
5.1. A very thin oxide is grown. This so-called gate oxide layer must have very high quality and are free of
contaminants and defects.

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5.2. A resist layer is again deposited.

5.3. The resist is lithographically patterned.
5.4. The resist serves as a mask for selectively etching the gate oxide.

Figure 1.12 : Fabrication process for an integrated circuit.

Step 6.0. The resist deposited in step 5.2 is removed. The active regions not covered by oxide will provide electrical
contact to metal.A gate electrode, made of polycrystalline silicon,is then deposited and patterned in steps 6.1
through 6.4.
6.1. A layer of polycrystalline (doped) silicon is deposited.
6.2. A layer of photosensitive resist is deposited.
6.3. The resist is patterned lithographically.
6.4. The resist serves as a mask for etching the underlying polycrystalline silicon selectively.
Step 7.0. The resist is removed by using organic solvents.The difference between steps 6.0 to 7.0 is the addition of
polycrystalline silicon. Each transistor must be connected with each other and to the outside through low-resistivity
metal wires. The metal wires are made in steps 7.1 through 7.3.
7.1. A layer of metal is deposited.
7.2. and 7.3.The metal is coated with resist and lithographically patterned.
7.4. The resist serves as a mask for etching the metal.
Step 8.0. The resist is removed, realizing a complete field effector transistor. The process used in the industry
follows the basic flow diagramed in Figure 2.18 but involves more detailed steps for quality assurance, functional

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enhancement, and for increasing the yield and repeatability. Many more steps may incur after step 8.0 as well. A
complete process run from the start to the finish may take 3 months, and 20–40 mask plates.
1.12 SILICON-BASED MEMS PROCESSES
MEMS process for a pressure sensor (Figure 1.13) is shown and processing steps explained. The process involves
two wafers—a bottom wafer is etched to form a cavity whereas a top wafer is used to make the membrane. A
description for each step in the diagram is as follows.

Figure 1.13: Process for a micro machined pressure sensor as an example.

Step a. The process starts with a bare silicon wafer. To create desired cavity shape, the wafer must be of a certain
crystallographic orientation. The wafer is cleaned thoroughly to remove any large particles, dirt particles, and
invisible organic residues. A combined mechanical wash and oxidizing acid bath may be used, followed by a rinse
by ultrapure water.
Step b. The cleaned wafer is placed inside a high-temperature furnace filled with running oxygen gas or water vapor.
Oxygen atoms present in the air will react with silicon to form a protective silicon dioxide thin film. The oxide is
grown on both sides of the wafer as well as on the edges.
step c. the wafer is removed from the furnace and cooled to room temperature. it will be very clean, because any
organic molecules would have been decomposed in the high temperature oxidation step. a layer of thin film photo
resist is deposited on the front surface of the wafer. (a chemical called hexamethyldisilazane, or hdms, is sometimes
spin- or vapor-coated to help increase the adhesion between the photo resist and an oxide surface.) the photo resist is
typically spin coated. the wafer is baked in a convection oven to remove some portion of the solvent from the photo
resist (pr) layer to establish firmness. this step is generally called “soft bake”.
step d. the photo resist is exposed through a mask with a high-energy radiation (such as ultra violet ray, electron
beam, or x-ray).the entire wafer is then placed inside a developing solution (often called developer) that removes
loosely bound photosensitive polymer.
step e. the photo resist needs to be baked again, this time at a higher temperature and often for a longer duration than
the soft bake. this second baking step, called “hard bake”, removes remaining solvents and makes photo resist that
remains on the wafer stick to the wafer even stronger.
step f. the photoresist is removed using an organic solvent etchant such as acetone (at room temperature or elevated
temperatures). the organic solvent does not etch the oxide and the silicon.

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step g. the silicon wafer is immersed in a wet silicon etchant, which does not attack the silicon oxide. only the
silicon in the open oxide window is etched, resulting in a cavity with sidewalls defined by crystallographic planes.
the cavity may reach the other side of the wafer if the open window is large enough for the given wafer thickness.
step h. the wafer at the end of stage (g) is tilted to provide a clear view of the through wafer cavity.
step i. a second silicon wafer is firmly bond to the front side of the bottom wafer processed through step (g).
step j. the bonded top wafer is thinned by using mechanical polishing or chemical etching.the remaining thickness
of the top wafer determines the thickness of the membrane. thin membranes are desired to have high sensitivity.
step k. strain sensors are then made on the prepared membrane. a thin film layer (e.g.oxide) is deposited and
patterned. it serves as a barrier layer to ion implantation. areas on the silicon wafer hit directly by energetic dopant
ions will become doped and form a piezoresistor, which changes its resistance upon applied stress due to membrane
bending under pressure difference.
1.13 PROCESS SELECTION AND DESIGN
Process selection and design is crucial for MEMS. Successful process design accommodates desired materials,
enables high yield, and realizes low-cost and high-performance devices.
Points of Consideration for Deposition Processes
The following characteristics should be carefully evaluated for each deposition process.
1. Ultimate thickness: There is practical limits to the thickness of films that can be deposited.Excessive thickness
may take too much time, or may cause stress build-up to the extent of causing self-destruction.
2. Deposition rate and control factors: High deposition speed certainly results in faster processes, but not always
better-quality materials.
3. Temperature of the process.
4. Deposition Profile: Various deposition and etching profiles are available associated with different methods and
processing conditions. It is rather difficult to produce all profiles.
Points of Consideration for Etching Processes
The following is a list of important issues to consider when evaluating an etching process.
1. Etch rate. The speed of material removal is important. A higher etch rate translates into shorter etching time and
greater manufacturing throughput.
2. End point detection. Determining that a process step has finished is not as easy as it may sound.
3. Etch rate selectivity. Selectivity is defined as the ratio between the etch rate of the targeted material and that of
non intended materials, such as mask layers. The selectivity ratio should be as large as possible. For example, an
etchant should not attack the mask at all in the ideal situation.
4. Processing temperature. Process steps with high temperature limit the selection of materials. The etch rate of
many systems are temperature dependant.
5. Sensitivity to overtime etch. Because of non uniform etch rate over a wafer, some structures on a wafer are
finished earlier than others. Hence over-time etch is unavoidable. A robust process that is insensitive to over etch is
always desirable.
6. Safety and cost of etchants. Certain etchants are hazardous to health when inhaled or get into contact with skin. It
is important to know the material safety issues associated with each etchant.

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7. Surface finish and defects. Different etching methods and materials result in varying degrees of smoothness of
surfaces and crack densities. It is important to know the degree of smoothness with various etching methods and
ways to improve the smoothness or artificially roughen a surface if necessary.

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