PENTIUM PROCESSOR FAMILY

Benjamin Nicomedes
For-Ian Sandoval
Presenters
OVERVIEW: PENTIUM PROCESSOR
• a brand used for a series of x86-
compatible microprocessors
• produce by Intel
• a consumer-level product

• Greek and Latin words pente + ium

• used the fifth generation microarchitecture
• current Pentium processors only share the
name but are in fact based on the same
processor chips
HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS

• 32-bit microprocessor introduced

by Intel in 1993
• contains more than 3
million transistors
• roots in the Intel486(TM) processor
• ''Pentium processor'' refers to a family of
microprocessors that share a common
architecture and instruction set
HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS

• The 1st Pentium processors (P5

variety) was fabricated in 0.8
micron bipolar complementary
metal oxide semiconductor
(BiCMOS) technology
• Pentium Pro, Pentium II and Pentium III (P6)
• Pentium 4 & Pentium D (Netburst)
• Pentium M (P6-Based)
• Pentium Dual-Core (P6-Based & Core)
HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS

• Pentium (Nehalem, Sandy

Bridge, Ivy Bridge Haswell and
Broadwell)
LIST OF INTEL PENTIUM PROCESSORS
EVOLUTION OF PENTIUM PROCESSORS
• significant processor evolution
facts, including introduction
date, ratings and number of
transistors
FEATURES OF THE PENTIUM FAMILY OF
PROCESSORS
• fully software compatible with the installed
base of over 100 million compatible Intel
architecture systems
• provides new levels of performance to new
and existing software
• reimplementation of the Intel
32-bit instruction set
architecture using the latest,
most advanced, design
techniques P54C
ADVANCE FEATURES OF THE PENTIUM
FAMILY OF PROCESSORS
• Superscalar architecture or execution
• Pipeline architecture
• Branch prediction or Branch Target Buffer
• Dual 8-KB On-Chip Caches
• Write-Back Cache
• 64-Bit Bus
• Instruction Optimization
• Floating-Point Optimization
• Pentium Extensions
THE ARCHITECTURE OF PENTIUM MICROPROCESSOR
REGISTER SET

• is to hold temporary results and control the

execution of the program
• EAX, ECX, EDX, EBX, ESP, EBP, ESI, or
EDI
• The 32-bit registers are named with prefix E,
EAX, etc, and the least 16 bits 0-15 of these
registers can be accessed with names such
as AX, SI.
• Similarly the lower eight bits (0-7) can be
accessed with names such as AL & BL.
REGISTER SET

• The comparison of the available flags in 16-

bit and 32-bit microprocessor is may provide
some clues related to capabilities of these
processors.
• All of these flag registers include 6 flags
related to data conditions (sign, zero, carry,
auxiliary, carry , overflow, and parity) and
three flags related to machine operations,
interrupts, Single-step and Strings)
REGISTER SET

• The instruction pointer EAP known as

program counter (PC) in 8-bit
microprocessor, is a 32-bit register to handle
32-bit memory addresses, and the lower 16
bit segment IP is used for 16-bit memory
address.
• The flag register is a 32-bit register, however
14-bits are being used at present for 13
different tasks;
REGISTER SET

• The I/O Privilege uses two bits in protected

mode to determine which I/O instructions can
be used, and the nested task is used to show
a link between two tasks.
• The processor also includes control registers
and system address registers, debug and
test registers for system and debugging
operations.
PENTIUM PROCESSOR MODES
Protected mode
• the native state of the
microprocessor
• all instructions and
architectural features are
available
• the recommended mode that all new
applications and operating systems should
target
• capabilities of protected mode is the ability
to directly execute "real-address mode"
PENTIUM PROCESSOR MODES
Real-Address Mode or Real-
Mode
• programming environment of
the processor, with a few
extensions
• reset initialization places the processor in
real mode where, with a single instruction, it
can switch to protected mode
PENTIUM PROCESSOR MODES
System Management Mode
• a standard architectural
feature unique to all new Intel
microprocessors
• provides an operating-system and
application independent
• transparent mechanism to implement
system power management
• OEM differentiation features
INTEL PENTIUM MMX MICROARCHITECTURE
P6 MICROARCHITECTURE

External bus Data Cache

Chip boundary Unit (L1)
Memory
Cluster
Bus Cluster Memory
Bus interface unit Order Buffer

AGU
Instruction
InstructionFetch Unit
Fetch nit
MMX
IEU/JEU
Control IEU/JEU
(Restricted)
Flow BTB/BAC
FEU Data
Instruction Fetch Cluster Flow
MIU
Instruction
Instruction Register
Alias Table
Decoder
Decoder Reservation Out-of-order
Station Cluster

Microcode Allocator ROB &

Sequencer 19
Retire RF
Issue Cluster
NETBURST MICROARCHITECTURE

BTB (4k entries) I-TLB/Prefetcher 64 bits

64-bit
IA32 Decoder Code ROM System
Bus
Trace Cache BTB Quad
Execution Trace Cache op Queue
(512 entries) Pumped
400M/533MHz
Allocator / Register Renamer 3.2/4.3 GB/sec
BIU
Memory op Queue INT / FP op Queue

Memory scheduler Fast Slow/General FP scheduler Simple FP

INT Register File / Bypass Network FP RF / Bypass Ntwk

U-L2 Cache
AGU AGU 2x ALU 2x ALU Slow ALU FP FP
256KB 8-way
Simple Simple Complex MMX Move
Ld addr St addr
Inst. Inst. Inst.
128B line, WB
SSE/2
48 GB/s
256 bits
L1 Data Cache (8KB 4-way,
20 64-byte line, WT, 1 rd + 1 wr port) @1.5Gz
PIPELINE DEPTH EVOLUTION

PREF DEC DEC EXEC WB

P5 Microarchitecture

IFU1 IFU2 IFU3 DEC1 DEC2 RAT ROB DIS EX RET1 RET2

P6 Microarchitecture

TC NextIP TC Fetch Drive Alloc Rename Queue Schedule Dispatch Reg File Exec Flags Br Ck Drive

NetBurst Microarchitecture
ADDRESSING MODE & TYPE OF INSTRUCTIONS

• instruction set is divided into 9 categories of

operations and has 11 addressing modes
• instruction may have 0-3 operands and the
operand can be 8, 16, or 32- bits long
• All Intel Architecture instruction encoding are
subsets of the general instruction format
ADDRESSING MODE & TYPE OF INSTRUCTIONS

• Instructions consist of optional instruction

prefixes (in any order)
• one or two primary opcode bytes
• an addressing-form specifier (if required)
consisting of the ModR/M byte
ADDRESSING MODE & TYPE OF INSTRUCTIONS

• sometimes the SIB (Scale-Index-Base) byte

• a displacement (if required)
• an immediate data field (if required)
TRENDS IN MICROPROCESSOR
• Microprocessor astounding range of chips
powering devices
• Embedded microprocessor
• Microprocessor packaging
• Microprocessor speed
• Microprocessor increasing power dissipation
• Microprocessor cost, compatibility and fit
• Microprocessor Architecture for Java
Computing or MAJC
MAJC
• microprocessor architecture designed to
meet the broadband demands of the 21st
century
• addressing the challenge of high bandwidth
• need for state-of-the-art computational
performance
MAJC ARCHITECTURE CHARACTERISTICS
• Scalability to take full advantage of advances
in semiconductor technology
• Broad scalability to systems with large
numbers of processors
• A new standard of performance for
applications with New Media computational
needs
• Focus on bandwidth throughput
21st CENTURY MICROPROCESSOR TRENDS
• Convergence of communication media and
computers (audio, video, and data) require
processors to compute information at wire
speed
• Advancements in semiconductor technology will
provide rapidly-increasing resources on each
microprocessor chip
• As microprocessors are used in increasingly
disparate applications from smart cards to
supercomputers there is great value in the
ability to create a wide span of implementations
from a given processor architecture
21st CENTURY MICROPROCESSOR TRENDS
• Software, over time, will become
independent of specific instruction sets
• Bandwidth between processors, memory,
and I/O devices needs to be available to
move information in real-time
• The content processed by computers is
becoming increasingly media-rich
FEATURES OF TODAY’S MICROPROCESSOR
• Modular Architecture
• Software Portability
• Multiple Levels of Parallelism
• Multiple Processor Units per Cluster
• Multiple Functional Units per Processor Unit
• Multiple Software
• SIMD Instructions
FEATURES OF TODAY’S MICROPROCESSOR
• Integral Support for Media-Rich Data
• Data Type-Independent Registers
• Instruction Grouping
• Data and Address Size
• Context Switch Optimization
THANK YOU!!!