Highlights :

1.BBU design progressing : Mechanical concept simplified.Incorporated

AMC support.
2.BBU : Processor and 1588 solution identified.
3.BBU : BB module layout in progress based on TI chipset.
4.RRH : Initiated work activities with Frogcell team.
Low Lights

1.Requirement discussion taking longer than predicted internally.

2.Change in device selection would mean earlier progress on CPU
board is reset.Work items needs to be aligned.
3. Not much progress on various design aspects on RRH.

MS-2 Overall Status

BBU-Design closure
RRH-Design closure
BBU- Board design
Platform SW Bringup Readyness
Design-documentation
 Escalations

1.Lack of support from device vendors is a key concern.

2.Frogcell contract not signed yet : work items not progress as predicted ,
workshop deferred as they could not travel.
Risks

1.Overall project schedule /plan needs to be aligned based on revised kick-

off and current status.
2.Platform software resourcing and scope needs to be re-aligned.
Refer detailed sheet for technical risk.

31/03/2018
31/01/2018
31/01/2018
16/03/2018
31/03/2018
31/03/2018
BBU- Board design
Platform SW Bringup Readyness
Design-documentation
16/03/2018
31/03/2018
31/03/2018
Sr.No Category Risk Description Severity
1588 v2 solution not completely analyzed .
Platform software ( 1588 protocol stack) ,
1 Technical Test configuration needs to be studied. Medium

Redundency/Availability
requirements,serviceability requirement
(MTTR) , MTBF target / supported operating
2 Technical life not available /clear. High

BOM Cost : No clear BOM targets defined by

customer. If overall product cost does not
meet customer's expectation at late stage
then it will have severe impact on program
3 Program schedule /cost. High

Second source qualifcation not covered under

4 Program schedule /cost estimates for the program. High
BBU Cabinet included in deliverables but not
5 Program estimated. Medium

Optical requirements are not clear. Range of

Technical/ optics , list of optics supported needs to be
6 Program clear. Medium
Technical/
7 Program L1 integration plan is un-clear. Medium

Frogcell :
1. Contract not signed yet.
2. RRH scope is still churning. Current
contract covers development ( HW +
Mechanics +SW), prototype , tooling costs for
3 different varients for RRH. This seem un-
8 Program realistic. High

Overall budget for proto cost seems very low.

A. Cost budgeted at 1K volume vs 20 units
volume.
B. Based on old rev of B and see many gaps.
C. Accessaries , optics , cabinet etc. not
9 Program estimated. High
Hardware will release Proto-2 before L1
integration. Overall test strategy much be
10 Technical defined to ensure adequate coverage. High

Vendor Support : Lack of support from device

11 Program vendors may impact overall schedule. High
Platform software work items seem moving
12 Program slow. Resourcing issues are getting resolved. Medium
Overall schedule needs to aligned to reflect
13 Program late kick-off and current relality . Medium
 Proto-procurement need to start 6 weeks
ahead of build schedule. Our PO' should in
14 Program place before. Medium
Optics requirements are unclear in terms of
speed , range support. Optics cost may not
15 Technical adequately coverd in proto budget. High

Changes in key devices selection at late

stage might create
huge impact on the overall
16 Program design/program. High
Impact Mitigation Target Date

This may create overall schedule /cost impact Need to identify an owner to study this and
on program if not closed. close before design closure. 1/30/2018

If these requirement come later it may create

a big impact on overall program

Key decisions taken earlier in the design

phase are difficult to change. This may lead to
design churn at later stage impacting overall Need to push for closing high level BOM
schedule/cost. cost alignment at design closure. 1/30/2018

Only first source qualification planned and

This will have a big impact on proto-cost if
included.
This will impact project cost ( effort/proto
cost).
second source identification can be done.
Plan to push back second source qualification
to CDOT.
Propose to re-use existing cabinets from
CDOT.

This may create overall schedule /cost impact

on program if not closed. If range of optics To be discussed with CDOT during
are to be supported then it will increase requirement discussion. Plan to test only two
qualification effort, proto cost. type of optics.
This may create overall schedule /cost impact
on program if not closed. Need to develop a plan.

Delay in starting RRH development and

overall schedule impact.

Need to re-estimate based on revised BOM

This will impact project cost ( proto cost). and current view.

This may impact Proto-2 quality, overall

schedule and cost. To be discussed.

This may create overall schedule /cost impact Requested CDOT to intervene . Vendor kick-
on program if not closed. off to be scheduled.
This may create overall schedule impact on
program if not closed.
Delay in proto-1 build.
Owner Status
Comments
OPEN
CLOSE
Sr.No Category Open Item
1 Requirements
Requirement Sign-off

2 Architecture
BBU Mainboard

Processor Selection

Memory sizes/ dimensioning

Phy Selection

1588 Solution

PCB Stack-up and vendor

BB Module

Processor /SOC Selection

Memory sizes

PCB Stack-up and vendor

CPRI optical Interface.

Form Factor- Mechanics Concept

Thermal Simulation

SI /PI

3 System
 Power Budget and Power distribution

Compliance Plan

Test strategy and testware

Bring-up
DVT
Pre-Compliance

Reliability
High level estimate
Overall FIT estimate

4 Procurement
Preliminary BOM for quote
Proto Board -Vendor quote
Proto Vendor Selection
Proto Board -PO release
Proto procurement
Target Date Owner Status

1/15/2018 Anand OPEN

1/24/2018 Kali OPEN

1/24/2018 Kali OPEN

1/24/2018 Kali OPEN

1/24/2018 Kali OPEN

1/24/2018 Kali OPEN

1/24/2018 Shiladitya OPEN

1/24/2018 Shiladitya OPEN

1/24/2018 Shiladitya OPEN

1/24/2018 Shiladitya OPEN

1/20/2018 Siva OPEN

1/20/2018 Deepak OPEN

1/30/2018 Shiladitya/Kali OPEN

1/24/2018 Avinash OPEN

1/30/2018 Avinash OPEN

2/14/2018 Avinash OPEN

2/14/2018 Avinash OPEN
3/15/2018 Avinash OPEN

1/30/2018 OPEN
2/28/2018 OPEN

1/16/2018 Kali,Shiladitya OPEN

1/23/2018 Yogendra OPEN
1/23/2018 Yogendra OPEN
1/30/2018 Yogendra,Mahesh OPEN
3/15/2018 Yogendra OPEN
Comments

Final response from our side needs to be sent to CDOT by 15/01.

01/18 additional comments to be addressed.

1. Comparison for all vendors.

2. Processor cost for 8350 , 8250 , 8240 , 8340 to be quoted by Cavium.
3.

1. Memory estimates to be taken from SW team.

01/18 Initial estimates available.

1. Need decision on 10G support , also clarify if 4x1G

to be supported : Anand.
01/18 : Need to discuss and conclude. This needs CDOT confirmation as
well.
1. IDT have been chosen based on data provided to us.
Micro-semi data is not provided and blocked CDOT vendor kickoff.
2. Software scope to be identified for 1588 : Mahesh
1. PCB stack available from Prodigy. Decision on PCB material to be
taken based on SI input and decision on 10G.

1. Selection is aligned for TI solution. Final approval to be taken from

CDOT.
2. Commercial temperature device to be used in Proto-1.
1. Memory estimates to be taken from SW team.
2. Need to verify how much Comm agelity L1 software needs .
01/18 : RAM estimates are available , NAND estimates are pending.
1. PCB stack available from Prodigy. Decision on PCB material to be
taken based on SI input for routing CPRI for 6-7 inches.
1. No of SFP interfaces to be finalized with CDOT. Verify if four can be fit
in PCB / Mechanics.
01/18 : Go with four SFP and decide later.

1. AMC based concept to be evaluated.

01/18 : Initial results need refinement. Electrical team shared revised power numbers.

1. No clear plan for SI/PI. : Mahesh.

1. Board level estimates exists and needs to be integrated.
2. Dying gaspe for PSU.
3. Power distribution.
Need an overall system level estimate.

1.Verify compliance standards from requirements and see if

we have design impact to support those.

1. Need a test configuration to test BBU independly.

2. Test equipment list to be reviewed again. See what is needed for
optical interface.

1. Need clarity on requirement for supported life time.

Mechanics is open.
OPEN
CLOSE
BBU Proto-1 Schedule

REQUIREMENTS

DESIGN CONCEPT

IMPLEMENTATION
 1-Jan 8-Jan 15-Jan 22-Jan
WK01 WK02 WK03 WK04

CDOT Sign-OFF

Design Concept Ready

(Mechanics and Board Concept)
Design Document Sign-off
Main Board - CPU
BB Module
Mechanics
Platform SW ( BSP , Diagnostics)

Main Board - CPU

Schematics
Prelimiary BOM
Placement
EMN Closure-Prelim
PCB Stack-Up and Layout Constraints
Layout
Gerber Release
Proto available
BB Module
Schematics
Prelimiary BOM
Placement
EMN Closure-Prelim
PCB Stack-Up and Layout Constraints
Layout
Gerber Release
Proto available

BBU Enclosure 1U
Mechanics Concept
Thermal simulation , Heat sink design.
BBU Enclosure
Detailed 3D
EMN Closure
Drawings Release
BB Module- Enclosure
Detailed 3D
EMN Closure
 Drawings Release

FPGA
High level Design
Pinout and Power Estimate
Implementation
Initial Binaries available

Platform SW ( BSP , Diagnostics)

Reference Platform Bring-Up

Board BringUp ReadyNess
 29-Jan 5-Feb 12-Feb 19-Feb 26-Feb 5-Mar 12-Mar 19-Mar 26-Mar 2-Apr
WK05 WK06 WK07 WK08 WK09 WK10 WK11 WK12 WK13 WK14
 9-Apr 16-Apr 23-Apr 30-Apr 7-May 14-May 21-May 28-May 4-Jun 11-Jun
WK15 WK16 WK17 WK18 WK19 WK20 WK21 WK22 WK23 WK24
 18-Jun 25-Jun 2-Jul 9-Jul
WK25 WK26 WK27 WK28
Documentation Owner
Requirement Specification -BBU
Requirements Specification-RRH
e-NodeB Hardware Architecture Document
BBU Hardware Design documentation Preparation
RRH Hardware Design documentation Preparation
BBU BSP/Firmware Design Documentation Preparation
RRH BSP/Firmware Design Documentation Preparation
BBU FPGA Design Documentation Preparation
RRH Design Documentation Preparation

TCT Board Proto-1 Activities

Base Band Board Proto-1 Activities

Schematics

Layout
Back Plane Board Proto-1 Activities
Target Date

Sub-Activities Start Date End Date Working days#

Actual Plan
Sub-Activities Start Date End Date Working days#

Logical Symbol Preparation 13-Dec-17 15-Dec-17 3

Schematics drawing 13-Dec-17 22-Dec-17 8

Schematics review 26-Dec-17 27-Dec-17 2

Schematics Update 28-Dec-17 29-Dec-17 2

BoM Review 26-Dec-17 27-Dec-17 2

BoM Release 28-Dec-17 29-Dec-17 2

PREQ for Class A components 13-Dec-17 22-Dec-17 8
PREQ for ALL components 28-Dec-17 29-Dec-17 2
Test Procedure and setup 1-Jan-18 30-Jan-18 30

Foot print creation 13-Dec-17 15-Dec-17 3

Component Placement 18-Dec-17 19-Dec-17 2

Component Placement Review 19-Dec-17 19-Dec-17 0

Layout 20-Dec-17 29-Dec-17 7
SI Analysis 26-Dec-17 29-Dec-17 4

PI Analysis 26-Dec-17 29-Dec-17 4

Layout update 1-Jan-18 2-Jan-18 2

Layout Review & 1st cut Gerber for
3-Jan-18 4-Jan-18 2
internal review
Final layout modifications 5-Jan-18 8-Jan-18 2
Sharing Gerber for DFM and DFA review 8-Jan-18 8-Jan-18 0
Manufacturing Review 9-Jan-18 15-Jan-18 5
Incorporation the review comments (EQ 16-Jan-18 17-Jan-18 2
addressing)
Final Gerber Release for Manufacturing 17-Jan-18 17-Jan-18 0
Stencil Release 17-Jan-18 17-Jan-18 0
PREQ for PCB fabrication 27-Dec-17 10-Jan-18 11
PREQ for stencil 27-Dec-17 10-Jan-18 11
PREQ for Assembly 27-Dec-17 10-Jan-18 11

Actual Plan
Sub-Activities Start Date End Date Working days#
 Resources

Resources

Vignesh

Remya

Shiladitya/Vikram/Kalidoss/Avinash/Rajesh/Vinesh/Anand
Remya

Shiladitya/Remya/Vidhya

Shiladitya
Raghuram/Venkat
Raghuram/Venkat
Remya/Shiladitya

Dinesh
Dinesh

Vikram/Kalidoss/Vignesh/Shiladitya/Avinash/Rajesh/Vinesh/Anand
Dinesh
Nithin/Shiladitya

Nithin/Shiladitya

Dinesh
Vikram/Kalidoss/Vignesh/Shiladitya/Avinash/Rajesh/Vinesh/Anand
Vignesh
Vikram/Kalidoss
Hi-Q/Prodigy
Vignesh
Vikram/Kalidoss
Vikram/Kalidoss
Raghuram/Venkat
Raghuram/Venkat
Raghuram/Venkat

Resources
% completion ETA

% completion ETA

99% 17-Jan-18

80% 19-Jan-18

0% 22-Jan-18
0%

80% 17-Jan-18

80% 17-Jan-18

99% 17-Jan-18
 80% 19-Jan-18

0% 22-Jan-18
0% 10-Feb-18
0% 3-Feb-18

0% 3-Feb-18

0%

% completion ETA
Remarks

Remarks

New IDT clock chip

Open Items
1. Properties updation for components
2. Decision on CPRI redundancy (2 or 4 SFP+ on front haul) (need closure by 17 Jan)- we have to go with 4
SFPs
3. Logic level compatibility check for new IDT clock chip- replaces TI CDCM chip
4. Decap optimisation and footprint update
5. Derating of inductors
6. All programming headers need to be combined for space savings
7. Single net updates
8. Backplane connector update

Dependency on row 25

1. CVDD convertor is RoHS exempt- is it ok?

4. Backplane connector selection
2. Hot swap controller selection
3. Derating of inductors

To be discussed
To be discussed

New IDT clock chip

Dependencies
1. EMECH concept/Thermal simulation (need closure by 17 Jan)
2. Decision on CPRI redundancy (2 or 4 SFP+ on front haul) (need closure by 17 Jan) - estimate for 4SFPs

Estimate- to be reconfirmed with ECAD

License Availability, Post route SI
Dependencies
1. License availability
2. Plain splitting implementation (need closure by 27 Jan)
Items below will be updated after discussion with ECAD on 17th Jan

Remarks
Sr.No Category Description Custom
1 Board BB -TCT Yes
2 Board BB -Module Yes
3 Board BB - Backplane Yes
4 Board PSU module NO
5 Mechanics BBU Enclosure YES
6 Mechanics BBU Cabinet TBD
7 Mechanics BB Module enclosure Yes
8 Mechanics BBU FAN unit Yes
9 Mechanics PSU module enclosure
Target Date Owner Status
2/28/2018 Kalidoss
2/28/2018 Shiladitya
2/28/2018 Kalidoss
2/28/2018 Kalidoss
2/28/2018 Siva + Ajmeer
2/28/2018
2/28/2018 Siva + Ajmeer
2/28/2018 Siva + Ajmeer
Comments
OPEN
CLOSE
 MS-1 MS-2 MS-3
1 Hardware
Release Note

System Overview and System Architecture

Y Y
Document
Installation, configuration and administration
document
User Guide for all hardware and software
components
System Level Test Plan and Test Report
Physical deliverables
BBU Hardware Y

BBU Cables, Connectors and other accessories Y

BBU Software (OS, Libraries, Firmware) Y

BBU Cabinet

RRH Hardware and associated cables,

connectors.
GPS/equivalent clock module (either internal or
Y
external)
Any power modules required
Any power adapters required for operating in
Indian operators
Ethernet Switches or any other interconnection
equipment
Any chassis required
BBU
Design & manufacturing knowhow kit for BBU
Hardware & RRH Document
Hardware Architecture Document, Module
Y
Design
Bill of Material (BoM) with vendor details Y Y
Schematic, Component List Y Y
Gerber Y Y
Assembly Document, Cable diagrams Y
Cable diagrams
General Description, Programming
Consideration
Circuit Design Y
Assembly Document, Cable Diagram. Y
Test Setup, Test Report Y
Thermal Analysis, Manufacturability

Test Jigs

Test Document

Mechanical design and packaging details

List of Test and development tools required

 Hardware
MS-4 MS-5 MS-6 Remarks

Y Y Y

Y Y Y

Y Y Y

Y Y Y

Y Y Y
Re-use of existing cabinets from CDOT to be
discussed.
Y Y Y

Y Y Y

Y Y Y

Y Y Y

Y Y Y

Y Y Y

Y Y Y

Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y

Y Y Y

Y Y Y
Y Y Y
Y Y Y
Y Y Y
Test jig development for manufacturing is not
planned.
Y Y Y

Y Y Y Transportation Packaging details to be

discussed.
Y Y Y
Documentation
BBU Platform Software Requirement Specifications
BBU Platform Software Architecture Document
BBU Platform Module Interface Specification
BBU Platform Design Document
BBU Platform Unit test case document
BBU Platform Integration Test Case Document
Owner Target Date

Kamjith 28-Feb-18
Kamjith 9-Mar-18
Kamjith, Harish 23-Mar-18
Harish 28-Feb-18
Kamjith, Harish 30-Mar-18

Activities Sub-Activities

Linux bringup on K2K EVM

Build - creation of the uboot, uimage
Booting with the new uimage
Linux bringup on Cavium EVM
Cavium linux build
Booting with the new uimage

Diagnostic CLIs for CCT board standaone

Interface (I2C, SPI, USB) related

Memory (DDR/NOR/SPI flash) related
GMAC interfaces related
LED, temperature sensor related
Miscellaneous

Diagnostic CLIs for BB board standalone

Interface (I2C, SPI, USB) related

Memory (DDR/NOR/SPI flash) related
GMAC interfaces related
Miscellaneous

Diagnostic CLIs for CCT + BB board combined

CCT-BB connection
CPRI loopback related

L1 integration activities
Verification of the L1 PHY module for the latest
SDK

K2K support for L2 modules

 Platform services aligning with the latest MCSDK
version

RRH interface support

(C&M) suport APIs

Cavium support for L2/L3 modules

Accelerator related changes
Transport related changes

FPGA APIs

Sync (1588) related activities

This document will detail out the (1) APIs exposed towards OAM (2) Diag CLIs available
Detailed design details

Start Date End Date Resources % completion ETA

22-Jan-18 24-Jan-18 Yashwanth,Harish

24-Jan-18 3-Feb-18 Yashwanth,Harish

22-Jan-18 24-Jan-18 Rahul,Harish

24-Jan-18 10-Feb-18 Rahul,Harish

12-Feb-18 16-Feb-18 Rahul,

19-Feb-18 23-Feb-18 Rahul,
26-Feb-18 2-Mar-18 Rahul,
5-Mar-18 9-Mar-18 Rahul,

5-Feb-18 9-Feb-18 Yashwanth

12-Feb-18 16-Feb-18 Yashwanth
19-Feb-18 23-Feb-18 Yashwanth
26-Feb-18 9-Mar-18 Yashwanth

12-Mar-18 Rahul, Yashwanth

30-Mar-18 Rahul, Yashwanth

26-Mar-18 6-Apr-18 Yashwanth

1-Mar-18 16-Mar-18 Harish

6-Apr-18 Harish

27-Apr-18 Harish
Remarks

Direct support from TI needed

Availabity of Cavium EVM is not clear

UT on EVM included for all CLIs

many of these diag tests may be already present in SDK, need to check
need to analyze the delta between EVM and actual design impact

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