International Conference on Emerging Research in Electronics, Computer Science and Technology –
2015
Design and Evaluation of FinFET based digital
circuits for high speed ICs.
Raju Hajare, Dr .C.Lakshminarayana. Sunil.C, Sumanth, Anish.A.R
Abstract— The Delay and Speed plays a complementary
role in ICs, as the delay decreases the speed increases and
vice-versa. The scaling of MOSFETs has resulted in
reduction in size of ICs. As we scale down to nanometer
regime, the Short Channel Effects (SCEs) of MOSFET
affects the system performance and reliability. Here in this
paper we discuss on FinFET, which is an alternate
MOSFET, through which the SCEs are reduced. The
performance analysis of FinFET based digital applications
such as inverter circuit, NAND and NOR gates at 22nm
and 14nm technology nodes is also discussed. The
simulations are done using HSPICE. The results obtained
for delay, average power dissipation and total power
dissipation are so promising that FinFET will be an
alternative to traditional MOSFET’s issues. The noise
margin calculation of FinFET based Inverter circuit at
22nm and 14nm is also discussed.
KEYWORDS : FinFET, PTM, Technology node, Power,
Delay, Noise margin.
1 INTRODUCTION
As Gordon Moore predicted, over the last three decades
number of transistors in a single chip has been increased
significantly from thousand to several billion. As a result of
this, the advancements in technologies gave us high-speed
multi-core processor technology, huge size memory devices,
etc. Yet, today’s emerging advanced robotic systems and
embedded systems need higher speeds, smaller sized IC’s to
push boundaries of their performance and current IC
technologies are unable to deliver their requirement [1-3].
Hence development of such systems remains a challenge. To
support development of such systems, it is necessary for IC
technology to scale down the transistors and increases the
speed and performance.Every circuit consists of an inverter,
NAND and NOR circuits.
Raju Hajare, is with department of Telecommunication Engineering, BMS
Institute of Technology, Bangalore 560064,India.(e-mail:
rajuhajare@bmsit.in).
C. Lakshminarayana., is with department of Electrical and electronics
Engineering , BMS college of Engineering, Bangalore, India 560019 (e-mail:
lngp.eee@bmsce.ac.in)
The shrinking of the CMOS technology has been increased
very aggressively with ultra-thin sizes[2].
This creates many significant challenges and reliability issues
in design which causes augmented process variations, SCEs,
power densities and leakage currents etc. Thus Inverter,
NAND and NOR circuits are one of the essential parts of
digital system. The operations of such device are usually
valued by taking its operation parameters like switching speed
in terms of delay of operation and power consumption. Since
the MOSFET’s failure at the nanometer regime beyond 32nm
and our focus is on operations at the lower node technology
such as 22nm and 14nm where alternative MOSFET called
FinFET comes into picture and its performance must be
studied and we shall prove that it is the solution for
conventional MOSFET’s failure.
2. MOSFET AND FINFET STRUCTURE
Metal Oxide Semiconductor Field Effect Transistor
(MOSFET) allowed us to build everyday advanced systems
such as Smart Phones, Laptops, etc., which is prior to the 22-
nm node. In 22-nm node further scaling down of MosFET has
become impossible due to increased SCEs, such as Drain
Induced Barrier lowering (DIBL), Impact Ionization, Velocity
saturation, Channel length modulation, Oxide breakdown, etc.
Hence for advancements in 22-nm node most of the foundries
introduced new type of transistor called Fin Field Effect
Transistor (FinFET) [5-7]. To deliver small and fast IC’s with
large computation capability, key requirements of transistor
design are:
1. High ON current (ION).
2. Low OFF current (IOFF)
3. High switching speed.
To achieve these, other transistor options which will give the
better performance, must be explored. That is the place where
FinFET technology plays a pivotal role [8-9]. Fig.2.1 shows
the traditional MOSFET.
978-1-4673-9563-2/15/$31.00 ©2015 IEEE
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 C. TECHNOLOGY NODES:
The 22-nanometer (22-nm) is the process step currently being
used. The typical half-pitch (i.e., half the dista. nce between
identical features in an array) for a memory cell using the
process is around 22 nm. The 14-nanometer (14 nm) node is
the technology node following the 22-nm (20 nm) node.

D. PREDICTIVE TECHNOLOGY MODEL:

The Predictive Technology Model (PTM) or PTM provides
accurate, customizable, and predictive model files for future
Fig.2.1: Structure of MOSFET[13].
transistor and interconnect technologies. These predictive
Fin Based Field Effect Transistor (FinFET) is a vertical model files are compatible with standard circuit simulators,
multiple-gate device that has been stated as a promising such as SPICE, and scalable with a wide range of process
candidate to substitute bulk CMOS technology for Very variations.
Large- Scale Integrated (VLSI) circuits, due to its higher
potentiality to push back the integration limits [10-12]. E. DEVICE PARAMETER CONSIDERATIONS:
Additionally, other advantages are mainly: lower short The design parameters are considered with respect to the PTM
channel effects impact, steeper sub-threshold slope and model files. Table 1 shows the design parameters we have
reduced variability influence. Here we are considering a employed for the circuit simulations in our present work.
Double Gate (DG) shorted gate (SG) FinFET to analyse the Table.1: Device parameter considerations [13].
digital circuits of Inverter, NAND and NOR gates. Fig.2.2
Shows Structure of FinFET PARAMETER 22nm FinFET 14nm FinFET
Gate Length (Lg) 22nm 14nm
Supply Voltage 0.9v 0.8v
Thickness of Fin 10nm 10nm
(TFIN)
Height of Fin 30nm 23nm
(HFIN)
Thickness of 1.4nm 1.3nm
oxide (TOX)

Technology nodes are defined based on the gate length as

Fig.2.2 Structure of FinFET.
3.TECHNICAL CONSIDERATIONS.
The concepts and considerations to be known prior to
understand the Inverter, NAND and NOR gates are as follows.
the device is scaled down the supply voltage, oxide thickness
and height of the fin is also scaled down to meet the
requirements and to avoid the velocity saturation factor. The
design considerations are done on the basis of the geometry
description of FinFET device structure. Fig.3.1 shows the
geometry description of FinFET.

A. HSPICE SIMULATION SOFTWARE:

The circuit simulations are done using HSPICE. It is an
optimizing analog circuit simulator. Which we have used it to
simulate electrical circuits in transient domain. It is best suited
for fast, accurate circuit and behavioural simulation. It
facilitates circuit-level analysis of performance.

B. COSMOSSCOPE SOFTWARE:
CosmosScope software program can help HSPICE simulator
to generate the output waveform. This is because Fig.3.1: Geometrical Description of FinFET[13].
CosmosScope program can support the entire Synopsys
simulator. The data that are received from the other The important parameter and equations through which the
programme can be turn to the useful information in Cosmos device parameter considerations:
Scope.

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 HFIN: Height of the To ensure a stable operation of the inverter, its noise margins
fin. WFIN: Width of NMH and NML need to be sufficiently positive. The noise
the fin. margin of a logic gate is directly related to the reliability and
LSD: Length of the source and robust operation of the logic circuit. The fig.3.2 represents the
drain. WSD: Width of the source method of calculating the Noise Margin for Inverter circuit.
and drain. LG: Length of the Gate.
Lext: Length of the source and drain extension.
Effective width (Weff) of the device is given
by,
Weff = 2HFIN + WFIN
And effective length of the channel is given by,
Leff = LG-26LG
Where, 6LG is the gate under lap length.

3.1 POWER:
Power consumption and dissipation is one of the major
performance metric of digital applications[10]. The power
Fig3.2: Graphical calculation of Noise Margin for FinFET
consumed by the FinFET based digital circuits at 22nm and
based Inverter circuit [13].
14nm technology nodes are studied here. Two kinds of power
are introduced, Average power and Total power. The former
4. FINFET BASED DIGITAL APPLICATIONS
represents the power calculated in an interval of 200ns,
whereas later represents the power calculated during an entire
Inverter, NAND and NOR gates are essential component in
cycle of operation.
any device circuits. According to International Technology
Roadmap For Semiconductors (ITRS), in current world’s
3.2 DELAY:
scenario 94% of chip area is occupied by memory where
The delay of the FinFET based digital circuit can be measured
switching operations are carried out by the circuits numerous
in terms of the rise and fall time delay of the circuit [10].
times. This demands the circuits to operate in high speed and
DELAY = (Rise time + Fall time) / 2
also power consumption of embedded memory circuits to be
reduced. Lowering the supply voltage is very effective in
3.3 NOISE MARGIN (NM):
power saving but scaling down the power supply using
To ensure the proper operation of the digital circuit, one has to
conventional MOSFET is an issue due to SCE. Hence,
take into account some stability considerations. In particular,
FinFET can be used as an alternative to scale down the power
the Noise Margin (NM) of an inverter is an important figure
supply.
for the stability of the digital circuits. Noise margin was
originally defined as “the maximum allowable spurious signal
that can be accepted by a device when used in a system while
5. RESULTS AND DISCUSSIONS
still giving correct operation” [4].For an inverter, it is possible
to define the high and low voltages V OH and VOL, where VOH is
First the SPICE model for FinFET based circuits is
the minimum output high voltage and V OL is the maximum
developed then needed alterations are done on the PTM model
output low voltage. Furthermore, one can define the transition
file according to our design and the SPICE model is simulated
points VIH and VIL, where VIH is the minimum input high
to obtain the necessary results. The parameters which we
voltage that can be treated as a high voltage at the input of an
focus to measure are delay, average and maximum power
inverter and
consumption. The Noise Margin for Inverter circuit is
VIL is the maximum input low voltage that can be treated as a
measured. The simulated results are recorded and tabulated
low voltage at the input of an inverter. If one has an inverter
with necessary graphical plots. The performance variations
satisfying the relationships
can be easily observed and studied here. Results obtained for
VIN ≤ VIL ‹ VOUT ≤
delay, NM, average and maximum power consumption are
VOH VIN ≤ VIH ‹
better than others.
VOUT ≤ VOL VIH > VIL
With VIN being the input voltage and V OUT the output voltage The 22nm model circuit is provided with a supply voltage of
of the inverter, then the high- and low-state noise margins 0.9V and the 14nm model circuit with 0.8V, similarly all
(NMH and NML, respectively) can be defined mathematically other parameters necessary to be scaled down are done with
as respect to the design consideration table described in the
NMH = VOH – VIH Table 1.
NML = VIL – VOL

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5.1 FINFET BASED INVERTER RESULTS: Fig.5.1c shows bar graph for inverter based results at 22nm
Table.2 shows simulation results for FinFET based Inverter and 14nm
circuit. The noise margin calculations are made and are
tabulated below.

Table.2: Simulation Results for FinFET based Inverter.ps-

PICO SECONDS, uw- MICRO WATTS

PARAMETER 22nm FinFET 14nm FinFET

Inverter Inverter
Delay 45.4625 ps 74.0142 ps
Avg Power 4.5646 uW 3.2797 uW
Max Power 65.5722 uW 28.0496 uW
Noise Margin low 670mV 550mV
(NML)
Noise Margin high 800mV 700mV
(NMH)
Fig.5.1c: Bar graph chart for FinFET Inverter.
Fig.5.1a and Fig.5.1b shows the output waveform obtained for
FinFET based Inverter circuit at 22nm and 14nm.
5.2. FINFET BASED NAND GATE RESULTS:
Table.3 shows simulation results for FinFET based NAND
circuit. Fig. 11 and 12 shows the simulated waveforms of
FinFET based NAND gate at 22nm and 14nm respectively

Table.3: Simulation Results For Finfet Based Nand Circuit.

PARAMETER 22nm FinFET 14nm FinFET

NAND NAND
Delay 42.4052 ps 72.2176 ps

Avg Power 119.2689 nW 85.2171 nW

Max Power 117.8822 uW 35.2913 uW

Fig.5.1a: Simulated waveform of FinFET based Inverter at
22nm.

Fig.5.1b: Simulated waveform of FinFET based Inverter at Fig.5.2a: Simulated waveform for NAND circuit at 22nm.
14nm.

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 Fig.5.2b: Simulated waveform for NAND circuit at 14nm. Fig.5.3.a: Simulated waveform for NOR circuit at 22nm.

Fig.5.2c shows bar graph for NAND circuit at 22nm and

14nm.

Fig.5.3.b: Simulated waveform for NOR circuit at

14nm.

Fig.5.3.c shows bar graph for FinFET based NOR circuit at

Fig.5.2c: Bar graph chart for FinFET based NAND circuit. 22nm and 14nm.

5.3. FINFET BASED NOR GATE RESULTS:

Table.4 shows simulation results for FinFET based NAND

circuit. Fig. 5.3.a and 5.3.b shows the simulated waveforms of
FinFET based NOR circuit at 22nm and 14nm respectively.

Table.4: Simulation Results for FinFET based NOR Circuit.

PARAMETE 22nm FinFET 14nm FinFET

R NOR NOR
Delay 51.0154 ps 86.2274 ps

Avg Power 123.9511 nW 87.2265 nW

Max Power 67.1310 uW 32.311 uW

Fig.5.3.c: Bar graph chart for FinFET based NOR circuit.
The results obtained for each of the digital application at system trade-off is a concept in which a system trade any of the
14nm and 22nm of FinFET shows a system trade-off. The parameter such as delay, power and area in order to obtain
better results.
As we scale down the device from 22nm to 14nm the area
covered by the device is reduced, the power consumption
hence the power dissipation is also reduced but the delay in
the operation of the device has increased at the 14nm node.
This is very minor issue because the system reliability and the
performance has improved because of this trade off and the
tolerant capacity of the device is also improved
6. CONCLUSION
Simulation results for FinFET based digital application at
22nm and 14nm are studied here. The short channel effects
which were faced by the MOSFET devices, hence failing to
operate at lower technology nodes has overcome by the
FinFET. The results obtained shows that the FinFET’s
application on the nanoscale devices has improved. The
values obtained for noise margin for FinFET based inverter in
our study proves that the circuit has better reliability and
tolerant capacity. Hence FinFET is a promising candidate in
the current and future high speed IC’s fabrication process and
the modern devices can possess FinFET based circuits and
perform better with more features, with more speed and low
power consumption and dissipation.
ACKNOWLEDGE
The authors acknowledge BMSIT for the Infrastructure and
Encouragement.
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AUTHORS BIOGRAPHY
Raju Hajare received B.E degree in
Electronics and Communication Engineering
from Mysore University, India. He did his
M.Tech in the field of Power Electronics
from Visvesvaraya Technological University,
India. He is currently working as a Associate Professor in Tele
Communication Department of BMS Institute of Technology,
Bangalore. His areas of interest are Semiconductor Devices,
Nanoelectronics and NEMS. He has Published research papers
in reputed international Journals and presented papers at
different international Conferences.
Dr.Lakshminarayana.C received his Ph.D
from Anna University, India. He is currently
working as a Professor in Department of
Electrical and Electronics Engineering, BMS
College of Engineering, Bangalore. His areas
of interest are Power Systems, Power Electronics
Nanoelectronics. He has presented papers at different
international Conferences and published papers in reputed
Journals.