Clock pulse is a time varying voltage signal in sequence of 0&1 for sufficient duration to perform

prescribed operation. The time period of clock consist a ‘1’ representation and a ‘0’ representation.

In the above figure upper level is considered as 1 and lower level as 0. The corner wnere transition
of 0 to 1 occurs, is known as rising edge and the corner where transition 1 to 0 occurs, is known as
falling edge.This clock pulse can be generated using schimit triger or 555 timer.

Latch: Latch is the bistable memory element.Which can store one bit in the form of either 1 or 0.It
can be designed by NAND gates as well as with NOR gate.

Ex.

S R Qn
0 0 NA
0 1 1
1 0 0
1 1 Same as
previous

Observation

1. In these circuit we will observe present state Q n+1 and previous state Q n because output of
memory element depends upon present input and past value of output.
2. Output of NAND gate is 1 if its any of the input is 0 but when its one input is 1 we have to
think about the value of another input value which will be the deciding factor.

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

3. If no input is given to the circuit and both inputs are connected together the output will be
complement to each other. for example if Q=0 so the output of NAND 2 will be 1 and if
output Q́ is 1 then next output of NAND1 will be 0 and so on.

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 4. For input R=0 and S=0 both the nand gates provide output 1 while both outputs in this case
are considered as complement to each other hence this state is not accepted.
5. For input R=1, S=0 it is clear that Q=1 but Q́ depends upon second input of NAND gate 2
which is connected to Q. Let consider Q=0 in previous state so now the output of NAND 2
comes to be 1 but this condition is not acceptable because in this case Q́ becomes 1 and Q
is already 1 which is not accepted.So our assumption about previous Q=0 is not correct. Now
let us assume Q=1 in previous state now both the input of NAND 2 are 1 hence output comes
to be 0.Which is acceptable by each concept.hence for this input next state will be 1.
6. For input R=0, S=1 it is clear that present state Q́ =1 but the output of NAND 1 ie Q
depends upon second input of NAND gate 1 which is connected to Q́ . Let consider Q́ =1 in
just previous state so now the output of NAND 1 comes to be 0 which is a acceptable output.
7. For input R=1, S=1 it is clear that the present value of Q and Q́ depends upon previous
state.Let consider first case where previous state of Q=1 then output of NAND 2 will be 0
as its both inputs are 1. Since we considered Q=1 hence previous tste of Q́ =0 so present
state of Q comes to be 1 which is same as previous state. Now for case 2 we consider
previous state of Q=0 then output of NAND 1 will be 1as its one input is 1. Since we
considered Q=0 hence previous state of Q́ =1 so the output of NAND 1 comes to be 0 which
is the present state of Q.This state is also same as previous state.

Practice question

1. Predict the output of the following circuit.

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