1.

Problem 1 on Multilevel Paging:

Logical Address = 5 bits

Page Size = 8 Bytes

Page Table Entry takes 32 bits

Page Table Entry size = 4 Bytes

What is
Size of PT1 (Inner Most PT) -
Size of PT2
Size of PT3
How does address Split work?

Solution:
Logical Address
Nothing specified so we need to

Assume it is Byte addressable system. p ( 2 bits) d (3 bits)

Here, Page size (d) is 8 B, 5 bits

So Page offset (d ) = 8 = 23 = 3 bits

In order to address 8 Bytes we need 3 bits.

So Page number = 2 bits (5-3=2)

So, Maximum no of pages our process requires = 22 = 4 Pages

So let us draw 4 Pages

Page-0 (00)

Page-1 (01)

Page-2 (10)

Page-3 (11)

Operating System 1|Prepared By: Minal Shah

These pages are going to be stored in non-contagious memory, so it Is going to be stored in random
frames.
SO since it non – contagious memory allocation, we cannot index this process directly by simple
addition, so we will create a One Level of Page Table.

So, Let us create a Page Table (First Level or Inner Level Page Table)

Page-0 (00)

Page-1 (01)

Page-2 (10)

Page-3 (11)

Now how may entries this PT will Have? (4 entries as we have 4 Pages)
But, How many entries one PT can store = 2 [Page size / size of entry = 8 B / 4 B = 2 entries]

Since one page can contain 2 entries, we need one more page to accommodate 4 entries.

Page-0 (00)

Page-1 (01)

Page-2 (10)

Operating System 2 | P r e p a r e d BPage-3

y : M i(11)
nal Shah
 No can we index this Page table in a single addition? ANs : No

You need to keep on creating levels of paging as long as complete Page Table can be fit into single
frame.

So again let us create one more level of Page Table [we are maintaining Page Table of Page Table]

Inner Level PT -1
Page-0 (00)

Page-1 (01)

Outer Level PT -2
Page-2 (10)

Page-3 (11)

Here we can see that all entries can be fit into in a single frame. Here we will stop. PT – 3 is not required.

How addresses will split?

We have 5 bits of LA, as you know this 3 bits (offset) is actually used to pick single byte in a process.

Logical Address
p ( 2 bits) d (3 bits)

5 bits
Within a page , how many bytes are present? 8 Bytes [page size = 8B given]

So every page will have require 8 Bytes.

Operating System 3|Prepared By: Minal Shah

 Inner Level PT -1

To convert LA to PA we will start with Outer Most PT and reach to process.

Logical Address
p ( 2 bits) d (3 bits)

5 bits

Here we are having 2 levels of Page Table split page number in to parts p1 = ____ and p2 = ______

2 bits needs to be split into 2 parts.

Example
Logical Address

0 1 1 1 0
5 bits

Start from outer Most table , 1st Left significant bit is 0.

Operating System 4|Prepared By: Minal Shah

 So it will select upper entry.

Inner Level PT -1 Page-0 (00)

1
Page-1 (01)

0
Outer Level PT -2
1 Page-2 (10)

0
1 Page-3 (11)

Next bit is 1, go to next level, select second entry Next 3 bits are 110 which Is 6.

Outer Level PT -2
Inner Level PT -1 Page-0 (00)

0
1
Page-1 (01)

CPU
PTBR (will hold starting
address of Outer most PT)
Operating System
0
1 Page-2 (10)
Outer Level PT -2
0
1 Page-3 (11)
5|Prepared By: Minal Shah
 So address split will look like this 1 bit 1 bit Logical Address 3 bits
P1 = 1 bit (To index outer most PT)
P1 P2 1 1 0
P2 = 1 bit (To index 2nd level of PT)
5 bits
Offset d = 3 bits

PT-1 (inner most ) Size = size of single page table =8 B , in PT we have 2 tables so total size = 16 B

PT-2 (Outer Most table) = 8 B

PT-3 is not required

2. Problem 2 on Multilevel Paging:

Logical Address = 64 bits

Page Size = 1 MB

Page Table Entry size = 4 Bytes

What is
Size of PT1 (Inner Most PT) – 2 46 B
Size of PT2 -
Size of PT3
How does address Split work?
Maximum no of PT entries in a single Page = ?
How many levels required

ANS :

Logical Address = 64 bits

Page Size = 1 MB

Page Table Entry size = 4 Bytes

What is
Size of PT1 (Inner Most PT) – 2 46 B
Size of PT2 - 28 pages * 220 Bytes = 228 B
Size of PT3 - 28 pages * 22 Bytes = 210 B
How does address Split work? P1 = 8 bits , P2 = 18 bits , P3 = 18 bits, offset = 20 bits
Maximum no of PT entries in a single Page = ? 218 entries
How many levels required? -> 3 levels
How many memory access required? 4 Memory access (no of level + 1) = 3 + 1 = 4

Operating System 6|Prepared By: Minal Shah