In DC motor interfacing, which modulation controls the duty cycle of square wave provided at the

output by generating variation in the average DC voltage?

a) Amplitude Modulation  
1
b) Frequency Modulation  
c) Pulse Width Modulation YES
d) Phase Modulation  
In LCD, which hex command performs the function of 'Display on, cursor on and blinking'?
a) 0x0A  
2 b) 0X0C  
c) 0X0F YES
d) 0X0E  
In LCD, which function is executed by '0x05' hex command?
a) Shift display left  
3 b) Shift display right YES
c) Clear display  
d) Return cursor to home  
Which functional unit of ARM family architecture is responsible for upgrading the address register
contents before the core reads or writes the next register value from memory location?
a) Data bus  
4
b) Barrel Shifter  
c) Instruction Decoder  
d) Incrementor YES
Which type of non-privileged processor mode is entered due to raising of high priority of an
interrupt?
a) User mode  
5
b) Fast Interrupt Mode (FIQ) YES
c) Interrupt Mode (IRQ)  
d) Supervisor Mode (SVC)  
In LPC 2148, which among the following is/are the functions of Mask register?
a) Byte addressability  
6 b) Relocation to ARM local bus for fastest possible I/O timing  
c) Treating sets of port bits in the form of group without changing other bits YES
d) All of the above  
In the process of pipelining, which instructions are fetched from the memory by the ARM processor
during the execution of current instruction?
a) Previous  
7
b) Present  
c) Next YES
d) All of the above  
How is the nature of instruction size in CISC processors?
a) Fixed  
8 b) Variable YES
c) Both a and b  
d) None of the above  
What is/are the configuration status of control unit in RISC Processors?
a) Hardwired YES
9 b) Microprogrammed  
c) Both a and b  
d) None of the above  
 While designing an embedded system, which sub-task oriented process allocates the time steps for
various modules that share the similar resources?
a) Simulation and Validation  
10
b) Iteration  
c) Hardware-Software Partitioning  
d) Scheduling YES
Which type of handshake packet indicates that the device is incapable of accepting data as it is
supposed to be busy with some another task?
a) ACK  
11
b) NAK YES
c) STALL  
d) None of the Above  
In Von Neumann architecture, which among the following handles all the operations of the system
that are inside and outside the processor?
a) Input Unit  
12
b) Output Unit  
c) Control Unit YES
d) Memory Unit  
What is the processor used by ARM7?
a) 8-bit CISC  
13 b) 8-bit RISC  
c) 32-bit CISC  
d) 32-bit RISC YES
What is the instruction set used by ARM7?
a) 16-bit Instruction set  
14 b) 32-bit Instruction set YES
c) 8-bit Instruction set  
d) 64-bit Instruction set  
How many registers are there in ARM7?
a) 35 registers (28 GPR and 7 SPR)  
15 b) 37 registers (28 GPR and 9 SPR)  
c) 37 registers (31 GPR and 6 SPR) YES
d) 35 registers (30 GPR and 5 SPR)  
ARM7 has an in-built debugging device?
a) Yes YES
16 b) No  
c) 0  
d) 0  
What is the capability of ARM7 f instruction for a second?
a) 130 MIPS YES
17 b) 110 MIPS  
c) 150 MIPS  
d) 125 MIPS  
What are T, D, M, I stands for in ARM7TDMI?
a) Timer, Debug, Multiplex, ICE  
18 b) Timer, Debug, Modulation, IS  
c) Thumb, Debug, Multiplier, ICE  
d) Thumb, Debug, Multiplier, ICE YES
19 What are the profiles for ARM architecture?
 a) A-profile, Application profile  
b) M-profile, Microcontroller profile  
c) R-profile, Real-time profile  
d) All of the above YES
ARM7DI operates in which mode?
a) Big Endian  
20 b) Little Endian  
c) Both a and b YES
d) None of the above  
What are the pipelining stages include?
a) Fetch, Decode, Write  
21 b) Fetch, Execute, Write  
c) Fetch, Decode, Execute, Write  
d) Fetch, Decode, Execute YES
What are the no of pins that are in the ARM7 processors?
a) 64 pin with QFP YES
22 b) 46 Pin with QFP  
c) 64 pin with LLC  
d) 46 pin with DIP  
Using what the processor wake-up from power-down?
a) External Interrupt YES
23 b) Serial Programming  
c) Internal Interrupt  
d) Program Counter  
What are the categories in the vectored interrupt controller?
a) Fast interrupt request  
24 b) Non vectored interrupt request  
c) Non-vectored IQR  
d) All of the above YES
What is the size of ADC and DAC?
a) 16 bit  
25 b) 32 bit  
c) 10 bit YES
d) 8 bit  
The ARM7TDMI-S uses which pipelining?
a) 1-stage  
26 b) 2-stage  
c) 3-stage YES
d) 4-stage  
The ARM7TDMI-S processor has __________ types of memory cycle.
a) 4 YES
27 b) 1  
c) 6  
d) 2  
Two wire interface is also called as _________
a) SPI  
28
b) I2C YES
c) UART  
 d) USART  
I2C in LPC2148 will address _______ number of slave devices.
a) 32  
29 b) 64  
c) 128  
d) 256 YES
I2C will address large number of slave devices.
a) TRUE YES
30 b) FALSE  
c) 0  
d) 0  
SDA is having a ____________transition when the clock line SCL is high.
a) High to Low YES
31 b) Low to High  
c) Low to Low  
d) High to High  
Inter Integrated Circuit is a ____________.
a) Single master, Single Slave  
32 b) Multi Master, Multi Slave YES
c) Single Master, Multi Slave  
d) Multi Master, Single Slave  
Master transmits means _________
a) Master node is receiving data from slave  
33 b) Slave node is transmitting data to master  
c) Master node is sending data to a slave YES
d) Slave node is sending data to master  
Who transmits the Start Bit?
a) Master Receive  
34 b) Slave Receive  
c) Master Transmit YES
d) Slave Transmit  
SPI device communicates in _________
a) Simplex  
35 b) Full Duplex YES
c) Half Duplex  
d) Both b and c  
How many logic signals are there in SPI?
a) 4 Signals YES
36 b) 5 Signals  
c) 3 Signals  
d) 2 Signals  
RISC Philosophy implemented with ___ major deign goals.
a) 6  
37 b) 8  
c) 4 YES
d) 2  
___ is the processing of instruction broken down to smaller unit.
38
a) ALU  
 b) CPU  
c) MCU  
d) Pipeline YES
Register contains
a) Addresses  
39 b) Data  
c) Both a and b YES
d) None of the above  
__ is used to communicate between part of the device
a) ALU  
40 b) BUS YES
c) MCU  
d) Perepherals  
____ is used to connect peripherals.
a) BUS  
41 b) PCI YES
c) MCU  
d) ALU  
_____ level covers electrical characteristics.
a) Logical  
42 b) Electrical  
c) Physical YES
d) All of the above  
____ level govern communication between the processor and peripheral.
a) Electrical  
43 b) Physical  
c) Logical YES
d) All of the above  
AMBA means____
a) Advance Microcontroller Bus Architecture YES
44 b) Advance Machine Bus Architecture  
c) None  
d) All of the above  
____ is placed between main memory and core .
a) RAM  
45 b) ROM  
c) Cache YES
d) All of the above  
____ is used to sped up data transfer
a) ROM  
46 b) Cache YES
c) RAM  
d) None of the above  
____ interrupt controller available in ARM Processor.
a) 4  
47 b) 3  
c) 2 YES
d) 1  
 Application of ARM processor is____
a) Automotive  
48 b) Consumable  
c) Mobile  
d) All of the above YES
General purpose registers holds the _____
a) Address  
49 b) Data  
c) Both a and b YES
d) None of the above  
The SPSR store the ___ mode of CPSR
a) Present  
50 b) Previous YES
c) Both a and b  
d) None of the above  
____ are used to stop specific interrupt
a) Interrupt request  
51 b) Interrupt Mask YES
c) None  
d) All of the above  
How many bank registers are available in ARM?
a) 16  
52 b) 20 YES
c) 24  
d) 30  
____ instruction perform bitwise operations
a) Compare  
53 b) Arithmatic  
c) Logical YES
d) None of the above  
Thumb code usually uses more instructions for the _____ job.
a) Same YES
54 b) Different  
c) Both a and b  
d) None of the above  
___is provided to service data transfer or communication channel with low latency.
a) SWI  
55 b) IRQ  
c) FIQ YES
d) None of the above  
The access time reading or writing a MMR depends on the___
a) AMDA  
56 b) AMBA YES
c) AMCA  
d) AMEA  
ADC consists of a _____bit successive-approximation converter
57 a) 4  
b) 8  
 c) 7  
d) 12 YES
Single or continuous conversion modes can be initiated in ____
a) Firmware  
58 b) Hardware  
c) Software YES
d) All of the above  
The MOSI pin is configured as an ____line in master mode
a) Input  
59 b) Output YES
c) Both a and b  
d) None of the above  
The master serial clock (SCL) is used to ______the data
a) Asynchronise  
60 b) Synchronise YES
c) Both a and b  
d) None of the above  
The main importance of ARM micro-processors is providing operation with ______
a) Higher degree of multi-tasking  
61 b) Lower error or glitches  
c) Efficient memory management  
d) Low cost and low power consumption YES
ARM processors where basically designed for _______
a) Main Frame System  
62 b) Distributed System  
c) Super Computer  
d) Mobile Systems YES
The ARM processors doesn’t support Byte address ability ?
a) TRUE  
63 b) FALSE YES
c) 0  
d) 0  
The address space in ARM is ______
a) 2^8  
64 b) 2^16  
c) 2^32 YES
d) 2^4  
In ARM, PC is implemented using ____
a) Cache  
65 b) Stack  
c) General Purpose Register YES
d) RAM  
Each instruction in ARM machines is encoded into ____ Word.
a) 2 Byte  
66 b) 3 Byte  
c) 4 Byte YES
d) 1 Byte  
67 In the process of pipelining, which instructions are fetched from the memory by the ARM processor
during the execution of current instruction?
 a) Next YES
b) Present  
c) Previous  
d) All of the above  
How is the nature of instruction size in CISC processors?
a) Variable YES
68 b) Fixed  
c) Both a and b  
d) None of the above  
Which microcontrollers are adopted for designing medium scale embedded systems?
a) 8-bit  
69 b) 16-bit  
c) 32-bit  
d) 16-bit to 32-bit YES