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  • Mainconzvs PDF

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    Roy Reynald
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    1. The document describes a high voltage direct current (HVDC) circuit design with key components including capacitors, resistors, transistors, and transformers. 2. The circuit uses transistors like the STW15NB50 to regulate current flow and components like the 1U63MKS2 capacitor to stabilize voltage. 3. The design aims to efficiently transmit power over long distances using direct current at high voltages enabled by converters on both ends of the transmission line.

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    mainconzvs.pdf

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    1. The document describes a high voltage direct current (HVDC) circuit design with key components including capacitors, resistors, transistors, and transformers. 2. The circuit uses transistors like the STW15NB50 to regulate current flow and components like the 1U63MKS2 capacitor to stabilize voltage. 3. The design aims to efficiently transmit power over long distances using direct current at high voltages enabled by converters on both ends of the transmission line.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    29 views1 page

    Mainconzvs PDF

    Uploaded by

    Roy Reynald
    1. The document describes a high voltage direct current (HVDC) circuit design with key components including capacitors, resistors, transistors, and transformers. 2. The circuit uses transistors like the STW15NB50 to regulate current flow and components like the 1U63MKS2 capacitor to stabilize voltage. 3. The design aims to efficiently transmit power over long distances using direct current at high voltages enabled by converters on both ends of the transmission line.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
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    of 1

    1 2 3 4 5 6 7 8

    +HVDC

    2
    +HVDC

    C1 C2
    100N630PHE428 100N630PHE428

    1 1
    A A
    C4 R1 R3 C13
    Q3 Q2
    1U63MKS2 10RM 10RM 1U63MKS2

    3
    +18V DRVB2 STW15NB50 STW15NB50 DRVA2

    BZX79C20
    3 T4 46:(13+13):1 3

    BZX79C20 BZX79C20
    L leakage = 19uH
    +18V 100T3F3R10
    1 L mag = 250uH 1

    D6
    4 1 2 4

    D4
    D3 5 5 D8
    +18V +12SV SS34 2 T3 C10 T2 2 SS34

    15

    16
    BZX79C20

    1
    XFMRDUALGD 1U400PMR XFMRDUALGD

    4
    6 6
    3 1
    Vin Vout

    D7

    D5
    DRVB1 DRVA1

    2
    U8 13
    78L12
    2

    C28
    10U16ERAD D2 R2 R4 D9
    SS34 10RM T1 10RM SS34

    10
    XFMR1

    9
    8

    6
    5
    4
    1 1 U15
    78L05
    +5VA
    Q4 Q1

    3
    STW15NB50 STW15NB50 3 1
    Vin Vout
    RTN

    MBR160

    MBR160
    B B

    4N7YCAP

    2
    D20

    D19

    10U16ERAD

    10U16ERAD
    +5VA +12SV

    C29
    100N63MKS2
    8
    VCC

    1N4148

    1N4148

    1N4148

    1N4148
    2 6

    C23

    C24
    MBR160
    A Vout

    MBR160
    C14

    D12

    D13

    D11

    D10
    R9 R28

    D18
    D17
    330RM 10KM
    3

    3
    K
    5
    R10 GND
    4K7M 2 U5 R24 L1
    PSUSD D1
    6N135 R23 12RM 1 40UH77894 +75V
    Q6 100RM R30 Minimum Load Load dump voltage clamp
    270RP6W
    R99 2N3904 I limit = 8.3A C27 2
    +75V
    C20 100P400PFR5
    1

    3K3M
    1NCER 3

    HFA30TB60C

    1K2P6W
    C8

    R31
    2200U100ERADTSU D36 D37 D38
    U1C
    5KP24A 5KP24A 5KP24A
    8 4011
    0V
    +12SV 10 +12SV
    9 +5VA +75V
    C16
    100N63MKS2
    C C
    R27 D14 R16 R14 R11
    10KM 1N4148 12 2 10KM C15
    820RM 22KM
    11 C5 +18V C3 100N63MKS2 R19
    PFCENABLE R17
    SVRST 13 1U63MKS2 47U16ERAD 1 62KM
    120KM 6 3
    U1D

    2
    D16 R22
    20

    C22 4011 5 4
    1N4148 5K1M R12
    1U63MKS2 U7 68KM
    ML4818 2 2 2 2 W Adj for 75V
    VCC

    10 U6
    SDOWN R20
    17 DRVB1 HCNR200
    A1OUT
    5VREF 24 Q13 Q9 Q7 Q8
    130KM

    VREF 1K3266W
    2N3906 2N3904 2N3906
    R21

    2N3904

    1
    5VREF +HVDC 13 16 DRVB2
    1N100FKC2

    CLOCK A2OUT
    R15 R13 R18
    1

    4 22RM 10RM 2KM


    CS
    22 DRVA1
    330K1W

    C17
    C18

    R7
    C19

    B1OUT
    1NCER

    1U63MKS2 1KM 8
    EA-
    2N3906

    R29

    2
    5 21 DRVA2
    EAOUT B2OUT
    Q5

    +12SV C25
    SYNC8fs
    C12 3 100N63MKS2
    RAMP
    12PCER D15 11 12
    3

    RT RCRST
    C9 +12SV 2

    14
    100N63MKS2 CT
    2 1 U1B
    R6 1N4148 14
    R103 RDELAY 4011
    C11 560RM 9 1 5
    2K3266W SS
    R25 3 4
    GND
    GND
    GND
    GND
    GND
    GND
    GND

    D 100PCER D
    W

    680P100FKC2

    1U63MKS2
    1K5M

    8 13KM 2 6
    1U63MKS2

    VDD
    2
    240KM
    R8

    470PCER

    A U1A
    7 Tdelay = 250ns
    R26
    C21

    Vout 4011
    R5 Title
    C26

    15
    18
    19
    23
    1
    6
    7

    7
    C7

    C6

    3 6 5K6M Main dc:dc converter - power stage


    K E
    5
    VSS
    Size Number Revision
    U4 f_osc = 2x 169kHz (free)
    HCPL-2200
    A3 A
    f_osc = 2x 176.4kHz (locked) Date: 03/05/2005 Sheet 3 of 5
    File: D:\john\..\maincon1.sch Drawn By: JFH
    1 2 3 4 5 6 7 8

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