System-On-Chip Architectures

Madhura Purnaprajna
 Organisation
• Log in to www.piazza.com for announcements,
course lectures, reading material, etc.
– Request email ids.
 Course Structure
• Fundamentals of Digital Design
• FPGA Architecture and Synthesis
• HW-SW based system design

• Reading list:
– Top 10 Microarchitecture Research Papers
• Assignments
– Design problems

• Project
– Accelerate your design using SoCs (2-member team)
 Course Objectives
• System on Chips

• All about SoCs:

– When did they come into existence?
– Why we need SoCs?
– How do we use them?
– Where are they being used?
 Goals
• Write applications for FPGAs
• Simulate/Functional validation
• Map/Run onto real FPGAs
• Performance Analysis
– optimize for time/power/area/speed
 My Interests
• FPGA Architectures and Synthesis
– projects! (Ask me)
• CPU/FPGA-based computing
• FPGA design: Circuit-level design
• Soft processor/GPU Computing
Introduction to FPGAs
 Application-driven Industry
Applications

Multimedia
HPC

Communication
Medical Electronics

Time
Power
Target Devices

9
 This presentation: Embedded Computing

Create Synergy

Embedded CPU Field Programmable Gate Arrays

Target Devices

10
The two domains ...

11
Processors
• Sequential computing
• Instruction-level parallelism
Instruction Memory

Decoder

Registers

ALU

Data Memory

Registers

12
 FPGAs
• User configurable
• User-defined parallelism

FFs FFs FFs

00 0
01 1 FU FU FU
10 1
11 1 FFs FFs FFs
FU FU FU

FFs FFs FFs

FU FU FU

13
 Application Mapping

Processor FPGA

<N

14
 Temporal vs Spatial Computing
Processor FPGA

Instruction Memory
FFs FFs FFs
00 0
Decoder 01 1 FU FU FU
10 1
Registers 11 1 FFs FFs FFs
FU FU FU
ALU
FFs FFs FFs
Data Memory
FU FU FU
Registers

x Limited parallelism ✓ User-defined parallelism

x Fixed architecture ✓ Flexibility
x Scalability? ✓ Performance per Watt 15
Application Mapping

Application

Algorithm

Programming

Optimisations

Architecture

Fabrication

Device

16
Design Effort: ASIC

HDL

Logic Synthesis

Technology Mapping

Place & Route

Fabrication

ASIC

17
Design Effort: FPGA

HDL

Logic Synthesis

Technology Mapping

Pack, Place & Route

FPGA

18
Design Effort: Processor

HLL

Compilation

Processor

19
 Application-to-Algorithm

HLL T HDL 100T

Compilation Logic Synthesis

Processor Technology Mapping

Pack, Place & Route

FPGA

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 Algorithm-to-Architecture

HLL HDL

Compilation few mins Logic Synthesis mins/hours

Processor Technology Mapping

Pack, Place & Route

FPGA

21
Application-to-Architecture

HLL HDL

Compilation mins Logic Synthesis hours/days

Processor Technology Mapping

Pack, Place & Route

FPGA

22
 Processor v/s FPGA

Processors
Ease of Adaptability

~35x
Area
~5x
FPGA Speed
~15x
Power

ASIC

Performance 23
 Its Melting!

1/4/2020 24
 How?

1/4/2020 25
 Can Intel cope?

1/4/2020 26
 Intel Acquires Altera

1/4/2020 27
UNIQUE TO FPGAS
FPGA Fabric

Block RAMs
DSP Blocks
Configurable Logic Blocks

29
 FPGA Fabric: User configurable

Block RAMs
DSP Blocks
Configurable Logic Blocks
Multi-issue Processor

Multiplier, Shifter Instruction Memory

Data Memory
ALU, multi-ported register files, multiplexing,
control logic, state-machines, etc Up to 2-port Register File

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FPGA Fabric: User configurable

Image Processing
Block RAMs

Controller
Processor

Ethernet
Crypto

DSP Blocks
Configurable Logic Blocks

31
Run-time Reconfiguration

MIPS Processor
Block RAMs

Game: Chess
Processor
Graphics

DSP Blocks
Configurable Logic Blocks

32
The new computing eco-system
 Reality
Applications

Language Language Language Language Language

Compiler Compiler Compiler Compiler Compiler

Target Devices

34
 In an ideal world …
Applications

Multimedia
HPC

Communication
Medical Electronics
Universal Compiler
Target Devices

35
 A new computing eco-system …
Applications

Multimedia
HPC

Communication
Medical Electronics
Universal Compiler
Single Device

36
Variations for a Single Architectural Template