20/07/2018 Vlsi Physical Design - - Unit 2 - Week 1

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Unit 2 - Week 1

Course
outline Week 1 Assignment
The due date for submitting this assignment has passed. Due on 2018-02-05, 23:59 IST.
How to access the
portal Submitted assignment

Week 1 1) Which of the following statements is false? 1 point

Lecture 1: The truth table of the function with output column (01010111) represents a behavioral representation of
Introduction the function.

Lecture 2: Design
The Verilog specification: “assign f = (A & B) | C;” represents a structural representation of the function
Representation f.
A netlist consisting of one 2-input XOR and one 2-input OR gate represents a behavioral
Lecture 3: VLSI
Design Styles representation.
(Part 1) A netlist of predefined modules in Verilog represents a structural representation.
Lecture 4: VLSI No, the answer is incorrect.
Design Styles
Score: 0
(Part 2)
Accepted Answers:
Lecture 5: VLSI
The Verilog specification: “assign f = (A & B) | C;” represents a structural representation of the function f.
Physical Design
Automation (Part
A netlist consisting of one 2-input XOR and one 2-input OR gate represents a behavioral representation.
1)
2) Which of the following statements is true for a 4-input LUT in a typical FPGA? 1 point
Lecture 6: VLSI
Physical Design It can be implemented using a 16x1 static memory block.
Automation (Part It can implement any function of 2-, 3- or 4-variables.
2)
It can implement any function of 4 variables only.
Week 1 Lecture It can also implement a few functions of 5 and 6 variables.
Material
No, the answer is incorrect.
Feedback for
Week 1
Score: 0
Accepted Answers:
Quiz : Week 1
Assignment
It can be implemented using a 16x1 static memory block.
It can implement any function of 2-, 3- or 4-variables.
Lecture 1: Note
3) Identify the incorrect statements corresponding to VLSI design styles. 1 point
Lecture 2: Note
In the gate array design style, floorplanning and placement represent the same problem.
Lecture 3: Note
In standard cell design style, the dimensions (heights and widths) of all the cells are the same.
Lecture 4: Note
For the full-custom design style, floorplanning and placement represent the same problem.
Lecture 5: Note Standard cell based design leads to faster circuit realizations as compared to FPGA based design.
Lecture 6: Note
No, the answer is incorrect.
Week 1 Score: 0
Assignment
Accepted Answers:
Solution
In standard cell design style, the dimensions (heights and widths) of all the cells are the same.
Week 2 For the full-custom design style, floorplanning and placement represent the same problem.

4) The minimum number of 4-input LUTS required to realize the following netlist will be ……….., where each
Week 3
rectangular block represents a logic function.

Week 4

Week 5

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20/07/2018 Vlsi Physical Design - - Unit 2 - Week 1

Week 6

Week 7

Week 8

Week 9

Week 10

Week 11

Week 12:

DOWNLOAD
VIDEOS

Supplementary
Demo Tutorials

Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Numeric) 4

1 point

5) Consider a gate array fabrication facility, where the chips designed by three customers X, Y and Z are being
fabricated. X orders 1,000 units, Y orders 2,000 units and Z orders 1,500 units of chips. Assume that the cost of
fabricating the generic masks corresponding to a design is Rs. 5 lakhs, and the cost of customization is Rs.
50,000 for every 500 chips. The total cost of fabrication of all the 4500 chips will be Rs. ………. Lakhs.

Hint

No, the answer is incorrect.

Score: 0
Accepted Answers:
(Type: Numeric) 19.5

1 point

6) Which of the following can be true for standard cell based designs? 1 point

The widths of three cells are 15, 25 and 35 units respectively.

The heights of three cells are 10, 12 and 15 respectively.
For inter-row interconnections, feed-through cells are required.
Design turnaround time is slower as compared to full custom design.

No, the answer is incorrect.

Score: 0
Accepted Answers:
The widths of three cells are 15, 25 and 35 units respectively.
For inter-row interconnections, feed-through cells are required.

7) Which of the following represents the correct ordering with respect to speed of circuits (slowest to 1 point
fastest)?

FPGA, Gate array, Standard cell, Full custom

FPGA, Gate array, Full custom, Standard cell
Gate array, FPGA, Standard cell, Full custom

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20/07/2018 Vlsi Physical Design - - Unit 2 - Week 1

Gate array, FPGA, Full custom, Standard cell

No, the answer is incorrect.

Score: 0
Accepted Answers:
FPGA, Gate array, Standard cell, Full custom

8) What is the main objective of floorplanning? 1 point

Given a set of blocks with defined shapes and pin locations, determine their positions on the layout.
Given a set of blocks with flexible shapes, determine their positions on the layout along with spaces for
routing.
Given a set of blocks with flexible shapes, determine their positions on the layout with accurate
estimation of wire lengths.
None of the above.

No, the answer is incorrect.

Score: 0
Accepted Answers:
None of the above.

9) Which of the following is true for clock routing? 1 point

Tries minimize the total interconnection length

Tries to minimize the worst-case delay
Tries to minimize the skew
None of the above

No, the answer is incorrect.

Score: 0
Accepted Answers:
Tries to minimize the skew

10)Match the following. 1 point

i. Takes a set of blocks of defined shapes and pin locations, and assigns the blocks
to exact locations on the layout surface.
A. Partitioning
ii. Takes the netlists in some particular order, and provides interconnection among
B. Floorplanning
them.
C. Placement
iii. Tries to assign tentative locations of the blocks on the layout area.
D. Routing
iv. Breaks a netlist into several pieces that can be laid out separately on the layout
surface.

A-(iv), B-(iii), C-(i), D-(ii)

A-(iv), B-(i), C-(iii), D-(ii)
A-(iv), B-(ii), C-(i), D-(iii)
None of the above

No, the answer is incorrect.

Score: 0
Accepted Answers:
A-(iv), B-(iii), C-(i), D-(ii)

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