4.

HF transistors

1
 Outline

Microwave and mm-wave transistors

High-frequency figures of merit

MOSFET structure & HF equivalent ckt.

SiGe HBT structure & HF equivalent ckt.

FETs vs. Bipolars

2
 Solid-State Electronic Devices

Unipolar Bipolar
Bipolar Junction Transistor
Field-Effect Transistor
Heterojunction Bipolar Transistor

J-FET “Homojunction”
CMOS
Si Bipolar Junction
MOSFET Transistor (BJT)
Si, SiGe
Si
MESFET Heterojunction
LDMOS GaAs
HEMT
Bipolar Transistor
Si (HBT)
GaAs, InP, GaN
GaAs, InP, SiGe

MG-MOSFET p-HEMT m-HEMT

Si, SiGe GaAs, InP, GaN

MG m-MOSFET InGaAs, Ge on Si?

3
 µ -wave & mm-wave transistors

SiGe HBT InP (GaAs) HBT

4
 µ -wave & mm-wave transistors
Si MOSFET

tensile stress film compressive stress film

gate gate

oxide source drain oxide source drain oxide

p-sub (SiGe) n-sub (SiGe)
STI
n-MOS STI
STI
p-MOS STI

5
 22-nm ETSOI IBM/ST/LETI/GF/SOITEC

K. Cheng et al. Paper 18.1, IEDM 2012

S. Narasimha et al. Paper 3.3, IEDM 2012

6
 Intel 22-nm FinFET
Fin not thin enough for fully depleted
Fin had to be doped=> bad for speed

C.-H. Jan et al.

Paper 3.1, IEDM 2012

7
 What drives device performance?
Material properties
electron mobility (InP > SiGe > Si)
hole mobility (SiGe > Si > InP)
saturation velocity (InP > Si/SiGe)
breakdown field (InP > Si)
thermal conductivity (Si > SiGe > InP)
Lithography (Si > InP)
Yield & reliability (MOS > SiGe HBT > InP HBT)

8
 FET
Unipolar: electrons or holes
Intrinsic device speed is
laterally defined by L
lithography driven.
Gate
vs. HBT
Bipolar: electrons & holes
intrinsic device speed is
vertically defined by WB
atomic layer growth driven
Emitter
Depletion Layer

Qc L
WB
Base
Depletion Layer
εr t

-Qch Channel
Collector

In both cases, real device speed is affected by 3-D parasitics.

Scaling in 2D and 3D is important.

9
 MOSFET vs. HEMT
Mostly on silicon III-V and Si, SiGe
MOS insulator gate Schottky gate
No gate current * Gate current (small)
Inversion channel Accumulation channel
Both p-type and n-type Mostly n-type
Substrate node must be Substrate node not biased,
biased connected to ground (as in SOI
MOSFETs)

The same DC I-V characteristics and small-signal equivalent

circuit

Q =C W V −V ; I =Q v E
n gate GS T  DS n n

10
Typical Forward HBT Gummel Plot

 
IC =JS A E e xp
V BE
VT
1
V CE
VA 
11
 Transfer characteristics in 90-nm n-MOS
Square-law in sub 130-nm MOSFETs invalid for most bias range

IDS=k ' n LW  V GS−V T 

12
Typical HBT output characteristics
Apparent negative ro
due to self-heating

IC =JS AE exp  
VBE
VT
1
V CE
VA 
13
45-nm SOI MOSFET output characteristics

Low output
resistance

14
 DC Characteristics
FET vs. HBT

Transfer Characteristics: Transfer Characteristics:

Exponential in subth.
Square-law or linear in
saturation region
Low turn-on voltage: 0.5 to
0.2 V
Output Characteristics
Small VA (ro)
Low breakdown
Exponential
High turn-on voltage: 0.7 to
0.9 V
Output Characteristics
Large VA (ro)
Moderate breakdown

15
 HF equiv. circuit and y-matrix of intrinsic
CE/CS transistor
Cbc Cgd
C G D
B Cgs vgs
Cbe rπ ro Ccs
Vbe ro Cdb
Ri gme-jω τ vgs
gmvbeejω τ n

E S

[ ][y
W
=
j C' g sC' g d −j C' g d
g ' m −j C' g d g ' o j C' d bC' g d  ] [ g  j Cb e Cb c 
; [ y ]= 
g m −j Cb c
−j Cb c
g o j CcsCb c  ]
Input admittance and voltage gain for 2-port loaded by
admittance YL YIN =Y1 1 −
Y1 2 Y2 1
and Gv =
−Y2 1
YL Y2 2 YL Y2 2

16
 Common base/gate and cascode
FET/HBT in CG/CB

[ ][
y
W
g ' g ' o j C' gsC' s b 
= m
−g ' m −g ' o
−g ' o
g ' o j C' d b C' g d 
;
]
[
[ y ]=
g m g o g  j Cb e
−g m −g o
−g o
g o  j CcsCb c  ]
FET/HBT in cascode topology
Y12 , CS Y21,CS −Y2 1 , CS
YIN =Y11, CS − Gv casc=
Y Y
Y22 ,CS Y11 ,CG− 12, CG 21,CG
YL Y22,CG Y12,CG−
[ Y1 1 , CGY2 2, CS
Y2 1 , CG ]
[ YL Y2 2 , CG]

17
 CE/CS HF circuit useful for hand analysis
Rg(b) Cg d(bc) Rd(c)
RG(B) Cgd(bc)
G(B) D(C)
Cgs(be) Vgs(be) D(C)
ro Cdb(cs) G(B)
g m e−j   v g sb e
Cgs(be)eff VIN gmeff VIN goeff Cdb(cs)

Rs(e)

S(E) S(E)

Impact of Rs(rE) included in RG(b), gm, fT and Cgs/Cb e

RG= Rg+Rs (can be used directly in Zi \n, NFMIN, Zsopt)

Zin= Rg+Rs – jfT/(fgmeff)

18
 Outline

Microwave and mm-wave transistors

High-frequency figures of merit

19
Figures of Merit (FoMs) for HF & High-Speed ICs

Devices: fT, fMAX, FMIN, BV

Circuits:
G×IIP3×f OIP3×f
FoMLNA= =
F−1 ×P F−1 ×P

FoMSERDES =
RB×MUXratio
P
FoMVCO=
 
fo
f
Pout
L〚 f〛×P

Z×IMAX ×BW3dB 2
FoM TIA = rm s FoMPA =Pou t ×G×PAE×f
i n ×P
20
 Device Figures of Merit

Cutoff frequency definition

Maximum oscillation frequency definition

Minimum noise figure and noise parameters

Intrinsic slew rate

21
fT definition: 20*log10|H21(f=fT)| = 0

Y 21 gm gm Y2 1 T
H21= ≈ ≈ H 2 1= ≈
Y 11 jCgsCgd  jCbeCbc  Y1 1 j 

1 C C gd
= gs C gd R sRd 
2 f T gm

1 Cbe C bc 
= r ErC C bc
2  fT gm

22
 fMAX definition MAGdB(f) =10*log (MAG)=0dB

fMAX is defined as the x-axis intercept of the power gain vs.

frequency plot.
Both MAG(f) and U(f) intercept the x-axis at the same point

10*log10U(f) has constant slope (approx. 20 dB/decade) and is

easier to extrapolate
Both can be calculated from measured S or Y parameters

23
U as a function of transistor 2-port params
(Mason, 1953)

U= 4 [ ℜ y 11
∣y 21−y 12∣ 2

 ℜ  y 22−ℜ  y 12 ℜ y 21 ]
MAG= ∣ ∣
S2 1
S1 2
k − k −1 
2

2 2 2
1−∣S11∣ −∣S22∣ ∣D∣
∣z 21−z 12∣2 k=
U= 4[ ℜ z 11  ℜz22 −ℜ z12  ℜz21 ] 2∣S12∣∣S21∣

D=S11×S22−S21×S12

fMAX (unlike fT) contains information about output impedance

24
fMAX definition: U vs. MAG (same x-axis intcp.)

25
Noise params of intrinsic CE/CS transistor
Noiseless
i
2 Y-matrix i
2
〈I 2n 2 〉
Rn =
n1 n2
2-port 2
4 kT  f ∣y 2 1 ∣

Gu =
〈I2n 1 〉
−
〈In 1 In* 2 〉
∣
4 kT  f 4 kT  f Rn ∣Y2 1∣2 ∣ Gsopt =
Gu
Rn 2
Gcor

〈 In 1 I*n 2 〉 FMIN =12R n Gcor Gsopt 

Ycor =y 1 1−
4 kT  f Rn y 2* 1
Gu , Gsopt decrease with correlation, Rsopt increases
FMIN decreases with correlation
26
Noise parameters of the CG/CB transistor

〈I2n2 〉
Rn = 2
4 kT  f∣y 21 ∣
2

∣ ∣
2 *
〈I 〉
n1 〈I I 〉
n1 n2
Gu = − 2
4kT  f 4 kT  f Rn∣Y 21∣

*
〈In1 In2 〉
Y cor =y 21y 11
4 kT  f Rn y *21

Note: y-matrix is that of CG configuration

imag(Y21+Y11) in CG/CB ≠ imag(Y11) in CS/CE

27
 Important ramifications for LNA design

Rn (CG) = Rn (CS)

Gu (CG) = Gu (CS)

Gcor (CG) = Gcor (CS)

FMIN (CG) ≈ FMIN (CS)

If correlation is weak, Imag(Ycor,Ysopt) = Imag (Yin) and can

be tuned out simultaneously

28
Noise equivalent circuit of intrinsic HBT
Noiseless RB
B C
2
i
n1
Y-matrix 2
i
n2 <inB> cπ βib <inC>
2-port
E


〈i i 〉=2q  f IB ∣1−e
*
nB nB
∣ IC 
−j n 2

*
〈inC inC 〉=2q  f IC

*
〈inB inC 〉=2qIC [exp  j n −1]

29
MESFET (MOSFET) Intrinsic Noise Currents
(Pucel 1975)
af
I
∣In d2∣=4 k T  f Pg m K f DS
f

f 2 P (γ ) = 2/3 (long channel)

∣In g2∣=4 k T  f R g m 2
fT
R (β ) = 4/15 (long channel)

In g Inx d
jC = j0.4 (long channel)
jC=
∣I ∣∣I ∣
nd
2
ng
2

Large noise signal model

30
 FET Noise Sources (C. Enz MTT 2002)

 = 2/3 (long
channel)
2
gm
∣In d2∣=4 k T  f g m K f  = 4/15 (long
Co x l g W f a f
channel)
Cgs 
2 In g Inx d
2 jC=
∣I ∣=4 k T  f  g
ng ∣I ∣∣I ∣
nd
2
ng
2
jC = j0.4 (long
m
channel)
31
 Pospieszalski T-dependent model (1989)
Vng , Tg, at input due to thermal noise from Ri
Ind, Td, at output to describe drain current noise
Ind and Vng are not correlated
Not large signal model
V2n d
V2ng Rg Cgd Rd
G D
Cgs vgs
ro Cdb
cds
Ri gme-j ωτ vgs
2
V ngs =4 k T g  f R i I2gs

V2n gs
I2nd
V2n b 2

2 Rdsub
I nd =4 k T d  f g o Rs Csb

V2n s
2 Rssub
I =2q  f I g
gs
V2n b 1
B
S

32
Generating fT,fMAX and NFMINvs. IC/D plots

Increasing Vbe

fT is the intercept: 113 GHz.

33
n-MOSFET characteristic current densities
invariant across nodes and foundries

34
 Characteristic current densities (ii)
JpfT = where fT reaches its max (n-FETs= 0.3-0.4 mA/µ m)

JpfMAX=where fMAX reaches its max (n-FETs= 0.2-0.3 mA/µ m)

JOPT=where NFMIN reaches its min (n-FETs=0.15-0.2 mA/µ m)

Note: All characteristic current densities have started to

increase at the 45-nm node and beyond because of strain
and lack of EOX scaling

35
 Characteristic current densities (iii)
In HBTs JOPT is a function of frequency
In HBTs JpfT, JpfMAX and JOPT increase in every new node)

36
 Impact of FET parasitic source/gate
resistances
gm Cg sCg d 
g m e≈ 1
1 g m Rs ≈ Rs Rd Cg d
2 f T gm
Rs has greater impact than Rg

Rg is always accompanied by Rs fT
f MAX≈
2  R i R s R g g o2  f T R g C gd
Making Rg << Rs is not effective

k1 depends on correlation (approx. 0.5)

f
FMIN≈1 2 k 1
fT
 g m Rs Rg 1

ZSOPT FET≈
1
 Cgs Cgd  [ gm R s R g 
k1 ]
j =
f Teff
f g meff [ g 'm R 'sW f R 'g  W f 
k1
j
]
37
 HBT fT, fMAX, NFMIN vs. IC characteristics
F

[ ]
2
1 1 WB WB XC kT CBE CBC
==    CBE CBC r Cr E CBCr C CCS≈F
2  fT  DB v exit 2 v SAT qIC gm

f MAX ≈
 fT
8  r B C BC

ZSOPT HBT≈
1
C beCbc  [ gm
2 ]
r E R b  j =
f Teff
f gmeff [ gm
2
r E R b  j ]
1 f
FMIN HBT ≈1 
 f Teff
 2 gm R b r E 

38
 Intrinsic Slew Rate

IpfT
SL i =
Co u t

I pfT IpfT
SL i = SL i =
Cb c Ccs Cg d Cd b

Important for output drivers and digital circuits

Degraded by interconnect parasitics

39
 Why do we need the HF FoMs?

Want to use the FOMs in circuit design

We have defined fT, fMAX, FMIN and techniques to
calculate them from the measured or simulated S
parameters and noise measurements (FMIN, Rn, Γopt
(GmIn in Spectre)
We now want to find expressions that link f T, fMAX,
FMIN to device bias current and geometry

40
 Outline

Microwave and mm-wave transistors

High-frequency figures of merit

MOSFET structure & HF equivalent ckt.

41
 Key nanoscale CMOS process features
STI to reduce active pitch
Retrograde Twin wells (latch-up, device parasitics)
M10
Triple well (deep n-well) for isolating p-well oxide
Thick gate oxide devices for IO compatibility M9

N+/P+ poly gate for symmetrical N/P-MOSFETs (HKMG in M8

<=45nm) M7

Self-aligned silicided D/S/G (low Rs, Rd, Rg) M6

low-k
Tensile/compressive stress liners for mobility imprvmnt. M5

M4
Dual Damascene Cu interconnects M3
tensile oxide spacer silicide Compressive oxide spacer silicide
stress liner contact Tungsten
contact via
stress liner contact M2
nitride spacer nitride spacer
gate gate
M1
n+ SDE SDE SDE SDE

STI
source
contact
p+

halo implants
n+
p+ drain
contact
STI
p+

STI
n+

STI
p+

STI
p+
source
contact
n+

halo implants
p+
n+ drain
contact
STI
n+

STI
oxide
p+ p-well p+ p+ p+ p+
p+ n-well p+ p+

Channel stop
Deep n-well
Back end
p- substrate Front end p- substrate

42
MOSFET structure and large signal circuit
B S G D B

gate

p+ RS Rd p+

Dsb Ddb
STI STI STI
STI
RCO Rdsb

Rsb Rdb
well
D
Intrinsic
device Rd

Intrinsic transistor Rg
Rsub B
Two pn junctions G

Parasitic resistances
Rs

43
 Typical MOSFET layout for high-
frequency apps.
DRAIN CONTACT

SOURCE STRIPE
DRAIN STRIPE
Dummy gate

GATE
SOURCE CONTACT CONTACT

10 gate fingers
44
 Complete CS mall signal equivalent circuit

Rg Cg d Rd
G D
Cgs vgs
ro Cds Cdb
-j ωτ
Ri gme vgs

Rdsub
Csb
Rs
Rssub
S B

45
 Geometry dependence of equiv. ckt. params

g m =g ' m W ; g d s=g ' d s W ; Cg s=C' g s W ; Cg d=C' g d W ; Cd s=C' d s W

R 'i R 'g d R' s R' d

Ri = ; Rg d= ; Rs = ; Rd = ;
W W W W

WF is the unit gate finger width.

W = NfxWf is the total gate finger width.

g'm, g'ds, C'gs, C'gd, C'ds, R'i, R'gd, R'd, R's are process-dependent

params

46
 MOSFET Capacitances
B S Cdsf B
D

Cf Cf
gate

Cov Cov
CJSW CJSW
p+ p+
CJSWG CJSWG
CJ CJ
STI STI Cdsb STI STI

Cgbo

Wext
CJSW L CJSW

CJSW Cgate
CJSW

B CJ S Cgso Cgdo D B
CJ
Wf

CJSW CJSW
Wext

Cgcon

47
MOSFET substrate resistance network is
layout dependent
B S D B

RCON RCON
gate

p+ p+

STI STI STI STI

RCO RSBwell R RDBwell RCO
DSwell

Can be calculated based on RSTI well

RSTI

layout geometry and RCO

B
doping/sheet resistance data
RSTI RSTI
L

RSTI RDBwell RSTI

RSBwell

Wf
RCO RCO
S G D

RSTI RSTI

RCO
B B

48
 MOSFET source/drain resistance

Not layout dependent

Depends on gate width W
Rs/W remains practically Rsp
Rac
Rsco
Rext
constant at 200-300Ω× µm
across nanoscale nodes STI STI

Rac = accumulation region resistance

Rsp = spreading resistance
Rext = resistance of the SDE region
Rsco = contact resistance

49
 Gate Resistance: Layout dependent: W f
Nf Nf = 3
XGW XGW DRAIN
GATE iSD GATE
Wf Wf REXT REXT
Wf Rgi Rgi Rgi Rgi Rgi Rgi
S D S D L
XGW XGW iG iSD iG
XGW RCON RCON
RCON, NCON SOURCE
NCON = 1 Wf
DRAIN
GATE iSD GATE
REXT Rgi Rgi R Rgi Rgi Rgi
gi REXT Rgi Rgi Rgi Rgi Rgi Rgi REXT
L
iG RCON Cgi Cgi Cgi Cgi Cgi Cgi Cgi RCON
iSD
RCON Rchi Rchi Rchi Rchi Rchi Rchi
SOURCE CHANNEL
Wf

GATE

RCON
REXT Rgi Rgi Rgi Rgi

Cgi Cgi Cgi Cgi Cgi Cgi Cgi

Rchi Rchi Rchi Rchi Rchi Rchi
Rgi Rgi REXT

Rg =
[ RCON RSHG
NCON

L
XGW
Wf
6  ]
CHANNEL
2 Nf

Rg =
[ RCON RSHG
NCON

L
XGW
Wf
3  ]
Nf
50
 Numerical Example
● 10µmx90nm device contacted on one side:
●RSHG = 10 Ohm, L=65nm, NCON=1, RCON=20 Ω, Wext
=150 nm;
● a) Wf=1µm; Nf = 10,

Rg =
[ 20

10
1 0.065
0.15 
1
3 ] =
2 074.3
=9.4 O h m
10 10
● b) Wf=2µm; Nf = 5,

Rg =
[ 20

10
1 0.065
0.15 
2
3 ] =
2 0126.15
=29.23 O h m
5 5
● Rs=Rd = (1/W)× 200 Ohm× µm = 20 Ohm in both cases.

51
 Numerical Example (ii)
● 10µmx90nm device contacted on both sides:
●RSHG = 10 Ohm, L=65nm, NCON=1, RCON=20Ω, Wext =150
nm;
● a) Wf=1µm; Nf = 10,

Rg =
[ 20

10
1 0.065 
0.15
1
6 ] =
2 048.71
=3.43 O h m
20 20
● b) Wf=2µm; Nf = 5,
●
Rg =
[ 20

10
1 0.065 
0.15
2
6 ] =
2 074.32
=9.4 O h m
10 10
● Rs=Rd =(1/W)× 200 Ohm× µm = 20 Ohm in both cases remain
large while Rg can be minimized.
●

52
 JpfT invariant to VT

130/90/65-nm MOSFETs fT, fMAX current density invariant over

devices with
low,
standard,
high VT, and
different nodes

Constant-current-density bias => designs more robust to VT

variation
53
 GP vs. LP 65nm CMOS
GP 30% faster than LP
and 300mV lower VGS =>
lower power!
VT variation is large but
mostly irrelevant
Constant-current-density
bias at 0.2-0.5mA/µm =>
robust to IDS, VT variation

Need VDS> 0.6 V

54
MOSFET fM AX as a function of layout

fT
f MAX =
2  Ri Rs Rg g d s2  f T Cg d 

fT
f MAX ≈

 
2
' ' RSHG W f
2 Ri Rs  g 'd s2  f T C'g d 
1 23 l G

55
Impact of using minimum width devices on
fM A X and (likely) on NFM IN
In the 90-nm node fMAX

degrades by 25% as the unit

finger width is reduced from 1
µm to 0.5 µm.
Even though gate resistance
improves, the degradation in fT

leads to fMAX degradation.

56
MOSFET Impedance Noise Parameters

1Ri Cg s 2 f2
Ru =Rs Rg k 2 Gn =k 1 g m 2
gm fT
k3
Z cor =Rs Rg k 3 Ri 
j  Cg s

f
Fm i n ≈1 2 k 1  g m Rs Rg k 2 1 2 R2i C2g s 
fT

PR 1−C2  P−C  PR
k 1 =PR−2C  PR ; k 2 = ; k 3=
k1 k1

57
 MOSFET noise parameters finger width and
bias dependence


' 2
f g R W
FMIN≈12 k 1 g 'm R's  m SHG f k 2 1 2 R2i C2g s 
fT 1 23 l G
f f
FMIN≈12 Const ≈1 2 Const
g '
m  V GS−V T
FMIN is a (strong) function of Wf and
lG

FMIN decreases as a function of

VGS until gm (fT) reaches its peak.

58
 Scaling of MOSFET HF Performance
C'gs,C'gd, C'db and ZSOPT approx. constant over nodes

g'm, g'o, fT, fMAX increase

FMIN , Rn decrease

RF & high-speed performance (except output swing) improves

with scaling
Leakage is not a problem at mm-waves and high-speed

Scaling is good for high-speed digital/wireline and mm-

waves

59
Making Nano-CMOS Designs PVT Independent
CMOS characteristic densities are largely invariant across nodes and
foundries

Constant-current-density biasing in analog/RF/mm-wave CMOS

minimizes impact of L, IDS, T, and VT variation

Characteristic current densities are invariant over topologies (CS, CG,

cascode, CMOS inverter, TIA)

In circuit design, one must fix Wf, L and scale only Nf

Implications for circuit design
CMOS CML gates, LNAs, TIAs, VCOs, Mixers, PAs, Opamps and
filters can be designed algorithmically and ported across nodes and
foundries
60
 Outline

Microwave and mm-wave transistors

High-frequency parameter definition
MOSFET structure & HF equivalent ckt.
SiGe HBT structure & HF equivalent ckt.

61
 SiGe BiCMOS Technology Cross-section

silicide silicide
silicide
contact contact
contact
emitter
gate gate
n+ SiGe base
n+ p+ p+

n-epi

n-epi
n+ p+ p+ p+ n+ p+ n+ n+ n+ STI n+ p+
STI STI halo implants STI STI STI STI halo implants STI STI
STI SIC Sinker STI
p-well n-well p+ (n-plug)
n-well n-well

DTI
DTI
Buried layer n+

Deep n-well p- substrate

p- substrate
p+ p+

62
 SiGe HBT Cross-section

nitride D spacer
Deep trench isolation
oxide
p+ external base poly between devices.
mono/poly
emitter Reduces Ccs
SiGe base
n+ p+
SIC collector
n-epi

n-epi

STI SIC STI

Sinker STI
(n-plug) Graded Ge base
p-well

DTI
L/D-shaped spacer
DTI

Buried layer n+
p- substrate
between emitter and
p- substrate
external base contact
Mono+poly emitter (low
RE)

63
 SiGe HBT HF Equivalent Circuit
Cbcxt rC

rbxt rbi Cbci Rbl Rsnk

C
B
Cbox Cbe rπ ro Ccs
gm e -jωτn

Rsub
S
rE

64
Geometry Dependence of Small Signal Params
IC JC IC JC REsq
IC =JC⋅wE⋅lE ; gm= = ⋅w E⋅lE ; go = = ⋅w E⋅lE ; RE= ;
VT V T VA V A lE w E
RSBX⋅wSP Rsbio wE
Rbx = ; Rbi= for double-base
2wE lE  12 lE

RSBX⋅w SP Rsbio wE
Rbx = ; Rbi= for single-base
wElE 3 lE

Cbe=Cbe ,diff C je =F gmCJE⋅w E⋅lE ; Cbep=CJEP⋅2⋅lE w E 

Cbci=C jCi⋅A BCi=C jCi⋅lE⋅wE 2bsic 

Cb c x =C jCX ×A BCext≈C JCX×2 ×w BCsp×w El E2 w BCsp 

65
 fT dependence on emitter length
To first order, fT is independent of emitter length

because length dependence cancels out in CR

As a second order effect, fT depends slightly on lE due

to peripheral BE capacitance and Rc.

66
Typical HBT fT-IC plots for devices with
different emitter lengths

67
 SiGe HBT fM A X layout dependence

f MAX =
 fT
8 Rb Cc b

1
Rb ∝ Cbc ∝l E
lE

RC, Rsub, Ccs affect (degrade) fMAX

fM AX is a (strong) function of wE.

fMAX is a weak function of lE.
68
 HBT noise parameters lE dependence

n2 VT 1
Rn = RERb  scales as n≈1 ideality factor
2 IC lE

Ysopt≈
f
f T Rn [ IC
2V T  f 2T
RERb  1 2 
f 
n 2 f 2T
4 f2
−j
n
2 ] scales as l E

  
2 2 2
n f IC fT n fT
FMIN≈1  RERb  1  2 
 fT 2V T f 4 f2

FMIN is weak function of lE but a (strong) function of wE

69
 HBT noise parameters bias dependence

n2 VT 1
Rn = RERb  scales as
2 IC IC

Ysopt≈
f
f T Rn [ IC
2V T  f 2T
RERb  1 2 
f 
n 2 f 2T
4 f 2
−j
n
2 ]
increases with I C

n f
FMIN≈1 
 fT  IC
2V T  f 2T
RERb  1  2 
f 
n 2 f 2T
4 f2

FMIN first decreases (due to drop in Rb(IC) – thermal noise is

dominant ) and then increases with IC (shot noise dominates)
70
 HBT Summary
HBT characteristic densities increase in newer nodes

In a given technology, JOPT increases with frequency

JOPT increases if a series resistance is added to emitter or base

Large fM AX can be obtained at lower JC and with higher BVCEO than fT.
Implications for circuit design
Designs must be modified in each node/foundry, although, for a given
peak fT, JC appears to be similar between foundries.

71
 Outline

Microwave and mm-wave transistors

High-frequency figures of merit
MOSFET structure & HF equivalent ckt.
SiGe HBT structure & HF equivalent ckt.
FETs vs. Bipolars

72
Noise Parameters: HBT VS. MOSFET (i)

HBT MOSFET

1 P
Rn ≈ r ERb  Rn ≈ Rs Rg 
2 gm gm

Ysopt≈
f
f T Rn [ gm
2
r ERb −j
n
2 ] Ysopt≈
f
f T Rn
[  Pg m Rs Rg −j P ]

1 f gm
FMIN≈1  r R 
 fT 2 E b  FMIN≈1
f
fT
 Pg m Rs Rg 

73
Noise Parameters: HBT VS. MOSFET (ii)

At equal bias current and comparable fT, the MOSFET has

lower gm and hence:

lower FMIN
lower Rn (higher sensitivity to Zsopt mismatch)

higher Rsopt (larger current for 50- noise matching)

In MOSFETs, the peak fMAX and the optimum noise bias

current density coincide. In HBTs the optimum noise current
density increases with frequency but is significantly smaller
than peak fT current density.
74
 Low-noise transistor design

Two steps:

Bias transistor at optimal noise current density

Size transistor (while keeping the optimal noise current

density) to make the real part of the optimum noise
impedance (Rsopt) equal to the desired value.

Sizing is achieved by increasing Wf (lE) or connecting gate

fingers (emitter stripes) in parallel.

75
 CMOS Technology over Nodes

Param/node 250nm 180nm 130nm:GP/LP 90nm:GP/LP 65nmGP/LP 45nm

L (nm) 250 180 120/120 65/80 45/57 39/35

EOT (nm) 5 3.5 2.1/2.3 1.6/2.1 1.3/1.8 1.1/1.3

VDD (V) 2.5 1.8 1.2/1.2 1.0/1.2 1.0/1.2 0.9/1

g'm (mS/µm) 0.35 0.55 0.8/0.7 1.2/1 1.6/1.2 1.8?

g'o (mS/µm) 0.03 0.05 0.08 0.13 0.18 0.17?

C'gs (fF/µm) 1.4 1.4 1 1 0.7 0.6

C'gd (fF/µm) 0.45 0.45 0.45 0.35 0.35 0.34?

C'db (fF/µm) 1.5 1.5 1.5 1.1 0.8 0.6?

R's/R'd (Ω*µm) 100 120 150 200 200 200

n-MOS fT (GHz) 40 60 80/80 140/120 190/160 250?

76
 Parasitic source and gate resistance
scaling
Parameter 65nm GP 65nm LP (GP) 45nm

Physical L (nm) 45 57 (45) 35

EOT (nm) 1.3 1.8 (1.3) 1.3 (1 for HKMG)

Wf (µm) 1 1 0.7

NCON 1 1 1

Contact on both sides No No No

RCON (Ω) 40 40 60

RSHG (Ω/sq) 15 15 20

Wext (nm) 120 120 100

Nf 1 1 1

RG (Ω) 191 159 (190) 250.5

77