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State Machine Programming

Sensor:
Output is 1 if water level is over
Output is 0 if water level is under

Sensor 1 = 0

STOP PUMP PUMP

____________ ___________
PumpCtrl = 0 PumpCtrl = 1

Sensor 2 = 1

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State.h
typedef enum {S_STOPPUMP,S_PUMP} state_t;
typedef enum {WATERUNDER, WATEROVER} sensor_t;
void initState(void);
void statemMachineUpdate(void);
void SensorsInit(void);
sensor_t sensor1(void);
sensor_t sensor2(void);
void pumpCtrlInit(void);
void pumpCtrl(int state);

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State.c
#include "state.h"

static state_t State;

void initState()

State = S_STOPPUMP;

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State.c
void stateMachineUpdate(void)

{ switch (State)
switch (State) {
{ case S_STOPPUMP:
case S_STOPPUMP: pumpCtrl(PUMPOFF);
if (sensor1() == WATERUNDER)
break;
State = S_PUMP;
case S_PUMP:
break;
pumpCtrl(PUMPON);
case S_PUMP:
break;
if (sensor2() == WATEROVER)
}}
State = S_STOPPUMP;

break; }

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main.c
#include "state.h"

int main(void)

{ sensorsInit();

pumpCtrlInit();

pumpCtrl(PUMPOFF);

initState();

while (1)
{
stateMachineUpdate();
}}

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State machine Drawing

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State machine drawing

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Exercise

 Design state machine and write code for

TIVA lauchpad:
 After reset, all LEDs are off
 If SW1 is pressed, turn on LED Red.
 Led Red still on if SW1 is released. LED Red is off if SW1 is
pressed again, and still off if SW1 is released.
 This sequence repeats forever.

 Note: Open the example7_StateMachine project and modify the

source code (marked as TODO)

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Software Timer
 Systick interrupt can be used to implement a software timer
 The timer resolution is the systick timer period. We often choose
1ms.
void SysTickIntHandler(void)

if (genTimerCount != 0)
{ genTimerCount--;
}}

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Software Timer
void genStateMachineUpdate(void) case S_GRIDOFF_WAIT:

{ switch (genState) if (gridState() == GRIDON)

{ {

case S_GRIDON: genState = S_GRIDON;}

if (gridState() == GRIDOFF) else if(genTimerCount == 0)

{ {

genState= S_GRIDOFF_WAIT; genState = S_GRIDOFF;

genTimerCount = 20; } }

break; break;

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 Design state machine and write code for
TIVA launchpad:
 After reset, all LEDs are off
 If SW2 is pressed in 3 second, turn on LED Green. LED Green
still on if SW2 is released. LED Green is off is SW2 is pressed
again in 6 second, and still off if SW2 is released after that. This
sequence repeats forever.

 Note: Open the example8_MultiStateMachine project and

modify the source code (marked as TODO)

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Multi Tasking

 To have more than one task to work

concurrently, we just need to call them in
a super loop
while (1)
{

StatemMachine1Update();

StateMachine2Update();

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Exercise

 Design state machine and write code for

TIVA lauchpad:
 After reset, all LEDs are off
 If SW1 is pressed, turn on LED Red. Led Red still on if SW1 is
released. LED Red is off if SW1 is pressed again, and still off if
SW1 is released. This sequence repeats forever.
 If SW2 is pressed in 3 second, turn on LED Green. LED Green
still on if SW2 is released. LED Green is off is SW2 is pressed
again in 6 second, and still off if SW2 is released after that. This
sequence repeats forever.
 Note: Open the example8_MultiStateMachine project and
modify the source code.

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Shared variable (biến dùng chung)

Hoạt động của một hệ thống có thể được

chia thành nhiều tác vụ độc lập mặc dù
chúng có liên quan tới nhau.

VD:
Một hệ thống phát hiện chuyển động sử dụng 1 sensor kết nối vào
chân P1.0. Một chuyển động được phát hiện khi sensor bằng 1 trong
2 lần lâý mẫu liên tiếp cách nhau 200ms.
LED1 (nôí vào P1.1) được nhấp nháy sau với chu kỳ 200ms trong
thời gian phát hiện chuyển động.
LED2 (nôí vào P1.2) được bật khi phát hiện chuyển động và tắt 10s
sau khi chuyển động không còn bị phát hiện.

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Shared variable (biến dùng chung)
!P1.0 !P1.0 P1.0

P1.0 P1.0
S0 S1 S2

mnt
mnt = 0 mnt = 1
!P1.0

!mnt mnt !mnt && (cnt < 50)

mnt !mnt
T0 T1 T2
cnt = 0
cnt++

!mnt && !(cnt < 50)

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I/O and software synchronization

 Hardware has 3 basic state: idle, busy and

done

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I/O and software synchronization

If the input device were faster than the software, a situation called CPU
bound, then the software waiting time would be zero

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I/O and software synchronization

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Interrupt
 An interrupt is the automatic transfer of software
execution in response to a hardware event that is
asynchronous with the current software execution
 When the hardware needs service, it will request an
interrupt by setting its trigger flag
 A thread is defined as the path of action of software
as it executes
 The execution of the interrupt service routine is called
a background thread

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Interrupt synchronization
 ISR should execute as fast as possible
 Placing backward branches (busy-wait loops,
iterations) in the interrupt software should be avoided
if possible
 Busy-wait synchronization is appropriate when the I/O
timing is predicable, and when the I/O structure is
simple and fixed
 Interrupt synchronization is appropriate when the I/O
timing is variable, and when the I/O structure is
complex

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Interrupt synchronization using semaphore

No wait on the ISR

A semaphore can be
used to synchronize
threads

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Interrupt synchronization using mail box

Mailbox là phương pháp sử dụng 1

semaphore cùng với 1 biến để lưu giữ giá
trị cần thông tin

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Interrupt synchronization using FIFO

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Interrupt synchronization using FIFO

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Sharing Data Safely between ISRs and other Threads

 Volatile data – can be updated outside of

the program’s immediate control

 Non-atomic shared data – can be

interrupted partway through read or
write, is vulnerable to race conditions.

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Volatile Data
 Compilers assume that variables in memory do not change
spontaneously, and optimize based on that belief
 Don’t reload a variable from memory if current function hasn’t changed it
 Read variable from memory into register (faster access)
 Write back to memory at end of the procedure, or before a procedure call, or
when compiler runs out of free registers
 This optimization can fail
 Example: reading from input port, polling for key press
 while (SW_0) ; will read from SW_0 once and reuse that
value
 Will generate an infinite loop triggered by SW_0 being true
 Variables for which it fails
 Memory-mapped peripheral register – register changes on its own
 Global variables modified by an ISR – ISR changes the variable
 Global variables in a multithreaded application – another thread or ISR
changes the variable

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The Volatile Directive
 Need to tell compiler which variables may change outside of its
control
 Use volatile keyword to force compiler to reload these vars from
memory for each use
volatile unsigned int num_ints;
 Pointer to a volatile int
volatile int * var; // or
int volatile * var;

 Now each C source read of a variable (e.g. status register) will result
in an assembly language LDR instruction

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Non-Atomic Shared Data
 Want to keep track of
current time and date
 Use 1 Hz interrupt from
timer
 System
 TimerVal structure tracks
time and days since some
reference event
 TimerVal’s fields are
updated by periodic 1 Hz
timer ISR
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void GetDateTime(DateTimeType * DT){
DT->day = TimerVal.day;
DT->hour = TimerVal.hour;
DT->minute = TimerVal.minute;
DT->second = TimerVal.second;
}
void DateTimeISR(void){
TimerVal.second++;
if (TimerVal.second > 59){
TimerVal.second = 0;
TimerVal.minute++;
if (TimerVal.minute > 59) {
TimerVal.minute = 0;
TimerVal.hour++;
if (TimerVal.hour > 23) {
TimerVal.hour = 0;
TimerVal.day++;
… etc.
}
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Non-Atomic Shared Data
 Problem
 An interrupt at the wrong time will lead to half-updated data in DT
 Failure Case
 TimerVal is {10, 23, 59, 59} (10th day, 23:59:59)
 Task code calls GetDateTime(), which starts copying the TimerVal fields to
DT: day = 10, hour = 23
 A timer interrupt occurs, which updates TimerVal to {11, 0, 0, 0}
 GetDateTime() resumes executing, copying the remaining TimerVal fields to
DT: minute = 0, second = 0
 DT now has a time stamp of {10, 23, 0, 0}.
 The system thinks time just jumped backwards one hour!
 Fundamental problem – “race condition”
 Preemption enables ISR to interrupt other code and possibly overwrite data
 Must ensure atomic (indivisible) access to the object
 Native atomic object size depends on processor’s instruction set and word size.
 Is 32 bits for ARM
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 Non-Atomic Shared Data
 Must protect any data object which both
 (1) requires multiple instructions to read or write (non-atomic access),
and
 (2) is potentially written by an ISR

 How many tasks/ISRs can write to the data object?

 One? Then we have one-way communication
 Must ensure the data isn’t overwritten partway through being read

 Writer and reader don’t interrupt each other

 More than one?
 Must ensure the data isn’t overwritten partway through being read

 Writer and reader don’t interrupt each other

 Must ensure the data isn’t overwritten partway through being written
 Writers don’t interrupt each other

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Definitions
 Race condition: Anomalous behavior due to unexpected
critical dependence on the relative timing of events.
Result of example code depends on the relative timing of
the read and write operations.

 Critical section: A section of code which creates a

possible race condition. The code section can only be
executed by one process at a time. Some synchronization
mechanism is required at the entry and exit of the critical
section to ensure exclusive use. (Exclusive Accesses
needed)

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Solution: Briefly Disable Preemption
 Prevent preemption within
void GetDateTime(DateTimeType *
critical section
DT){
 If an ISR can write to the
uint32_t m;
shared data object, need to
disable interrupts
 Restore previous state
IntMasterDisable();
afterwards
DT->day = TimerVal.day;
DT->hour = TimerVal.hour;
 Avoid if possible
 Disabling interrupts delays response to all DT->minute = TimerVal.minute;
other processing requests DT->second = TimerVal.second;
 Make this time as short as possible (e.g. a
few instructions) IntMasterEnable();
}

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Solution: Briefly Disable Preemption
 Can use CMIS core
 If an ISR can write to the
shared data object, need to
disable interrupts
 save current interrupt
masking state in m
 disable interrupts
 Restore previous state
afterwards (interrupts
may have already been
disabled for another reason)
 Use CMSIS-CORE to save,
control and restore interrupt
masking state
BM Kỹ Thuật Điện Tử - ĐH Bách Khoa TP.HCM
void GetDateTime(DateTimeType *
DT){
uint32_t m;
m = __get_PRIMASK();
__disable_irq();
DT->day = TimerVal.day;
DT->hour = TimerVal.hour;
DT->minute = TimerVal.minute;
DT->second = TimerVal.second;
__set_PRIMASK(m);
}
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Summary for Sharing Data
 In thread/ISR diagram, identify shared data
 Determine which shared data is too large to be handled atomically by
default
 This needs to be protected from preemption (e.g. disable interrupt(s), use an
RTOS synchronization mechanism)
 Declare (and initialize) shared variables as volatile in main file (or
globals.c)
 volatile int my_shared_var=0;
 Update extern.h to make these variables available to functions in other
files
 volatile extern int my_shared_var;
 #include “extern.h” in every file which uses these shared variables
 When using long (non-atomic) shared data, save, disable and restore
interrupt masking status
 CMSIS-CORE interface: __disable_irq(), __get_PRIMASK(),
__set_PRIMASK()
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CMSIS
 TIVA C families are based on ARM Cortex-M4
Core. There are also many other vendors who
use CM4 in their products.
 A standard hardware abstraction layer is
therefore needed.
 Cortex Microcontroller Software Interface
Standard(CMSIS) is a vendor-independent
HAL for Cortex-M processor series.

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