Hi,

First I will ans why hold violation come into picture?

Look into basic definition of hold time and it's minimum amount
of time data should be stable after the clock edge.

It's just an English statement but let's try to understand what is

logic behind that when u launch a data and once it reaches FF
how does a FF will know that it's 1 or 0 (Plz refer internal structure
of Dff for ref. Using 2*1 mux),so if u refer to FF structure of A FF
using Mux u can see it's 2 mux connected I m not going in depth
of structure now as a VLSI engineer u know very well that Any ckt
is fundamentally made with help of Transistors only . So when u
give any I/p to FF then I/p pin capacitance starts charging in a
Linear manner( U are giving rectangular signal to A capacitance
then o/p waveform will be ramp signal or triangular),

And once it get charged fully then u can say it's holding 1 and if it
has charger below Vil then it's 0 but what if it is in b/w Max
threshold and min threshold then it's called Metastability and u
loose your data bcoz u don't know if it is 1 or 0, that min amount
of time req to charge ur cap ( i/p cap of CMOS used to finally
build ur FF) fully is nothing but Hold time.

So conclusion is that Hold check ensure

SDF stands for Standard delay format.

It gives information on the timing data extensively used in

backend VLSI design flows.

SDF gives information about

1. Path delays
2. Interconnect delays
3. Timing constraints
4. Tech parameters affecting delays
5. Cell delays.
6. SDF file is also used in the back annotation of delays in
the gate level simulations for mimicking the exact Si
behavior.

What is Standard Delay Format (SDF)?

SDF stands for the “Standard Delay Format”.

It stores the timing data generated by EDA tools for use at any
stage in the design process. It can be used anywhere in the flow as
to import or export the timing information about design.

The data in the SDF file is represented in tool independent way

and can include:

1. Delays: Module path delay, device delay, interconnects delay

and port delay.
2. Timing checks: Setup, hold, recovery, removal, skew, width,
period and no change.
3. Timing constraints: Path, skew, period, sum and diff.
4. Timing environment: Intended operating timing
environment.
5. Incremental and absolute delays.
6. Conditional and unconditional module path delays and
timing checks.
7. Design/Instance specific or type/library specific data.
8. Scaling, environmental and technology parameters like,
Process variations, temperature, voltage and wire load models.

Throughout the design process, you can use several different sdf
files. Some of these files can contain pre layout timing data.
Others can contain path constraint or post layout timing data.

The name of each sdf file is generated (determined) by EDA tool.

There are no conventions for naming SDF files.

Meta stable state:

Meta stable state refers to the state in which a digital block/circuit stays
in an unstable equilibrium state. That is , the circuit will not be able to
settle to a stable 0/1 rather will be between 0/1.
Whenever there are setup and hold time violations in any flip-flop, it
enters a state where its output is unpredictable: this state is known as
metastable state (quasi stable state); at the end of metastable state, the
flip-flop settles down to either '1' or '0'. This whole process is known as
metastability.
 Definition of false path:

A timing path, which can get captured even after a very large interval of
time has passes, and still, can produce the required output is termed as
a false path. A false path, thus, does not need to get timed and can be
ignored while doing timing analysis.

False paths for static signals arising due to merging of modes:

Suppose you have a structure as shown in figure 1 below. You have two
modes, and the path to multiplexer output is different depending upon
the mode. However, in order to cover timing for both the modes, you
have to keep the “Mode select bit” unconstrained. This result in paths
being formed through multiplexer select also. You can specify "set false
path" through select of multiplexer as this will be static in both the
modes, if there are no special timing requirements related to mode
transition on this signal. Specifically speaking, for the scenario shown in
figure 1,
          Mode 1 : set_case_analysis 0 MUX/SEL
          Mode 2 : set_case_analysis 1 MUX/SEL
          Mode with Mode1 and Mode2 merged together : set_false_path
-through MUX/SEL
 Figure 2: Mode selection signal selecting between mode1 and mode2
paths
Architectural false paths: There are some timing paths that are never
possible to occur. Let us illustrate with the help of a hypothetical, but
very simplistic example that will help understand the scenario. Suppose
we have a scenario in which the select signals of two 2:1 multiplexers
are tied to same signal. Thus, there cannot be a scenario where data
through in0 pin of MUX0 can traverse through in1 pin of MUX1.
Hence, it is a false path by design architecture. Figure 3 below depicts
the scenario.

Figure 3: A hypothetical example showing architectural false path

Specifying false path: The SDC command to specify a timing path as false
path is "set_false_path". We can apply false path in following cases:
      From register to register paths
o set_false_path -from regA -to regB
o
      Paths being launched from one clock and being captured at
another
 o set_false_path -from [get_clocks clk1] -to [get_clocks
clk2]
o
      Through a signal
o set_false_path -through [get_pins AND1/B]

multicycle path:
By definition, a multi-cycle path is one in which data launched
from one flop is allowed (through architecture definition) to take
more than one clock cycle to reach to the destination flop.