SEGA SERVICE MANUAL GENESIS MEGA DRIVE PAL MEGA CD/SEGA CD NO. 010 ISSUED APRIL, 1994 CONTENTS GENESIS VA7 PARTS SPECIFICATIONS MEGA DRIVE PAL VA6.5 PARTS SPECIFICATIONS «++ +00000ceeeseeeeeeeeeeeeenees an MEGA CD / SEGA CD PARTS SPECIFICATIONS This manual contains IC specification to be added to the manuals issued previously. Sega Enterprises, Ltd.PARTS SPECIFICATIONS IC1 16/32-bit Microprocessor IC MCB8HCOOOFNB Ic HDB8HCO0oCPB I Top View & Pin Layout Signal Desoription SEEvsssasasass85 woot pores bus oe > Tawa] anes mate or | 15.00 me a a ss co wi ° ai processor [rcv TEE | asrncwnonous = leer ee ea ER avco0o |, BTS EE i. eesoon we 4 E mi 4 esse (aa aus a. A pent [oa | | i re PESowTmOL (TBR sone _f Coniner ATTN T fa Beggs seeseeesee svsreu ToCr__ | wreanuer conrnet Sonnac Description No.|Pin Name|VO] Function [NoJPinName]VO] Function NoJPin Name] vO] Function TD, Z| VPA_| 1 | Vall pepeatadins | [45] Are 2. 24) BERR | 1 [Bos enor a] Ay SD |10| ata bus 25] Ty a3] Ap 2D 26 | TPL, _| | | Interrupt contro! 9] Aig | © |Adéress bus stp 7 SA | AS | 0 [Adress arabe 25] Foy Sif 7 [Ups [0 [Upper dara sabe] [29 FC] 0 |Processorstaes | [52] Vee | [Power sappy ECDs 10 [Lower eat arabe —] [30] Fy 33] An. 9 | RAY | O [Read/Write Sif NC = 34] A; O | Address bus TACK | 1 [Dats taster mA 35 [Aas 10 | DTACK | | | Acknowledge 33, Ay 361 V1 |onp TBC [0 [Bus grant 34 st] Ve IZ] BGACE | 1 [Bus grantadinowiedge | [35] Ay 331 Dis 13 BR [1 [Bus request 36[ Ag 30 De Ta] Veg = [Power supply ST At @| Ds 15] CLR [Chosk 3B. si] Dy 16 Vas] 3o[ Ag | O | Aeros bos [Dy 17|-V, oxo ao] Ae 63 Diy |1/0|Data bus Te] NC — [Nev connased ai] Ap ist] Ds 19 HALT _1V/O/ Fal a2] Ay | Ds. 20| RES | W/O [Reser 43] Ay 6 D, Dr YMA 0 | Vaid mena aren —| [a4] aye ca Zp E10 [enable Au Ds1C2/3_ 32768 Word x Bbit CMOS Pseudo-Static RAM ICHMBS258BLFP-10 IC TC51892FL-10 Ii Top View & Pin Layout mPinname [-eename TFunaton TADWAld | Adres inp RAW __| Readrieinput Output enable OERESH ‘input/refresh input TE__| Chip enable input 101-108 | Da inpuvourpt Voo___| Powersupply GND | Ground Block Diagram TY covumy DECODER ‘SENSE AMP. be Ana! WOGATE |) | 28 4 vo1-V08 aoe [TTT gs OW ADDRESS = ae BUFFER (8) = Meurer | MEMORY ARRAY = 7 250120 x8 COUNTER = ical 100K. nernesn |—-[~RERRESH CEO“) GENERATOR [CONTROLLER |-—j__ TIMER oTIC4 Z80A Central Processing Unit Ic 2808 315-0041 I Top View & Pin Layout An |o Ato AB] Ae AB] Ms Description Pin [Pin Name] wo | Function 30-20] 125 AD-AIS: 3.STATEO | System address bus, 15-12 10 DoD? 3STATE IO) System data bus, 6 [oreed Receives a +5V single-phase clock signal. Int “Fative "Low" I the inpavouipat device Tssues a signal that requests an interrupt to the Z80 CPU and the imerrupt enable flag is zero, this interrupt request is accepted at the end of the instruction that is currently in progress. "7 ‘Active "Low". This is an interrupt request that has priority over INT and cannot be inhibited by the software. NMI is always accepted, and when the insruc- tion that is currently in progress finishes, interrupt processing is started and the Z80 CPU automatically san from address OO66H. 8 ‘Active “Low”, This indicates that the HALT instruction is being executed. Executes the NOP instruction inter- nally and also refreshes memory. The halt state is released by RESET. NMI or INT (when enabled), 19 MRED ‘Active “Low”. This indicates thatthe address bus ourpute the effective memory address for memory read/write. ‘Tetive "Low". This indicates thatthe Tow-order 8 bit oF] the address bus output effective addresses of the puvoutput device for the read/write operation with this device. This is ouput together with MI during an interrupt response to indicate the response. 2 3STATEO ‘Active “Low”. This indicates the timing with which data from the memory or inpu/output device is read 3STATEO ‘ative "Low", This indicates that the effective data wo be ‘written to the memory or input/output device the address of which is specified is onthe data bus ‘When the bus request is acknowledged, this informs the ‘bus master which ourputs the bus request thatthe system bus can be controlled. ‘Active "Low". Signal to inform the CPU that the memory of inpuvoutput device the address of which is specified is not ready to send data. The CPU is waiting when this signal is input. i ‘Active “Low”. This has priory over NMI and is accepted atthe end of the machine cycle that is currently in progress. Ths is se to “Low” when a bus master other| than the CPU wants to control the system bus. i gy ‘Active “Low”. This resets the interrupt enable flag, interrupt vector register and memory refresh register of the program counter to se the interrupt mode to mode 0, initializing the 280 CPU. ‘This indicates that the machine cycle ing executed is an OP code fetch cycle. RH ‘ative "Low", This indicates that the address for} refreshing the dynamic RAM is output tothe low-order 7 bits of the address bus. MREQ also goes “Low” at this time.IC5 65536 bit Static CMOS RAM Ic UPDss646-15L Ic MaB4644.80 IC MBB4B4A-10LL Hi Top view & Pin Layout Block Diagram [| esase er Inooness| | now | | (se x20 urren | foccooen) | wewoRy cel. ARRAY I I ADDRESS INPUT 10, wer [fansesuron| Tourn] | OUTPUTENABLEINPUT zarun —|Joowrnon DATA INOUTPUT & [eonTROL | pecoDER. L '+5V POWER SUPPLY | Cp ENABLE 1. 21NPUT a | ‘onouno BUFFER WRITE ENABLE INPUT TIT TT No CONNECTION B04 ALA As Ase = —+p— T a —_56—____ 1 Operation Mode ce | ce, | We ‘MODE: OUTPUTSTATE | POWER SUPPLY CURRENT a x x | = Non-elect j x G x x (Power down) High impedance = a H HH ‘Ouiput disable L # L HO Red Dor Ten L H x L Write Di Ics CUSTOM IC ICCUSTOM CHIP SGEFC1004 «IC CUSTOM CHIP SGEFC1004 IC CUSTOM CHIP SGE FC1008 315-5487-R 837-5487-01R 315-5487-01R Top View & Pin Layout 208 1 Description Re] Name | vo Function Re] name | vo Function 1] _Sb0 5 | _Soe 2 [S01 6 | _sos 1 | Deal prt RAM interface signals 1. | Dual port RAM interface signals 3 ‘SD2 rat en 7 ‘SD6 ae ipa + _sp3 @| 307we] vere [0] Funaton Fe] Nene [vO Funeton TI > 59 | 2RES | WO | 280 inerface signals | | aR | Tt STS 280 inestce sige Dual por RAM intetace signals. | P=} 10 66 | TRAM Stet Sot 0 | sam imerace 7 a ‘VO | Dual port RAM interface signals. 7 a 19 | _RD2 @ | Ra 20 | _ RDS 70 | ASE 2 _vss__| = | OND | ROM | 22 | _RDS 72 | _ FOC 23 | _ RDS 73 | FOR | RDS | 74 | CeO 25 ROT] 75 | TIME 25 | ADO 76 [CART| 1 z]_ADI 7[ tas] 0 $2 | Wo | Dua pon RAM ines signal ae 2 | _ ADS 7 |_DBR [10 30 [| _ADé w [VoD | — | Powersupply 31 | ADs @1_| TESTO | WO | Textsignal. (Sexo cenainly) 32 | ADs 2 | TESTI 33 AD? 83 TEST2 1 Test signals. 34 {VIDEO AVSS| — 84 TEST3 (Chesepinsset to Soren): 35_[R(ANALOG) | POO 36 [G (ANALOG) © | VIDEO+PSG % | pcr 37_[B (ANALOG) a7] Pe 38 MIDEO AVDD — 8 | PCS | WO | Joy pad imerface. ~»| ws lo a9 | Pos | sraw [10 90 | Pes a1 |_vSynC_| 0 | Pos 42 |_CSYNC_| 10 | VIDEO-PSG 2 | _vss__| - | GND 2 |_FSYNC_ [170 93 | PBO 44) VoD | — | Powersupply. | PBI eo] wT, 95 [PB 46 | _NISC 96 | Pas a7 | _VPA 7 | Pea | FAT |o 38 | PBS wo | _ RESET (68000 interface signals. 99 | P86 50 FCO 100 PAO VO | Joy pad Interface. 51 FCL ' 101 PAL 32_| REO | 00 | 280 ierfcesienals 102|__PA2 33.|_vss__| - | OND 103, PAS sa] _auss | — oa [PAS BS] WOR 1O| wy 105 | PAS: 36] _MOL__| = 106 | PAS 37] SOUND_| = vor] FT 58 SOUND | 00 | Use this pin sett opencenain. || 108 PRESFie] Name | vo Funetion Re] Name [v0 | Function 108) a 159 | _VAB : Prof vz] Wo | Use tis pin setto open cenainly. | [60] _vaT my) 10 | 16 | VAs 12] __Za0 162] VA 113 _ZAl 168 | VAIO tia] Zaz 14 | VAN us| _Za3 165 [VAI Ti | Zag 166| _VAI3 117 | _Zas 167 VAI | 1 | ggqgo address bs rig] __Za6 168 | VAIS nig) Zaz 169 | Vale 120 ZA8 UO!) 2eoadiest ne 170 VAIT a1 | 2A9 i [ vals 122 | _Za10 12) Valo 1] Zan 173 | VA2 124] Zatz 174 | VA2I 125 | _ZAI3 vs|_vaz 126 [Zale 176 | VAz3 17 | _2als 17 [SOUND _| = 128 SRES 178 [PSG (ANALOG)| 0 _| VIDEO+PSG 129 SELI 1 179 SOUND AVSS| — 130| CLK V/O | 68000 interface signals. 180 VSS — | GND Ta | SBCR__| O | VIDEO-PSG ter | INT | © | 280 inerace signals. 132 | _ZELK | VO | 280 merle signals 12) BR [0 133 [vss | - | GND 183 | BOACK_| U0 Te] MLR | I 84 [BC | 1 | 68000 imtertce signals 1as[_EDCLK | 10 ws [TPT [0 136 [VDD __| — | Powersupsy wes | IP 1 137 | vbo 1e7|_TORO_[ 0 ae] vbr wee] RD [1 139 | _vp2 1a | wR [uo | *>merasesienae 140 | vD3 10] Mit a | vs ii | aS aa] vps 12 | UBS 143 | vps 193 [EDS | 10 | 68000 interface signals aa [vor 19 | RW as |_vos_| VO) $600 dat us 195 | _DTAR 146 | ve 196 | _UWR | 0 1a | _vbI0 197 | EWR [10 | PSRAM inert vas [vb 198 | CAS0_| 10 149 | vDI2 199 | RASO__| O | P-SRAM inerace 150 | vDI3 200] 200 isi] vbIe 201] 201 152) _vbis a2] 202 153) vss = [ GND 205 [203 | 1) | go dat tos s4 [VAI 204| _ZD4 155 | VA 205 | 205 156 | _VA3__| 1/0 | 68000 address bus [z= 206 1s7|__vaa aor] 207 ise | VAs aoe] vDD__| — | PowersuplyIC7/8 65536 Word x 4bit Dynamic RAM Io Msmaca64L-12 lo MsMacasal-15 Ic UPDa1264v.12 Io MBer461-12 Ic HMs34612P-12 IcTwssés1-1280L IC V530261Z10 Ic kMazacsaz-10 ICMSMS1C2621025 IC KM424C647-12 Outside View MEPin Layout Block Diagram ! IME On ROW ADDRESS BUFFER 0 ee ee — | eee “QT / 0 ee ag 4, tt surren |_Qwjn0,| woureer ‘1024ROW (266 x 4) 1% , nO— eax Sno, ReieTER Ser O— i ADDRESS INPUT Le ! om cope] *N i % : 258K MEMORY CELL | ? Is Ut tT | —_— 7 250 x4 | owdiitren | S10, i ery oe ; |) sera |e 50 5 ame enn pracusecron SERA | C80 Sr so, P-PORT) wesonss — we I ‘STROBE INPUT ROW ADDRESS oS ‘STROBE INPUT WRITE BAR BITTWRITE WBIWTE( [ENABLE INDL INPUT DATATANSEER) BTEC) —+ ‘OUPUT ENABLE OUTPUT SeMAL covTmoL neuT =o semmuenasiemeut FEC)— ‘clock oscitLAToR1C9/10 Quad Operational Amplifier le Lma2e Top View Pin Layout our Te frjour, sets! Legis 1 Fa, veel] Iijono +". iis, > te. our. [7} fajour, 1C11_ RGB Encoder IC CXAI145-T6 Top View 2 a = @& = = 2 <8 ob os 8 b&b & & 0) @ (33> @) ® @® @ ® ® Sooo lees ope =a HIGH & ies cae) [aw] GER a aie Ly cme | [a ai Tea tied fectiod [aaron iz i ee ee a ' EF 2 25 ® e & & iler Ic UPC7BOSHF Top View IH Block Diagram —io—PARTS SPECIFICATIONS IC1 16/32-bit Microprocessor Ic ScNes0o0ceNes Ic Mces000Ps Top View & Pin Layout Signal Description ‘Aopress aus voor rset ae DATA BUS —)ois00 = Foo a pnogesson [rer OEE | asyncynonous a | oo wo seneasco |e fica” |. DIAS PROSESGOR £ cs renpaenat (=< a [Pee | irerraarion CONTROL | WFR samme f connor corm (EY a contmot ConTmoL, Z| fee} Desoription [NoJPin Name]VO] Function | [No|PinName|VO] Function Function 1] Dy Z| BERR | 1 [Bus error 2 Bl 3 Dy |10| Dasa bus ZL TEE 1 | erat const Address bus [ato 25| PL s- 3 26[ Fo 6 |_AS | [Address strobe 27] FC, | O | Processor status Bower supply 7 | UDS | 0 | Upper data strobe Bt FC S| EDS [0 [Lower data strobe —| [291 — Ay RT| 0 | Address bus | RaW [0 [Readiwrie [A Ag DIACK | 1 [Das seater 31] A Vee [= [GND 10 | DTACK | | | Acknowledge 32| At Dis. Tr] BG [0 [Bus grant [A Dit 12] BGACK | 1 [Bus rantacirowtedee | [34] Ag 35] Dip 13 BR | 1 [Bus request 35[ Ar [s7[ Dy Ta] Vee] = [Powersupply 36] Ag | © | Address bus 38] Dy 15] CLK [1 |Closk x 59] Dig |10| Data bus 16] Vas—| = [GND 38] A GO| Dy 17 Fatt [0| Hatt 33] Ay | si] Dy 18 | RESET [VO] Reset 40) Ay 2D; 19 VMA [0 [Vaid menan adaren—| [ar] Aye 3] De Z| E [0 [Enable a2] Aue 64, Ds 21] VPA [Oi Vale penprenteatres| [43] Avewa) IC2/3_ 32768 Word x Sbit CMOS Pseudo-Static RAM ICHMesoseasP-45 IC UPDS28920-15 IC ToSt892-12 WITop View & Pin Layout IEPin Name ‘ [_Pianame | Funeion _] ia AO-Alé | Ades input A WE Write enable input te Output enable s OEIRFSH | jpuvetresh input he = i CE__| Chip enable npur Ae WO1-108__| Data inputfourpat Hy: Voc Power supply: el jrour a GND__| Ground 03 vos enh Block Diagram ‘CENRFER) i , REFRESH REFERENCE INNER REFRESH ADDRESS voutace | osciator | 4 | clock COUNTER GENERATOR: [CONTROLLER (GENERATOR | —= 10 BUFFER |—O 110, A 1024 SENS AMP | =o eurFeR|—o to, , Sh Row. 2 [ADDRESS SS S$ burren so io surFeR|—owo, ao MEMORY ARRAY ie surrer|—owo, Row. pecooEH WO BUFFER |—O WO, bo yee SS $1 coumn + $—\pooress| ro surren|ovo, Sf ourrer wo Bus iv Ao = (COLUMN DECODER VO BUFFER YO; No surrer|—owo, -12-Ica IC CUSTOM CHIP UPDS2271 Parts No. : 315-5433 Top View 120 a2 a Pin Name No Pin Name No. Pin Name No. Pin Name No. Pin Name T VDD a GND a VDD 121 ‘GND z MCLE az GND 2 ‘A07 1 ‘GND 3 CART 3 ZAG 33 08 123 CLK 4 ZRMM a ZAS Ba ‘A08 124 M3 3 XREF 5 ZAZ 85 ‘AI 125; XAS. 6 XML a ZAL 86 AIL 126) LDS, 7 ZRSS a ZA0 7 lz 127 UDs: 6 XZBR 8 OAs 88 AI 128) RWO- 3 ‘WAI a OA6 39 Ala 129) DIK 10 ZBAK 30, ‘QAO 0 AIS 130 BG i Zww 31 OAL 3 Ale 131 BGA 12 ZRR 32 ‘OA2 7 AIT 132 BR 3 TREO. 33 OAS 3 Als 133 HALT, 14 MRO 34 ‘OAS 38 Aig 134 VRES 15 XNMI 35 Ba 95 | _Am 135 XVPA 16 21 36 od 96 ‘AL 136 FCO 17 200 37 ‘080. 7 AD 137 FCI 18 207 8 ‘OBL 98 AB 138 oo 2 GRD. 3 O82 3 ‘GND 139 DOL 2 ‘VDD, @ ‘OBS, 100 VDD 1 Doz zi ‘GND, ai OBS: 101 HL Tal Dos Zz ZCLK 2 (ei) 102, XFDW. 142, Dos B ‘WRES 3 OC 103, XFDC 143 Dos ma Zz. a OGz 104, XDIS 144 ed ee | 26 25 6 ‘Oct 106; ‘VDPM. 146 ‘Dow. 7 Zs 7 Os: 107, ROM. 147, (Doe [204 & (O66 108; ‘ASEL 148, Dio | _ZAF @ STO 108. XTIM 149 Dir 2 ZAE 70. TST 110 RAS2 150 DIZ 3 ZAD 7 TsT2 i CASE 151 DIS 32 ZAC 72 XIAP 112, ‘OBO 152 Die 33 ZAB B AOI 113, ‘CASO 153 Dis 34 ZAA Zz ‘02 14 SRES 154, NTS. 35 ZAG. 75 AOS Hs CED, 135; SY 36 ZAB 76 ‘04 116; XLWE 156 SOUN 37 ZAT 7 ‘AOS: 117 TALS 157, TNTA 35 ZAG 78 ‘A06 118 NOE 138 EDCK 3 TAS 79 “GND. ng EOE, 159) ‘GND. Ca VDD 2 GND 120) ‘VDD 10, ‘GND -413-IC6 Z80A Central Processing Unit 1c 7808 Parts No. = 315-0041 Top View & Pin Layout Ml Description Pin Pm Nan] VO Function SOOT ao-ais | SSTATEO | Sysem address bus, TS] pop7 [SSTATEUO| Syem dab © |COOCK| 1 _| Receives SV single-phase clock signal ‘ative "Low" Tf the inpavoutpar device Wsues & signal ‘that requests an interrupt to the Z80 CPU and the terrupt enable flag is zero, this interrupt request is accepted at the end of the insruction that is currently in progres. a6 | INT t ‘Active “Low This i an Inierupt request that bas priority over INT and cannot be inhibited by the toftvare, NNT is always accepted, and when the insta: tion that is curently in progress finishes, inerupt processing i stared and the 280 CPU automatically stars from address COS6H | NM 1 ‘Active “Low”, This indicated that the HALT instruction is being executed. Executes the NOP instruction inter 38 | FACT © | nally and also refeshes memory. The halt state is released by RESET. NMI or INT (when enabled), ‘Active “Low”. This indicated thatthe address bus outputs 19 | RED | 3STATEO | age effective memory addres for memory readite ‘Aaive "Low" This indicates that ie low-order 8 bis of the address bus output effective addresses of the 20 | TORS | 3STATEO | puvoutput device forthe read/write operation with this device. This is output together with Mil during an interrupt response fo indicat the response. ‘Active “Low. This indicates the timing with which data 21 | RD_ | SSTATEO | ‘om the memory orinpioutpt device is read ‘Active “Low”, This indicates thatthe effective data to be 22. | WR | 3STATEO | writen to the memory or inpuvloutput device the address ‘of which is specified ison the data bus. "When the bus request is acknowledged, this informs the 23 | BUSAK | 0 _| bus master which ousputs the bus request thatthe system bus can be controlled. ‘Active “Low”. Signal to inform the CPU that the ‘memory of input/output device the address of which is specified is not ready to send data. The CPU is waiting ‘when this signal is input ‘Active “Low”. This has priority over NMI and is ‘accepted atthe end of the machine eycle that is currently in progress. This is set to “Low” when a bus master other| than the CPU wants to contol the system bus. 2s | BUSRO 1 ‘Active “Low”, This resets the interrupt enable flag, interrupt vector register and memory refresh register of| the program counter to set the interrupt mode to mode 0, thus initializing the 280 CPU. indicates that the machine cycle executed is an OP code fetch cycle. ative “Low”. This indicates that the addres Tr =H refreshing the dynamic RAM is ouput to the low-order 7 * © | bite of the address bus. MIRED also goes “Low” at this time. —14-IC7 65536 bit Static CMOS RAM Ic UPD4168C-15 IC MBB464A-15L Ic KM6264BL-12 DIP600 Ic HY6264LP-15 Ic UPD4168C-20 Ic UPD4364Cx Ic HMe2641-120 Ic HMez651-90 I Top View & Pin Layout ADDRESS INPUT (OUTPUT ENABLE INPUT DATA INOUTPUT +5 POWER SUPPLY (CHIP ENABLE 1,2 INPUT ‘GROUND WRITE ENABLE INPUT NO CONNECTION IC UPD4168C-15-SG Ic UPD43640-15 Ic TMM2084-15 Ic TMM2063-12 IC KM6264BLS-12L DIP300 Ic KMa264L-15 IEBlock Diagram os.50 laponess| | row (ase x 258) uFFER | loecooer| | MEMORY CELL "ARRAY I i weur |_| sense swirce || ourpur cel COLON |conTRot| conta _DECODER TOORESE curren | z qALAL | oe we 1 Operation Mode | ce | OF | WE MODE OUTPUT STATE _| POWER SUPPLY CURRENT #H x x x Non-select | x LL x x (Poverdown) | Highimpedance is L|_# a # ‘Ourpa 1 L_f_# L a Read Dos een L ce L Write Ds Ica CUSTOMIC IC CUSTOM CHIP YM7101 Parts No. : 315-5313 I Top View & Pin Layout -15-Description wo-| Pr Name [10 | Paton [re [Panere [0 Fincion 7 TS, 30 | SBCR | O | Subcarmeroupun a A7A.SaMie cock) 2 | SD, 3] CLKy | 0 | 280 CPU clock (3 S8MHz) 3 SDy 32 | _MCK |__| Master clock input (53.7MH). T 80s 33_| EDCK | 00 | Dot lek ipstoupu (134/107. Sposa | | easel bs 2 ee © | Sg 3] cD) | 7 [S05 36] oD, | @ | SD, 57] oD, | o| 3 8 | CDs 10 | Sep 9] CDy np st | CD TRAST 9 | vnan sete al oy we] CAs) $2) 1 tg | cpu data bs. 14 |__WEy | Cg ~ 15 | Wey | CD 16 | OE | S[_Dye 17 [np | — | GND | Cy 16 | RDp | yp 19 | RD, 6 | Cys 20 | RD, @ | Dy zi | RD, 70 | Die 2} Rs 10| vam aunts ae | _RD, m2 [Cay 2 | _RDg 73 | Cay 25 | RDy 74 [Cag 25 | __AGC | — | ROB analog GND. 75 [Cay 27 [R(ANLONG) 76 [_Cay 25 [G(ANLONG)) 0 | Linear RGB ouput 7 [Cag 29_[B(ANLONG)| 78 | __CAy 30] AVC | ~ | RGB analog VDD 79 | CAs 31] ADy @ | CAs 3] AD, a | Cay 33] AD, | CAy | VO | CPU address bus 34] ADs | Cay SLADE] MO | VRAM ated bs myo 36 | ADs | CA 37 | _ADg 3 | Cay 38 | AD, #7 [Carp 32] YS | © | Transparent output 3 | _CAyp 40 SPAB LO | Sprite timing /O. 89 CAng 4 |_VSYNC_| 0 | CRT Vayne our cloak out 30 | Carp 2 | CSYNC_| 10 | viDeO+PSG 31 | Chap 3 | RSYNC | U0 | CRT SYNC ipuvourput sz | Cag) [AL | 1 | Lighten detest %3 | _CAze | Sele | 1 | CPU selec (80007280) 4 | _AYS 46 [PAL | 1 | CRT select (NTSC/PAL) 35.|_ SOUND 7 [RESET [1 initia eset input 96 | _AGS: 48 | SEL, | 1 | 68000CPU clock (CLK) /O control. || 97 | _GND_ 2] CLK, [0 | 6000 CPU clk eT) || 96 | INFNo, | PinName | vo | Function No.| PinName | 1/0 Function =] oe [o| Tia] DTAR | 10 | 66000 inverse 100] BGAK | 10 | 68000 interface us| _OWR ro | Bo] || 16] _LWR. 1o2| REO | 1 | 280imerface 117| OED | © | Work RAM strobe conto. 103 IRTAK | 1 | 118] _CASp ro4| Py | | 00 merce 119| RAS 105| Ply | 120| Rap 105] TORO 121 | Ray Wort ROT | sre vz | Ry 108 | WR 123] RAg |, | Work RAM (DRAM) adiresviolor 109] Mt 124| Ray code output 110] As. 125 | RAs mm | _UDS 126 al FEE | | 000 inetce = Te 113) Rw 128 _vop | 1 | Digital VDD. = a7IC9/10 65536 Word x 4bit Dynamic RAM Ic MsMacze4l-12 IC MsMacz6aL-15 IC UPDs1264v-12 IcMBe1461-12 Ic HMs34612P-12 ICTMS4461-128DL_ IC V580261210 Ie KMaz4c64z-10 Ic MSMms1C262.102S W Outside View Pin Layout Block Diagram LUNE OR ROW ADDRESS BUFFER / Qe A04 row ecooen KY, were " i RO) Wak (DATA, t BUFFER wo) OUTPUT | ToRROW TA LG o,| neotes 4 | aooness nut une Lo eine : .o- oe etSen i 7 250K MEMORY CELL | a. ! Tf it | 6 : pase ost nearer i ADDRESS | U if u y ‘SERIAL i nomEN senitparaseicoron (=, $654 | -@ 5) feourour i |~dse "Pern Line avoness a ROW ADDRESS: ‘STROBE INPUT STHCUEMPUT no i WRITE BAR BTTWRITE WBATE( Been ENABLE INDI, INPUT CLOCK OSCILLATOR: Ove scrarmeren ora OUTPUT ENABLE © ema cowrnoL wut => I i i semauenaseweur SE@—] —18-IC11_ FM Sound Source/DA Converter Io yma612 I Top View & Pin Layout Description No. | PnName | 10 Function T GND =| Greend pn 2 Do 3 D, 4 De 5 De vO | B-bitbiirectonal data bus. Communicates data with the processor 6 Dy 7 De 3 De 3 Dy 10 TEST i) Pin to test this LS]. Do not connect. Tr Te 1 Tnitializes the internal register. 2 GND =| Ground pin, D = | Inept seal sued frm the wo tna, When the ime programmed in he vines tas elapsed, this goes low. Output with open dain ‘Control the DO = D7 data bus cS [RD [wR] Al | AD Denil Writes giver of ners ee Wiis register daa of timer, ee. 1 ° ' 7 ° 1 Writes register data of channels 1-3. 3 ed OLA | O | 1 | 0 | Wiites register addrests of channels 6 « o O [1 [0 | 1 | 1 | Writes register data of channels 46 > me Oo ft | 0 | 0 Reads statuses z 2 T LX |x |X |X| DO D7 are set wo high impedance 19 | _AGND =| Groond pin - seh (© | Two-channe analog opus. These are output with asoure follower BH} Ave = | 45V power supply pins. ue _| oMVer T | Master clock inet = 49 =JEGA DRIVE PAI IC13 RGB Encoder IC CXANT45P Top View 2 13 ARARA ARE AEE Wie ‘on ° PERUEEOEEES t 2 Pin Layout Bowe ee oo es & 8 # B+ ob oF ge fF & @—P—3—O ® @—B—_OD—B 2 4 A ct J oi | me esuiatr] le. fo la q fa q By q Bl fl vo <6 vec C Bo we1C15,17 Three Terminal Regulator IC MA7805UC IC MC7805CT Top View I Block Diagram {e) dm ] Y i as WW evo our Ko “Te az an -21-IEGA CD / SEGA CD PARTS SPECIFICATION IC1_ 16/32-Bit Microprocessor IC MC68HCOOFN12 Ii Top View & Pin Layout aaa, alsgeecallad SEBescuaseeasseee Ie HDssHCo00cP-12 IC TMPEBHCOOOT-12 I Signal Description nooness aus See reser =r DATA BUS lt ———pis-00 x roo a processor [Fer Tos | Asvncunonous Sarvs | 2 Ba pee caine csencooe | BTASE -AI8 a MS penuptienal ¢ =< | ARBITRATION a Cournot |v ‘SONTAGL ERR svsten {hese venue CONTROL = CONTROL Description [No|PinName|vO] Function | [No|PinNameVO] Function | |NoPinNamelVO] Function a) [VBA | 1 | Vand Peripheral Adaress| [40] Ag Zz]: 2a} BERET [Bus Eror alae STD, 1/0 | Data Bus 25{-1h [A 4[_D, 26 1 | interrupt Control A] cg, [Ome s1-e Pay 50] Ay €| AS | O | Address Strobe 28| Fe, St _Ay 7 [UBS [0 |Unper aa Stabe —] [29] FC —| 0 |Procesorstatwe | [52] Vor | = | Power Supp &|_Lps | O | Lower Data Strobe 30 | FC, S3| Ag 9] RAW [0 [Read/Write aif NC [= 34] A © | Address Bus Brack | [Dat Transfer 32] Ay s5[ Aa 10 a 1 | Acknowledge 33. 36] Vs, -|GND Ti] BG | 0 [Bus Grant 34] As 37] Vs 12| BGACK | 1 | Bus Gran Acknowledge ||35| Ag ‘58 |D, | 13] BR 1 | Bus Request Eq 59] Dy Ta[ Veg | = [Power Supp STAs | —D; is[ CURT [lock [AL ata 5] Vs] —]onp SLB o | adie Bus os T7T_¥, way [Dig —]10| Data Bus Te] NC | = | Nor Coen a} A ele 19 | RAET [VO] Hale a2] Ann [Dy 201 RES [WO] Reset #3] Ag [Dy 21 [WMA | | Vale enon Ata] [aa A o_O 2 E10 [Embie BAe [DyIC2_ CUSTOM CHIP MCE2 No] VO] PinName |[ Wo. | vO | Pin Name Pans No, : 315-5548 =] Ves Ta = Ves 6 [1 TRO | [148-70] Boe WTop View a7] 1 | _xM_| [14s | 10) BIG [1 | tepcx—| [71s] B11 39 | 0] oxrem_| | isi |_| Boz 90[ 1 [ren —| sz [10 [oi 91_| 1 wart | [183 | 0 | Bb 92) 0) oHRD | 52 |= |, 31 mnt | {185 | 70] BDIS 34_[ 0] —ocpe | |"156_[ v0] —BPRAG 95| 0 | OPROE || 187 | 1/0] BPRAT 36 [= ¥, 138_[-VO_|_BPRAZ oT = [Vp 159-| 70 _BPRA3 98 | 0 | ocaR | | 160_| v0 | BPRAS 39 [ 1 TaIg | 161] 1/0 | BPRAS io | 1 Tats | | 162_[/0_|BPRAG Tor | Tal? | |165_[ 0 BPRAT 102] 1 ais | [164 [= ¥; 7 103 | 1 ais | {165 — Von No | WO | PinName |[ No. ] UO | PinName |{joe[—1—] tala —] | 16s [70 BPRAS To] cs | [3 = Veo 105-[ TO] Bats | | 167 |_0 | OPRRAS. 7-0 | opram_|{-4¢[ 0 | Gowe—} [106 [10 | Bata] [168 [0 | oPRcas, 3 = v 45_| 10] BoADO_| {107 | = V, 169| 0 | OPRUWE STP ORBROM_| [aT 0 [Boa —| 0s | “OBA } [7170-[ 0 oPRL WE So 1koM | [a7 | v0] Baba | 05 [vo Bato} 710 var So icaso| [4s [0 | B0aDS | [10 |_ WO |— Ba | 72 [v0 | Wva2 71 | owe] [49 [Baa] Pt [0 [pas | 173 [vo [vas 3] 1 | tower | |730 |= Vs naz [WO [Bar| [174 [v0 vas o[1_]taset—] |7$1| 70 [ Boas} [7113 [- vo [Bae | 175 [vo | Wvas 10 = Von ‘S| v0|BOADe || 44 |= [Von | [176 [= Vs T_[ 1] RAsz —] [53_| v0 | Boap7 | 7s vO [Bas] a7 [Was iz [1] casa] [s¢_[ vo | Bobs | 16 [vO Baa | [178 [0 | 1var Bp} ee | [sso [009] 7 [vo [Bas] 979 0a Te_[ 1 | TFRs | [seo popi0 | Tire [vo az] [180 [10] Was. =| V; 37 | vo | BoD | [119 [= V, 1e1_|_ 10 IVAIo 16[_O | OERES | |"ss_| vo] Bopi2 | "120 | 70 | Bar 182| uO [ VAIL 17_[-W0_[Beapo—|{~s9_| 0] Bobis_| zi [ Tt [roo] Fass = 7 16_|- WO |BEADI_| | 60_[ = Y; iz 1 IFC] | [384 [ WO_| Wiz 19-[- 0 Beab2—|[-61_| = [Vp] [423 | oor [iss [0 [vais {0 | BEADS] [e210] Boba] [ize 0] —orpt | [186 | 10 | Wale 2i_| Wo | BeaDs | [3 | vo] Bois | 125. [ 0 [ora | [ier [v0 | Wwais 22_| WO —| BEADS] [se] 0 | ~oLeDR | [126 [~0 [ovr | [ies [v0 | Ivate 23_| O| BEADS] |~5_| | OLEDG | "127 |~O | “oreser_| 189 | — Vy; | -O|BEAD?_||~65_| 0 | LATCH _| [128 [0 | onaLT | [150 [1 [ Taiz 25-0 | Beps ||? | 0 | osHFT | "129. [ 0 | oct | [191 | 10 |“ BvD0 25 [= Ves | 0 | oat | {130 = V; 192 | 10 _[BVDI m= VY; @[-0| opt | | 131 | =| Voo. 153 | 10 | _BvDz [| BEDS —] [70] 1] are | [132 [0 | optack_| ise [v0 | vps 2310 —| —BEDIO—] [771] _F_|iscor | [133-1 [ix | 95 [v0 avp4 30_| vo | Ben | [72 [= 7 Ta¢_|1|_1xLps | |196-|~v0 | vps: 310] Bepig—] [7731 [isso] 7135 [| xups | [197 | v0 | Bv6 32-10 | _Bepis | [74 [o| Exc | [136 [1 [kas | 198 [v0 | 5v07 33-10 | Bepia | [775-1 | Tore | [137 [0 [ bo | 199 | v0 | vps 34_[-0[ BEDI] [76 [1 | ata | [138 [vo [Bb | | 200 | = V; 3s_|_0 | ogRAs_|[77_[ 1 [ice | 38 [vo [pba [201 [Von 36 ‘Oecas—||~78-| 1| B83 | [140 [ 0] Bos | | 202 | vo | Bv08 370 | OBE —} [79 = Vo Tat] | —Bba [203 V0 [BvD 10 3 Vs 30] vo| B07 | [a [= V; 706 | WO_| BvD 330} _oewe | [Tai] vO] ssi | [3 | O| eps | [205 [v0 | Bvbi2 [0 | ooras—| [-82| vo | —p0 | ae [vO] Bs | | 206 | vo | avis, HO | 00cas—] [783_[ 0 | onocK | [7145 || Bb7 | [207 [vo evbig @ 01 0008 —] [C811 1cKs0 | [146 [v0 [pbs | [206 [v0 TavisIC3_ PCM Sound Source IC RFSCI644 Parts No. = 315-S476A, Ii Top View & Pin Layout cama HELE HL HH Sema, ou 17 Testo» = m=Description (IC3) Pn) Name | v0 Function Pe] Name | vo Function 7 AID WSL RAMAT | | Low addres signs of te SRAM & 7-| ~All 76-[-RaMAO_| © | MROM. [Al | RAMAX | O | LSB address signal of he MROME 17] AS Fiigh order 32k byte SRAM & MROM 2a S| RAMC2B | O | select signal sar wo] paweie | o | LO™ order 32K bye SRAM & NIROW EAE] 1 | Adare signals rom uP sl sig . ad Signal to wate Gas to The paeado oe 63 | RAMWEB | © | SRAM or SRAM. Signal to read cata fom We parade as) MOE TAs «2 [nawoes | 0 | SE Se ot ROW gta? SDA his SEL DAGE | | sutpesgmtot Rand tena a7 st ‘output tthe parallel DAC. [ps a | zl ts 37 [Das zt ps | SHL | 0] DACTS "1" das sample old signal 2 LDS 1 | aa bos signals wit 2 30" SHR [0] DACT-3 7 data samplefhoi signal Signal obiained by sampling and Dz x 38 | _DACTR | © | holaing the DAC? outpurat SHR Signal obained by sampling and 28-1 Do 38 | pact. | o BAe | ap meatal fom oF holding the DAC? ouput at SL. RD et pf a aa | wean | o | Wor sek sal oupet he Ta WRB [1] Wit signal from 2. Snr ae eer es pcade ANT || © | neue | o | LR Ga Ha caper w Be er S[RAMADE) | these pine provide multiplex signals of 3S LRAMADS) | the low order addressidaa “to the || 36 | DATA | o | Digital audio data signal ouput to he SS TRAMADS| | SRAM, and. when comeced to an sefil DAC SE TRANEDT v0 | MROM ese pos grande cam ot |TS5 | acre | o | Bk GSE HEAT ov © Be @TRAMADT] | Win Comers to an SRAM thee | Har PRESETS LT Ree SOTRAMADI] | pins also provide data bus signals tthe er Sebo] _| Sant vo] XIN | 1 [An extemal apital oselllor i 53_[ RAMAIA ar aout | oe SS ‘cock signals input to XIN direct. SSTRAMAIZ| — | sigh ner dds signa te sane] [L121 TESTE Tessie inp. Neral, fda 56 RAMA] | 0 Ee S7[RaMAio] | & MROM. | 17 | TEST? | 1 | sowever, TEST2s fixed at "H" when 33 RAMAP ie | TESTS sn MROM or SRAM is used. 53" RAMAB 12 = RAMAT 19 , ‘66 | RAMAG 431 voc | - | Powersupply pins STL RAMAS| ¢, | Low adress signs ofttesRaM& — |69"] 6 RAMAG MROM, 15 73 RAMA 52] GND | ~ | Ground pins 74 RAMAZ 72 (Note: The interface with the serial DAC is formed in the MSB initial mode. =IC5 CMOS Dynamic RAM « lo UPD424270LE-10 Hi Top View & Pin Layout . input Stato Output no | eration Mode RAS | CAS| UW] iW | State | OP HAD |B | Open | Sad HOD valid [Sia TOE] Haid [Read epee TL) EE) | 12) | Open —| Early write aye TEP T1)| Underined [Delayed wrt eyele TOE HSC] Valid Read modified write ee LE [HD | D| Open | RAS oly refresh evle HE [—L—[b_| | Open | CaS before RAS refesh avec T[H=0[-H [A _| Valle —[ High-speed page mode read eyele TL THE [EA | C2) | Open —| High-speed page mode early write le TL TH=L £2) [1 2) | Underined [Highspeed page mode delayed wri ere TTHSETHSC IHS] Valid Highapeed page mode read modified wnite aye Note: H-High(nacive), L=Low active), D=Don't care. IC6 Battery Back-up 1c MBs790 Hi Top View & Pin Layout Block Diagram wet] Lcowrnot Vaan] MOE Figwe Your EE] aM Your 3 Vn Vaare 5] [BVsexse ao, file, OAR, [7] fgReser ono] falreserIC 7/8 65536 Word x.16bit Dynamic RAM Ic T051166482-80 Ii Top View & Pin Layout 0 at R 3 a as as aT Ie 70811864280 Pin Name AOA? | Abies pa FAS__| Row Address Soke TAS___| Comm Adie Srabe TW | Reaper Bit Wate Inpat iw Read/Lower Bit Write Input OE Output Enable TOI=1016 | Da WO Ver _[ Power Sumy 50) Mss. | Ground Nic.__| Net Conesed v2 04 oo 108 1010 4012 10% voVe ve od Hor ior oe oN fo tore SPREE TTT ETT T ET TT Vee ¥ BATA OUTPUT DATAINEUT ' OE om) BUFFER ‘BUFFER: WoO q TT T i me—ta> [7] Cc ee Look Nee CRSO~) GENERATOR py cok BUFFER (8) Decoren) a SENSE ANP Sal rernesn ea CONTROLLER WOGATE po a] Tell o| meen a COUNTER & | 38 [1 | memory annay o-| BB | a ROW ADDRESS BE || asnxasexte gather: =) 8 | f \| | eooKne |! 308 STRAIGHT BAS FASo-| Generator GENERATOR —27-bie IC9_8-Circults Non-inverting Bus Tranceiver Top View & Pin Layout ‘OUTPUT ENABLE feo] fro] fre] frr7]_frg] 4 pps [OL fvliv{iv| | { iA [QOlA [Ea 9 Ie Te ey we IC10/11 Bbit CMOS Pseudo Static RAM IC TCS18324FL-10 Ii Top View & Pin Layout Symbol] PinName ‘Aran | Ades Input RAW | Read/Write Input BE/RFSH | Output Enable /Refresh ce | Chip Enable TO=WO,_| Data input Output Block Diagram Yo an coLun { { DECODER ‘SENSE AMP. z = Sonu awe) Abpaees WO GATE Se ess, by . =e : Tie |] [52 ROW ADDRESS [ay Ey oro 8) "Surrene fy] = 7} x | 1 | memory array — Bes 7 <== ult] mae | | [be cOUNTER E34 a) Ee T se Ly 52 cod aoe Ll ee ame] [5 aexeraron [| conTmotier MER senrsno— to le Tes1@32FL-40 Pin Configuration and Pin Description — 28 — Wo1-vo81C13. CD-ROM LS! te Lceest MiTop Viow 4, 4 Description No] VO | PinName ][ No. | UO | PinName || No.| VO | PinName |[ No. | VO | PinName TL ¥, |W] 105 a= ¥; ao Er 26 RAG Z| Wo [oz @2_| 10 D3 [0 RCS 30] Rar, [10 | 101 3 | 00 Dé 6 |_0 | HOE 410 RAB zt = V 44] WO Ds | = V; so RAO 2s") extac_| [| 00 Dé. | WO_| HD? © | 0 | RAlo 26[ 0 | xTaL | [46 [ 00 Dz, | WO] HD. 7 [0] Rall 3 rest |[ar RS | WO_| HDs =| 0 | RAI2 5a | BD. | WO] HDs 9 [0 | RAs a se | [a WE | vO] HDs 1o_[ | Ral 30) 1 | bwsec | [7s0[ cS 70 | WO_| abe | -O | _Rals 3] = Von s1_[ 0 INT 7i_|_W_[ HDI iz [0] _RWE 32] 1] trek | [752 [= Vv; 72_| WO] HDO. 3 V, 33) 1 | Sbata_||[-s3 [1 | Reser_|[3 | — Von ia| 0 | ROE 3 BCK sé_|1 | ENABLE | | 75 SELDRO 15_[ WO _| ERA 3s [cat | [55 ew | 7s [oa 16 | | Ios 36] 1 | c2P0. 36 [1 HIRD. 76 {0 RAL 7 [10 [ 107 37_|_0 | __MCk 74 TxD 7 {0 RAZ 18 | 0 | 106 36 [ 10 [bo $80 | wait || | 0] Ras 19 | | 105 39 | 10 Dr 39_[0_| ren || 79 [0 RAG 20-10 | 10a [10 D2 “0 wo 10 RAS IC14/15/16 64k(8k x 8)bIt Static RAM Ic MB8464A-90 IC MB8464A-80 IC MB84644-10LL PF-G-BND Top View & Pin Lay Block Diagram WiTop yout a iagr ties 0 Gno Ano . — 1 1(| | besgsanen ‘Data inputs/ourputs z 8 suede Chip select 3 5 :Chip salt 2 AsO 3 Output enable Tes —— Write enable = Power supply (+5V) ‘ = vo Gare, COLUMN ‘Ground BUFFER ‘DECODER, ‘Not connected Ao: Tes — FEO eur weurroureut | cs BUFFER BUFFER weo—| Tes —29- I WO, —— Wshide IC17 2-Circult D-type Flip-flop lo 74ac74 icravnc74 Ii Top View & Pin Layout Von FE 02 cia PRE ae fal_fis]_fa]_[ri]_fio]_[o ux” 9 . _I [2] aan lb Cex IC1/2 18Bit Digital Filter & 16Bit D/A Converter Io Levee -c Ic 7883KM Top View Description Pa] Name [00 Fanaion Pa] Nave [00 ae 1 [SHOUT | 0 | DAG capa Te EMP] , | oecammncu 2 Vref = _| Reference voltage “H™ input. 1s | EMPHI cde 3 [LAVDD | = | Powersupply of anlog cesta] [16 | DN | 1 | Dobie Rormal spend swing pin 4 | DYDD | — | Powersupply of digital circuits. 17 | soca 1 | Input source select inputs. § BLCK 1_| Bit clock. 18 | soci (PULL-DOWN) Digial ado daa apt ecw ioe 6 | DATA | 1 | Input from the MSB in the 19) MODE | 1 | ULLDOWN) i 20, “Test pins. (normally, set to “L”) TUR cick iat tary 7est | | pudl’oowny y 7} ance | 1 | tack ern LRCK "A cat 2 [BERD | = | Grwnd of igial dra 8 ‘TEST 1_| Test pin. (normally, set to “L”) 23 | cxour | 0 Seas te ROUT ‘Attenuator data input. Input from the % 3 | arr | 1 | Aten da int a Sears aS S128: XOUT TO [SHIFT [1 [Atenustr dt wansfercock inp || 24 [XIN [1] Coa ostinor inp TH [LATOR [1 [ Atenoatordt inch cock input] [ 25 [_XOUT | © | Cryst esi ope inaining signal 26 | AGND | — | Ground fale cui 2 es : (normally, set to “H") Eu Vref. —_| Reference voltage “L” input. BL TET LT [Tesla (arma. sao) 2 [ GHa0uT [0 | DAC CHa cup —30-1C3/4/5 Quad Operational Amplifier Ic uPcasaca Top View 14 5 IC6 3-Terminal Voltage Regulator IC UPC2405HF Front View 9° 3 U z ia INPUT gNp OUTPUT -31- MEPin Layout Mf) fs) — vee Lear 4 — yoo woSEGA ©1994 Sega Enterprises, Ltd. Printed in Japan (1) 40420