Benefits and Challenges of Designing Cryogenic
CMOS RF Circuits for Quantum Computers
M. Mehrpoo∗ , B. Patra∗ , J. Gong∗ , P. A. ’t Hart∗ , J. P. G. van Dijk∗ , H. Homulle∗ , G. Kiene∗ ,
A. Vladimirescu† , F. Sebastiano∗ , E. Charbon∗§¶ , M. Babaie∗
∗ Delft University of Technology, Delft, The Netherlands † University of California, Berkeley, CA
§ EPFL, Lausanne, Switzerland ¶ Intel, Hillsboro, OR
m.mehrpoo@ieee.org
Abstract—Accurate and low-noise generation and amplifica-
tion of microwave signals are required for the manipulation
and readout of quantum bits (qubits). A fault-tolerant quan-
tum computer operates at deep cryogenic temperatures (i.e.,
<100 mK) and requires thousands of qubits for running practical
quantum algorithms. Consequently, CMOS radio-frequency (RF)
integrated circuits operating at cryogenic temperatures down
to 4 K (Cryo-CMOS) offer a higher level of system integration
and scalability for future quantum computers. In this paper, we
extensively discuss the role, benefits, and constraints of Cryo-
CMOS for qubits control and readout. The main characteristics
of the CMOS transistors and their impacts on RF circuit designs
are described. Furthermore, opportunities and challenges of low
noise RF signal generation and amplification are investigated.
I. I NTRODUCTION
Quantum computing promises to solve specific compu-
tational problems exponentially faster than any imaginable
digital computer. These problems include DNA analysis, effi-
cient search in gigantic data sets concerning medical research,
consumer behavior and financial markets [1], and optimization
of materials and industrial chemical processes [2]. Quantum
mechanics permits a particle to exist in a superposition state
and be entangled to physically separated systems. These phe-
nomena are exploited by quantum machines to simultaneously
produce rich configuration states and highly correlated behav-
ior to tackle classically intractable computational problems.
A quantum computer operates by processing the information
stored in quantum bits (qubits), the states of which is repre-
sented using Dirac’s notation, as a superposition of |0i and |1i
states. Although qubits usually operate at deep cryogenic tem-
peratures, their coherence time and gate fidelity are typically
not sufficient to be used as computational qubits directly [3],
[4]. It is, however, possible to perform fault-tolerant quantum
computing by exploiting quantum error correction (QCE),
which encodes the information in a logical qubit constructed
from a collection of physical qubits [5].
Performing operations on the qubits requires a classical
electronic controller for manipulating the qubits and reading
out their quantum state. Currently, state-of-the-art quantum
processors contain only a few qubits (<20 qubits) and require
This work was supported by Intel Corporation.
978-1-7281-0397-6/19/$31.00 ©2019 IEEE
ADC
MUX
LNA
LOI/Q
READOUT
Digital Control
(ASIC/FPGA)
Quantum Processor
LOI/Q Phase
Detector
Frequency Synthesizer
CONTROL LOI/Q
DEMUX
Driver DAC
Pprobe
1-4K
20-100mK 300K
Fig. 1. Block diagram of a cryo-CMOS circuit for qubits readout and control.
multiple RF and DC cables per qubit, which are each con-
nected to room temperature laboratory instruments [6], [7].
However, more than 100 logical qubits are needed to reach
quantum supremacy or solve a quantum chemistry problem
even with the most straightforward quantum algorithms [8].
This indicates the need for thousands or millions of phys-
ical qubits by considering the redundancy added by QCE
schemes, such as surface codes [5]. Consequently, for the
fault-tolerant quantum computer with millions of qubits, indi-
vidually connecting each qubit to a room-temperature off-the-
shelf electronics becomes challenging, if not impossible, due
to the utter interconnect complexity, poor system reliability,
and cost. A more promising approach is to integrate the
readout and control circuitry in a standard CMOS technology
operating at cryogenic temperatures (cryo-CMOS), leading to
a significant reduction of form factor, power consumption,
and system cost/complexity and most importantly enabling
scalability [9]–[11]. This approach significantly improves the
latency of the QEC loop by reducing the round-trip delay of
cables and filters, which is considerable with respect to the
qubit operation time.
Qubit control and readout require generation and acquisition
of specific RF signals. For instance, for control of transmons
(superconducting qubits), a 4-8 GHz microwave signal with a
duration of <1µs must be applied [12], [13], and for their state
readout, the resonant frequency of a microwave resonator that
 (a) (b)
(e) (f)
Fig. 2. (a)-(g) DC characterization and translated parameters of an NMOS transistor (W/L = 1.2 µm/40 nm) at 300 K and 4 K, (h) a class-A power amplifier.
is strongly coupled to the qubit is measured. Consequently, as
can be gathered from Fig.1, the simplified block diagram of
the Cryo-CMOS controller comprises several RF blocks and
closely resembles a wireless transceiver.
In this paper, we focus on the benefits, constraints, and
challenges of designing cryogenic CMOS RF circuits. The
primary characteristics of CMOS transistors and their impacts
on RF circuit designs are described in Section II. Section III
and IV focuses on the design opportunities and challenges of
the implementation of two fundamental blocks present in the
system diagram in Fig. 1, i.e., readout circuits and frequency
synthesizers, respectively. Conclusions are drawn in section V.
II. C RYO -CMOS CHARACTERIZATION AND IMPACT ON RF
CIRCUIT DESIGN
DC characterization results of 40-nm CMOS devices, shown
in Fig. 2(a)-(c), can be translated into design-oriented param-
eters in Fig. 2(d)-(g), to analyze how cryogenic CMOS affects
RF circuit design choices and strategies. From the ID -VGS
curves shown in Fig. 2(a), it can be observed that the threshold
voltage at 4 K increases by almost 100 mV compared to room
temperature (RT), due to an increase in ionization energy [14]
[15] [16]. This presents a challenge for voltage headroom,
especially in case of stacked transistor-based circuit topologies
with demanding high linearity requirements. Hence, there is an
urge to use low VT H devices and constant current biasing. As
shown in ID -VDS curves of Fig. 2(b), there is an increase in
the current driving capability of the device mainly caused by
an increase in mobility of the devices at 4 K due to a decrease
in electron scattering [15].
Fig. 2(c) shows the transconductance (gm ) as a function of
VGS , suggesting that there is an increase in gm by almost a
factor of 2 in the strong inversion region. An increase in gm ,
(c) (d)
VDD
POUT
RL
Pin
Vb
(g) (h)
while no change in gate capacitance (gate oxide/metallization
variation) points to an increase in device transit frequency (fT )
[17]. Fig. 2(d) which shows the rout of the devices at RT and
4 K, suggesting that the rout decreases by a factor of 2 in the
strong inversion.1 Finally, from Fig. 2(c) and Fig. 2(d), one can
infer that there is no increase in the intrinsic gain of the device
at 4 K compared to RT, as shown in Fig. 2(f).
After analyzing the effect of device parameter variations,
let’s consider the design example of a highly linear class-
A Cryo-CMOS (power) amplifier, as shown in Fig. 2(h). The
voltage gain of such an amplifier is governed by
gm
Av = gm × RL = × (RL .ID ) (1)
ID
where RL (RL << rout ) is the load resistance seen by the
amplifier and is fixed by the matching network, ID is the
current of the amplifier and is determined by the output power
(POU T ) required to drive the qubits. As can be gathered from
Fig. 2(g), in order to obtain the best linearity, the device should
be biased in the strong inversion region at an overdrive voltage
of ∼0.25 V, for both 4 K and RT. The device can then be sized
based on the calculated load current and overdrive voltage.
From Fig. 2(e)), it can be observed that in the moderate and
strong inversion, the gm /ID remains almost the same over
temperature. Consequently, the voltage gain of the amplifier
would be the same over temperature, for large signal operation
where linearity is crucial. However, if the linearity require-
ments are more relaxed, in blocks such as readout low noise
amplifiers, it is suggested to bias the transistor towards the
weak-inversion, where gm /ID is higher at 4 K, and thus the
circuit can be more power efficient at cryogenic temperatures.
1 To ensure the same operating region, the plots are made with the same
overdrive voltage (hence 100 mV increase in VGS at 4 K).
 III. C RYOGENIC R EADOUT probe

pulse amp.
signal gen.
digital readout chain

qubits state
High-fidelity readout of qubits is an essential element of matched amplification
filters downconv.
AWG

ωr1

ωr,n
any superconducting-based quantum computer, imposing strin- ADC
300K
gent requirements on the noise performance of the readout
chain [12], [13]. Moreover, a promising scalable readout Tpulse HEMT ~4K
20dB LNA stage
solution relies on the frequency multiplexing of many qubits, time
that would require circuits with GHz-range amplification band- supercond.
50mK

attenuator
Quantum Chip parametric
width and large dynamic range [18], [19]. stage
readout feedline amplifier
The readout of superconducting qubits, as schematically
30dB
depicted in Fig. 3, is typically implemented by dispersively

Port 2
Port 1
coupling each qubit to individual frequency multiplexed res- high-Q 0
readout

S21(dB)
onators, which are capacitively coupled to a common feedline.
resonator ωr1 ωr,n
During the readout operation, the feedline is probed with a
ωr1 ωr,n
short (100–300 ns [12], [13], [18]–[21]) weak RF pulse with super-

the same frequency as the qubit, which is typically within 4–
8 GHz. Due to the qubit-state-dependent frequency shift [19],
the notch in the feedline transmission curve (S21 ) gets slightly
shifted causing a state-dependent phase shift of the output
pulse, as shown for Q1 in Fig. 3(b). To be able to detect
this phase modulated signal with a power level of around
-130 dBm [20], the output signals should be amplified by
around 120 dB in a few stages before downconversion to
a relatively low-intermediate frequency (IF) and digitization
over a large bandwidth. Each carrier of the digitized signal
is then filtered with a matched filter to provide near optimal
signal-to-noise ratios.
To be able to achieve high-fidelity (>99% [13], [18]–
[20]) readout, many recent developments [12], [13], [18]–
[21] rely on a superconducting parametric amplifier, operating
at the base temperature close to the qubits, followed by a
high-electron-mobility transistors (HEMT) low-noise ampli-
fier (LNA), operating at 4 K. State-of-the-art superconducting
parametric amplifiers [22], [23] have shown broad bandwidths,
a typical gain of 20 dB, and noise temperatures close to the
quantum limit (e.g., 0.336 K at 7 GHz), making them crucial
components for multiplexed, high-fidelity readout operations.
The HEMT LNAs, however, have 10× larger noise tempera-
tures (e.g., the commercial LNA in [24], which is widely used
in the state-of-the-art readout setups [12], [13], [18], [19], has
the best noise temperature of 2.2 K over 4 to 8 GHz range with
a power consumption of 7.7 mW).
To be able to integrate the whole readout chain in a
deep-submicron CMOS technology, the applicability of low-
power RF CMOS LNAs at cryogenic temperatures has to be
investigated. Besides the analog/RF characteristics improve-
ment at cryogenic temperatures mentioned in section-II, the
minimum noise temperature has been also reported to improve
by approximately 10× in 32-nm SOI CMOS [25] at 6 K. This
might be surprising since a more significant change is expected
as the temperature has reduced by 50×. This has been recently
explained by observing that the channel noise in nanoscale
CMOS (with LCH <100 nm) is dominated by the suppressed
shot noise (Sid = 2qIDS F ) in the medium to strong inversion
regime [26], [27]. Such saturation of noise improvement versus
temperature can lead to excessive power consumption in the
zoomed
conducting
Qubits ωQ1 ωQ,n
|0 |1
ωr1 ω +Δ
(a) r1 1 (b)
Fig. 3. (a) Schematic of a typical frequency-multiplexed readout scheme for
superconducting qubits, with the readout electronics at RT. (b) an example
transmission spectra and the qubit-state-dependent frequency shift.
realization of LNAs with a few Kelvin noise temperature
requirements [10]. Consequently, to be able to break the
noise-power consumption trade-off of the active devices and
benefit from the cryogenic operation, alternative RF CMOS
amplification techniques such as parametric amplifiers need to
be investigated.
A parametric amplifier utilizes a nonlinear capacitance or
inductance together with a relatively large amplitude pump
signal to provide amplification of the desired signal [28]. The
operation principle can be intuitively explained by assuming a
simple time-invariant nonlinear response between the amplifier
3
output (vout ) and its input (vin ), where vout = vin +a3 vin . By
applying the desired signal (As cos(ωs t)) and the pump signal
(Ap cos(ωp t)) to the amplifier input, a component proportional
to a3 A2p As appears at the frequency of the desired signal. Hav-
ing sufficient nonlinearity and a large pump signal amplitude,
an amplification of ∝ a3 A2p can be achieved. As the noise of
reactive components is directly proportional to their loss and
the ambient temperature, the parametric amplifier can be a
promising candidate for low-noise amplification at cryogenic
temperatures.
The aforementioned superconducting parametric amplifiers
typically rely on a nonlinear extremely-low-loss junction that
operates similar to an inductor [22], which is currently not
available in bulk CMOS processes. Nonlinear varactors have
thus been employed by a few works [29]–[31] to achieve a
parametric gain in CMOS, where only [31] has demonstrated
RF parametric amplification using inductors and varactors. The
implementation in [31] is still based on an active LNA preced-
ing the parametric amplifier and has a limited 1dB-bandwidth
of around 400 MHz, and, more importantly, it is sensitive to
the phase difference between the desired and pump signals,
making it impractical for a multiplexed readout. Thus, several
hurdles must be overcome to fully benefit from parametric

101
Resistivity [10-9 Ω.m]
100
10-1
10-2
1 10 100 300
(a) Temperature [K] (b)
Fig. 4. (a) Copper resistivity versus temperature, (b) measured frequency of
an ring oscillator versus supply voltage taken from [14].
amplification in Cryo-CMOS, including the availability of
GHz-range bandwidth, phase-insensitive operation and avoid-
ing preceding active LNAs. Although this will be challenging,
we truly believe that adapting parametric amplifiers in cryo-
CMOS for qubit readout is the most promising approach.
IV. C RYOGENIC F REQUENCY G ENERATION
In order not to degrade the fidelity of a single qubit gate,
the integrated frequency noise (FN) of the control signal
should be <1.9 kHz [32]. This requirement directly translates
to -115 dBc/Hz in-band phase noise (PN) for a phase-locked
loop (PLL) and an out-of-band PN of -147 dBc/Hz at a
10 MHz offset from a 6 GHz carrier for an RF oscillator [10].
Achieving such a stringent PN is extremely challenging even
when considering the thermal noise reduction of active and
passive devices at cryogenic temperatures.
A. Performance of Cryo-CMOS RF Oscillators
The quality factor of passive components such as inductors,
and capacitors improves by reducing temperature due to the
reduction of metallization and substrate losses. However, at
some point, as shown in Fig. 4 (a), due to the impurities and
crystallographic defects in metal layers, the resistivity of the
metals, and hence the Q-factor of passives do not improve by
further reducing the temperature [33]. Besides, the Q-factor of
an LC tank also depends on the loss of switched capacitors
used for frequency tuning. As can be gathered from Fig. 2 (d),
the transistor’s on-resistance and thus Q-factor of switched
capacitors just improves by 2×. On the other hand, the channel
noise of MOSFETs in deep sub-micron processes is mainly
determined by the shot noise, which just scales ∼10× from
300 K to 4 K as stated in the previous section. Consequently,
we expect that the phase noise of an oscillator in the thermal
noise region reduces by ∼16 dB (10 dB due to channel noise
reduction and 6 dB due to the tank Q-factor improvement),
which is in line with the measurement results in [10].
The flicker noise of an NMOS transistor is mainly due
to the carrier-density fluctuation, caused by the capture and
emission of carriers at interface traps [34]. At cryogenic
temperatures, the dopants freeze-out and the free carriers
are mainly contributed by the negligible intrinsic electron-
hole-pairs, increasing the flicker noise [35], [36]. Hence, the
flicker noise corner of RF oscillators can go beyond the PLL
bandwidth at cryogenic temperatures, significantly degrading
PLL’s jitter and integrated FN.
In order to mitigate the effect of the increase in the 1/f 3
corner, one needs to resort to oscillator topologies with low
flicker noise upconversion. It is well-known that the flicker
noise upconversion in an LC oscillator significantly reduces
if the common-mode of the circuit also resonates at twice
the oscillation frequency [37], [38]. However, it is not trivial
to adapt this technique for cryogenic oscillators where the
value of single-ended capacitance significantly varies due to
Supply Voltage [V] substrate freeze out. Consequently, this issue calls for a new
digital calibration loop to automatically adjust the common-
mode resonance of the oscillator at its optimum point.
B. Performance of Cryo-CMOS Phase Detectors
The in-band PN of an all-digital PLL (ADPLL) is usually
determined by a time resolution of a time-to-digital converter
(TDC) [39]. To achieve the target in-band PN, the TDC
resolution has to be finer than 1 ps even when considering
a reference frequency (FREF) as high as 100 MHz.
The TDC core is usually based on a digital delay line,
whose time resolution is equal to an inverter propagation
delay (∼10 psec in 40-nm CMOS at RT). Fig. 4 (b) shows
the measured oscillation frequency of a ring oscillator versus
different supply voltages for both 300 K and 4 K [14]. The
oscillation frequency increases by ∼36% due to the higher
current driving capability of the transistors at 4 K, resulting in
∼6-7 psec for the inverter delay. Despite this improvement in
time resolution, to satisfy the in-band PN requirement, there is
a need for sub-gate-delay resolution for TDCs. Furthermore,
the current mismatch of CMOS transistors also increases by
∼1.2× at cryogenic temperatures as shown in [16]. As a
result, the TDC nonlinearity becomes much severer at 4 K, thus
degrading PLL’s jitter and spurious tone emissions. Therefore,
innovative PLL architectures (i.e., injection-locked structure
in [40], [41]) associated with intensive digital calibration
techniques are extremely required at cryogenic temperatures
to tackle the challenges mentioned above.
V. C ONCLUSION
Designing CMOS radio-frequency integrated circuits at
cryogenic temperatures is crucial to provide large scale in-
tegration, required to go from today’s small number (∼20) of
qubits to the thousands of qubits needed in practical quantum
algorithms. At cryogenic temperatures, RF designers can take
advantage of higher current driving capability, transconduc-
tance and the maximum power gain of CMOS transistors.
However, they require a new set of CMOS device models to
exploit those advantages, while at the same time satisfying
the extremely demanding requirements for quantum-processor
control and readout at a very limited power budget. Designers
also have to face unwanted degradation in device parameters,
such as higher threshold voltage, and lower output resistance.
Furthermore, transistors’ self-heating, shot noise and flicker
noise can deteriorate both the noise figure of the read-out
chain and timing of the control signals. Consequently, new
design structures and strategies are required to tackle the
abovementioned issues.
 R EFERENCES
[1] L. K. Grover, “A fast quantum mechanical algorithm for database
search,” in In Proceedings of the twenty-eighth annual ACM symposium
on Theory of computing, 1996, pp. 212–219.
[2] R. P. Feynman, “Simulating physics with computers,” Int. J. Theor.
Phys., vol. 21, pp. 467–488, 1982.
[3] E. Kawakami, P. Scarlino, D. R. Ward, F. R. Braakman, D. E. Savage,
M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, and
L. M. K. Vandersypen, “Electrical control of a long-lived spin qubit in
a si/sige quantum dot,” Nature Nanotechnology, vol. 9, pp. 666 EP –,
08 2014.
[4] L. DiCarlo, J. M. Chow, J. M. Gambetta, L. S. Bishop, B. R. Johnson,
D. I. Schuster, J. Majer, A. Blais, L. Frunzio, S. M. Girvin, and R. J.
Schoelkopf, “Demonstration of two-qubit algorithms with a supercon-
ducting quantum processor,” Nature, vol. 460, pp. 240 EP –, 06 2009.
[5] A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, “Surface
codes: Towards practical large-scale quantum computation,” Phys. Rev.
A, vol. 86, p. 032324, Sep 2012.
[6] “IBM builds its most powerful universal quantum com-
puting processors,” 2017. [Online]. Available: http://www-
03.ibm.com/press/us/en/pressrelease/52403.wss.
[7] J. Kelly et al., “State preservation by repetitive error detection in a
superconducting quantum circuit,” Nature, vol. 519, pp. 66 EP –, 03
2015.
[8] D. Wecker, B. Bauer, B. K. Clark, M. B. Hastings, and M. Troyer, “Gate-
count estimates for performing quantum chemistry on small quantum
computers,” Phys. Rev. A, vol. 90, p. 022305, Aug 2014.
[9] E. Charbon et al., “Cryo-CMOS circuits and systems for scalable
quantum computing,” in in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, 2017, pp. 212–219.
[10] B. Patra et al., “Cryo-CMOS circuits and systems for quantum comput-
ing applications,” IEEE Journal of Solid-State Circuits, vol. 53, no. 1,
pp. 309–321, Jan 2018.
[11] F. Sebastiano et al., “Cryo-CMOS electronic control for scalable
quantum computing,” in in 54th ACM/EDAC/IEEE Design Automation
Conference (DAC), 2017, pp. 1–6.
[12] C. C. Bultink, B. Tarasinski, N. Haandbæk, S. Poletto, N. Haider,
D. Michalak, A. Bruno, and L. DiCarlo, “General method for extracting
the quantum efficiency of dispersive qubit readout in circuit QED,”
Applied Physics Letters, vol. 112, no. 9, p. 092601, 2018.
[13] T. Walter, P. Kurpiers, S. Gasparinetti, P. Magnard, A. Potočnik,
Y. Salathé, M. Pechal, M. Mondal, M. Oppliger, C. Eichler et al., “Rapid
high-fidelity single-shot dispersive readout of superconducting qubits,”
Physical Review Applied, vol. 7, no. 5, p. 054020, 2017.
[14] R. M. Incandela, L. Song, H. Homulle, E. Charbon, A. Vladimirescu,
and F. Sebastiano, “Characterization and compact modeling of nanome-
ter CMOS transistors at deep-cryogenic temperatures,” IEEE Journal of
the Electron Devices Society, Apr 2018.
[15] F. Balestra and G. Ghibaudo, “Brief review of the MOS device physics
for low temperature electronics,” Solid-State Electronics, vol. 37, no. 12,
pp. 1967 – 1975, 1994.
[16] P. A. ’t Hart, J. P. G. van Dijk, M. Babaie, E. Charbon, A. Vladimircscu,
and F. Sebastiano, “Characterization and model validation of mismatch
in nanometer cmos at cryogenic temperatures,” in 2018 48th European
Solid-State Device Research Conference (ESSDERC), Sept 2018, pp.
246–249.
[17] A. Beckers, F. Jazaeri, and C. Enz, “Characterization and modeling of
28 nm bulk CMOS technology down to 4.2 k,” IEEE Journal of the
Electron Devices Society, 2018.
[18] C. A. Ryan, B. R. Johnson, D. Ristè, B. Donovan, and T. A. Ohki,
“Hardware for dynamic quantum computing,” Review of Scientific In-
struments, vol. 88, no. 10, p. 104703, 2017.
[19] C. K. Andersen, J. Heinsoo, A. Remm, S. Krinner, Y. Salathe, T. Walter,
S. Gasparinetti, J.-C. Besse, A. Potocnik, C. Eichler et al., “Rapid high-
fidelity multiplexed readout of superconducting qubits,” Bulletin of the
American Physical Society, 2018.
[20] Y. Salathé, P. Kurpiers, T. Karg, C. Lang, C. K. Andersen, A. Akin,
S. Krinner, C. Eichler, and A. Wallraff, “Low-latency digital signal
processing for feedback and feedforward in quantum computing and
communication,” Physical Review Applied, vol. 9, no. 3, p. 034011,
2018.
[21] C. C. Bultink, M. Rol, T. OBrien, X. Fu, B. Dikken, C. Dickel,
R. Vermeulen, J. de Sterke, A. Bruno, R. Schouten et al., “Active
resonator reset in the nonlinear dispersive regime of circuit QED,”
Physical Review Applied, vol. 6, no. 3, p. 034008, 2016.
[22] C. Macklin, K. OBrien, D. Hover, M. Schwartz, V. Bolkhovsky,
X. Zhang, W. Oliver, and I. Siddiqi, “A near–quantum-limited josephson
traveling-wave parametric amplifier,” Science, vol. 350, no. 6258, pp.
307–310, 2015.
[23] T. Roy, S. Kundu, M. Chand, A. Vadiraj, A. Ranadive, N. Nehra, M. P.
Patankar, J. Aumentado, A. Clerk, and R. Vijay, “Broadband parametric
amplification with impedance engineering: Beyond the gain-bandwidth
product,” Applied Physics Letters, vol. 107, no. 26, p. 262601, 2015.
[24] LNF–LNC4 8C: 4-8 GHz Cryogenic Low Noise Amplifier, Low Noise
Factory, 2018.
[25] A. Coskun and J. Bardin, “Cryogenic small-signal and noise perfor-
mance of 32nm SOI CMOS,” in Microwave Symposium (IMS), 2014
IEEE MTT-S International. IEEE, 2014, pp. 1–4.
[26] J. Wang, X.-M. Peng, Z.-J. Liu, L. Wang, Z. Luo, and D.-D. Wang,
“Observation of nonconservation characteristics of radio frequency noise
mechanism of 40-nm n-MOSFET,” Chinese Physics B, vol. 27, no. 2,
p. 027201, 2018.
[27] X. Chen, C.-H. Chen, and R. Lee, “Fast evaluation of the high-frequency
channel noise in nanoscale MOSFETs,” IEEE Transactions on Electron
Devices, vol. 65, no. 4, pp. 1502–1509, 2018.
[28] R. E. Collin, Foundations for microwave engineering. John Wiley &
Sons, 2007.
[29] S. Ranganathan and Y. Tsividis, “A MOS capacitor-based discrete-time
parametric amplifier with 1.2 V output swing and 3 µW power dissi-
pation,” in Solid-State Circuits Conference, 2003. Digest of Technical
Papers. ISSCC. 2003 IEEE International. IEEE, 2003, pp. 406–502.
[30] A. Yoshizawa and S. Iida, “A gain-boosted discrete-time charge-domain
FIR LPF with double-complementary MOS parametric amplifiers,” in
Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical
Papers. IEEE International. IEEE, 2008, pp. 68–596.
[31] W. Lee and E. Afshari, “A CMOS noise-squeezing amplifier,” IEEE
Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp.
329–339, 2012.
[32] J. P. van Dijk, E. Kawakami, R. N. Schouten, M. Veldhorst, L. M.
Vandersypen, M. Babaie, E. Charbon, and F. Sebastiano, “The im-
pact of classical control electronics on qubit fidelity,” arXiv preprint
arXiv:1803.06176, Mar 2018.
[33] J. Ekin, Experimental techniques for low-temperature measurements:
cryostat design, material properties and superconductor critical-current
testing. Oxford university press, 2006.
[34] J. Chang, A. Abidi, and C. Viswanathan, “Flicker noise in CMOS tran-
sistors from subthreshold to strong inversion at various temperatures,”
IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 1965–1971,
Nov 1994.
[35] E. Green, “Temperature dependence of semi-
conductor conductivity,” 2014. [Online]. Available:
https://www.iiserkol.ac.in/ ph324/StudyMaterials/ResistivityTdep.pdf
[36] K. Hung, P. Ko, C. Hu, and Y. Cheng, “Flicker noise characteristics
of advanced mos technologies,” in Electron Devices Meeting, 1988.
IEDM’88. Technical Digest., International. IEEE, 1988, pp. 34–37.
[37] M. Shahmohammadi, M. Babaie, and R. B. Staszewski, “A 1/f noise
upconversion reduction technique for voltage-biased RF CMOS oscilla-
tors,” IEEE Journal of Solid-State Circuits, vol. 51, no. 11, pp. 2610–
2624, Nov 2016.
[38] D. Murphy, H. Darabi, and H. Wu, “Implicit common-mode resonance
in LC oscillators,” IEEE Journal of Solid-State Circuits, vol. 52, no. 3,
pp. 812–821, Mar 2017.
[39] R. B. Staszewski et al., “All-digital PLL and transmitter for mobile
phones,” IEEE journal of Solid-State circuits, vol. 40, no. 12, pp. 2469–
2482, Dec 2005.
[40] A. Elkholy, A. Elmallah, M. G. Ahmed, and P. K. Hanumolu, “A 6.75–
8.25-GHz 250-dB FoM rapid on/off fractional-N injection-locked clock
multiplier,” IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp.
1818–1829, Dec 2018.
[41] J. Gong, Y. He, A. Ba, Y.-H. Liu, J. Dijkhuis, S. Traferro, C. Bachmann,
K. Philips, and M. Babaie, “A 1.33 mW, 1.6 psrms -integrated-jitter,
1.8-2.7 GHz ring-oscillator-based fractional-N injection-locked DPLL
for internet-of-things applications,” in 2018 IEEE Radio Frequency
Integrated Circuits Symposium (RFIC), Jun 2018, pp. 44–47.