Sumator cu anticiparea transportului

entity sumator is
Port(cin : in STD_LOGIC;
cout: out STD_LOGIC;
s : out STD_LOGIC_VECTOR (7 downto 0);
op1 : in STD_LOGIC_VECTOR (7 downto 0);
op2 : in STD_LOGIC_VECTOR (7 downto 0)
);
end sumator;

architecture Behavioral of sumator is

component sumator_2b is
Port ( x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
cin : in STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC;
s : out STD_LOGIC_VECTOR(1 downto 0));
end component;

signal c2, c4, c6, c8: STD_LOGIC;

signal p1, g1, p2, g2, p3, g3, p4,g4: STD_LOGIC;

begin

sumator1 : sumator_2b port map(op1 (1 downto 0), op2 (1 downto 0),c1,p1,g1,s(1 downto 0));
tr11 : c2 <= g1 or (p1 and cin);
sumator2 : sumator_2b port map (op1 (3 downto 2), op2 (3 downto 0),c2,p2,g2,s (3 downto 2));
tr22 : c4 <= g2 or (p2 and c2);
sumator3 : sumator_2b port map (op1 (5 downto 3), op2 (5 downto 4),c4,p3,g3,s (5 downto 4));
tr33 : c6 <= g3 or (p3 and c4);
sumator4 : sumator_2b port map (op1 (7 downto 6), op2 (7 downto 6),c6,p4,g4,s(7 downto 6));
tr44 : c8 <= g4 or (p4 and c6);

end Behavioral;

Sumator 2b
entity sumator_2b is
Port ( x : in STD_LOGIC_VECTOR(1 downto 0);
y : in STD_LOGIC_VECTOR(1 downto 0);
cin:in STD_LOGIC;
p : out STD_LOGIC;
g : out STD_LOGIC;
s : out STD_LOGIC_VECTOR(1 downto 0));
end sumator_2b;

architecture Behavioral of sumator_2b is

begin

s <= x + y + cin;
g <= (x(1) and y(1)) or ((x(1) or y(1))and (x(0) and y(0)));
p <= (x(1) or y(1)) and (x(0) or y(0));

end Behavioral;

Sumator cu generare transport :

entity generare_anticipat is
Port ( P : in STD_LOGIC_VECTOR (3 downto 0);
G : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
C : out STD_LOGIC_VECTOR (3 downto 0));
end generare_anticipat;
architecture Behavioral of generare_anticipat is
begin
C(0)<=G(0) or (P(0)and cin);
C(1)<=G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND (G(0) or (P(0)and cin)));
C(2)<=G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1) AND P(0) AND (G(0) or (P(0)and cin)));
C(3)<=G(3) OR (P(3) AND G(2)) OR(P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND
P(0) AND (G(0) or (P(0)and cin)));
end Behavioral;

entity sum is
port(x: in std_logic_vector(1 downto 0);
y: in std_logic_vector(1 downto 0);
cin: in std_logic;
P:out std_logic;
G:out std_logic;
s: out std_logic_vector(1 downto 0));
end sum;
architecture Behavioral of sum is
signal c2:std_logic;
--signal carryout:std_logic;
signal p0,g0,p1,g1:std_logic;
begin
g0<=x(0) and y(0);
p0<=x(0) or y(0);
g1<=x(1) and y(1);
p1<=x(1) or y(1);
s(0)<=x(0) xor y(0) xor cin;
c2<=g0 or (p0 and cin);
s(1)<=x(1) xor y(1) xor c2;
G<=(g1 or (p1 and g0));
P<=(p1 and p0);
end Behavioral;

Inmultire matriciala
entity Inmultire is
generic (n:natural:= 4) ;
Port ( x: in std_logic_vector(n-1 downto 0);
y: in std_logic_vector(n-1 downto 0);
p: out std_logic_vector(n+3 downto 0));
end Inmultire;

architecture Behavioral of Inmultire is

component Sumator_elementar is

Port( in1: in std_logic;

in2: in std_logic;
tin: in std_logic;
sout: out std_logic;
tout: out std_logic);

end component Sumator_elementar;

type array4x4 is array(0 to 3) of std_logic_vector(3 downto 0);

type array4x5 is array(0 to 3) of std_logic_vector(4 downto 0);
signal pp:array4x4;
signal c,s:array4x5;

begin

gen1: for i in 0 to n-1 generate

gen2: for j in 0 to n-1 generate
pp(i)(j) <= x(i) and y(j);
end generate gen2;
end generate gen1;

gen3: for i in 0 to n-2 generate

c(i)(0)<='0';
end generate gen3;

gen4: for i in 0 to n-1 generate

s(0)(i)<= pp(0)(i);
end generate gen4;
s(0)(n)<= '0';

gen5: for i in 0 to n-2 generate

s(i+1)(4) <= c(i)(4);
end generate gen5;

gen6: for i in 0 to n-2 generate

gen7: for j in 0 to n-1 generate
sum: Sumator_elementar port map ( pp(i+1)(j), s(i)(j+1), c(i)(j), s(i+1)(j), c(i)(j+1));
end generate gen7;
end generate gen6;

produs: for i in 0 to n-1 generate

p(i)<= s(i)(0);
p(i+n)<= s(n-1)(i+1);
end generate;

end Behavioral;

Circuit de înmulţire secvenţială prin metoda deplasării şi adunării

pentru două numere fără semn

entity SE is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
tout : out STD_LOGIC);
end SE;
architecture Behavioral of SE is
begin
s<= a xor b xor tin;
tout<= (a and b ) or ((a or b)and tin);
end Behavioral;

entity ADDN is
generic (n: natural:=4);
Port ( A : in STD_LOGIC_VECTOR (n-1 downto 0);
B : in STD_LOGIC_VECTOR (n-1 downto 0);
CI : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (n-1 downto 0);
OFL : out STD_LOGIC;
 CO : out STD_LOGIC);
end ADDN;
architecture Behavioral of ADDN is
component se is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
tin : in STD_LOGIC;
s : out STD_LOGIC;
tout : out STD_LOGIC);
end component se;
signal T :STD_LOGIC_VECTOR (n downto 0);
begin
T(0)<=CI;
gen_sum: for i in 0 to n-1 generate
sum_elem: se port map (A(i),B(i),T(i),S(i),T(i+1));
end generate gen_sum;
CO<=T(n);
OFL<=T(n) xor T(n-1);
end Behavioral;

entity FDCEN is
generic(n:integer:=3);
port(clk: in std_logic;
rst:in std_logic;
ce:in std_logic;
d: in std_logic_vector(n downto 0);
q: out std_logic_vector(n downto 0));
end FDCEN;
architecture Behavioral of FDCEN is
signal qq: std_logic_vector(n downto 0):=(others=>'0');
begin
func: process(clk)
begin
if rising_edge(clk) then
if rst='1'
then qq<=(others=>'0');
else if ce='1'
then qq<=d;
end if;
end if;
end if;
end process func;
q<=qq;
end Behavioral;

entity SRCLEDN is
generic(n:integer:=3);
port(clk:in std_logic;
rst:in std_logic;
ce:in std_logic;
sli:in std_logic;
sri:in std_logic;
load:in std_logic;
left:in std_logic;
d: in std_logic_vector(n downto 0);
q: out std_logic_vector(n downto 0));
end SRCLEDN;

architecture Behavioral of SRCLEDN is

signal q1:std_logic_vector(n downto 0);

begin

proc: process(clk)
begin

if rising_edge(clk) then

if(rst='1')
then q1<=(others=>'0');
elsif load='1'
then q1<=d;
elsif ce='1'
then if left='0'
then q1(n)<=sri;
q1(n-1 downto 0)<=q1(n
downto 1);
else q1(0)<=sli;
q1(n downto 1)<=q1(n-1 downto 0);
end if;
end if;
end if;
end process proc;
q<=q1;
end Behavioral;

Detectie sir de biti :

entity detectie is
port (clk, rst: in std_logic;
input: in std_logic;
tact: in std_logic;
detectat: out std_logic);
end detectie;

architecture Behavioral of detectie is

type tip_stare is (init, prim, doi, trei,patru,cinci,sase,sapte,opt);
signal stare: tip_stare;
begin

detect: process(clk)
begin
if rising_edge (clk) then
if tact='1' then
if rst='1' then
stare<=init;
detectat<='1';
else

case stare is
when init =>
if input='1' then
 stare<=prim;
else stare<=init;
end if;

when prim => detectat<='0';

if input='1' then
stare<=doi;
else stare<=init;
end if;

when doi => detectat<='0';

if input='1' then
stare<=trei;
else stare<=init;
end if;
when trei => detectat<='0';
if input='1' then
stare<=trei;
else stare<=patru;
end if;
when patru => detectat<='0';
if input='1' then
stare<=cinci;
else stare<=init;
end if;
when cinci => detectat<='0';
if input='1' then
stare<=doi;
else stare<=sase;
end if;
when sapte => detectat<='0';
if input='1' then
stare<=opt;
else stare<=init;
end if;

when opt => detectat<='1';

stare<=init;
when sase => detectat<='0';
if input='1' then
stare<=sapte;
else stare<=init;
end if;

end case;
end if;
end if;
end if;
end process detect;
end Behavioral;

entity filtru is
port(clk,rst,d_in:in std_logic;
q_out:out std_logic);
end filtru;
architecture Behavioral of filtru is
signal Q1, Q2, Q3 : std_logic;
begin
--**Insert the following after the 'begin' keyword**
process(clk)
begin
if (clk'event and clk= '1') then
if (rst = '1') then
Q1 <= '0';
Q2 <= '0';
Q3 <= '0';
else
Q1 <= D_IN;
Q2 <= Q1;
Q3 <= Q2;
end if;
end if;
end process;
Q_OUT <= Q1 and Q2 and (not Q3);
end Behavioral;

Numarator sus

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:27:49 04/07/2014
-- Design Name:
-- Module Name: numarator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity numarator is
generic(
n: natural := 8);
port(
clk: in STD_LOGIC;
 rst: in STD_LOGIC;
nr: out STD_LOGIC_VECTOR(n-1 downto 0)
);
end numarator;

architecture Structural of numarator is

signal x, y: STD_LOGIC_VECTOR(0 to n-1);
component bistabil is
port(
clk: in STD_LOGIC;
rst: in STD_LOGIC;
D: in STD_LOGIC;
Q: out STD_LOGIC;
QN: out STD_LOGIC);
end component bistabil;

begin
b0: bistabil port map (clk, rst, x(0), y(0), x(0));
gen: for i in 1 to n-1 generate
bi: bistabil port map (y(i-1), rst, x(i), y(i), x(i));
end generate;
nr <= y;

end Structural;

Fifo 8x8

entity fifo8x8 is
port(CLK,RESET,rdinc,wrinc,WR,RD: in std_logic;
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);

end fifo8x8;

architecture Behavioral of fifo8x8 is

type fifo_array is array (7 downto 0) of std_logic_vector(7 downto 0);
signal wrptr: std_logic_vector(2 downto 0):="000";
signal rdptr: std_logic_vector(2 downto 0):="000";
signal dec_out: std_logic_vector(7 downto 0);
signal mux_in: fifo_array;
signal mux_out:std_logic_vector(7 downto 0);
signal en: std_logic_vector(7 downto 0);
begin

PointerScriere: process (CLK,RESET,WRINC)

begin
if (rising_edge(CLK)) then
if RESET='1' then
wrptr<="000";
elsif wrinc='1' then
wrptr<=wrptr+"001";
else
wrptr<=wrptr;
end if;
end if;

end process PointerScriere;

PointerCitire: process (CLK,RESET,RDINC)

 variable i:std_logic_vector(2 downto 0):=rdptr;
begin
if (rising_edge(CLK)) then
if RESET='1' then
rdptr<="000";
elsif rdinc='1' then
rdptr<=rdptr+"001";
else
rdptr<=rdptr;
end if;
end if;
end process PointerCitire;
Decodificator: process(wrptr)
begin
case wrptr is
when "000" => dec_out<="10000000";
when "001" => dec_out<=('0','1','0','0','0','0','0','0');
when "010" => dec_out<=('0','0','1','0','0','0','0','0');
when "011" => dec_out<=('0','0','0','1','0','0','0','0');
when "100" => dec_out<=('0','0','0','0','1','0','0','0');
when "101" => dec_out<=('0','0','0','0','0','1','0','0');
when "110" => dec_out<=('0','0','0','0','0','0','1','0');
when "111" => dec_out<=('0','0','0','0','0','0','0','1');
when others => dec_out<=('0','0','0','0','0','0','0','0');
end case;
end process Decodificator;

Enable: process(WR, dec_out)

begin
for i in integer range 0 to 7 loop
en(i)<=wr and dec_out(i);
end loop;
end process Enable;

Multiplexor: process(rdptr,mux_in)
--rdptr e selectul pt multiplexor
--mux_in e fifo
begin
mux_out<=mux_in(conv_integer(rdptr));
end process Multiplexor;
Buff: process(mux_out,RD)
begin
if (RD='1') then
data_out<=mux_out;
else data_out<=(others=>'Z');
end if;
end process Buff;
Registre: process(CLK,RESET,data_in)
begin
if (rising_edge(CLK)) then
if (RESET='1') then
for i in integer range 0 to 7 loop
mux_in(i) <= "00000000";
end loop;
else
 for i in integer range 0 to 7 loop
if en(i)='1' then
mux_in(i)<=data_in;
end if;
end loop;
end if;
end if;
end process Registre;
end Behavioral;