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Digital Logic Design Sequential Logic

Chapter 5: Sequential Circuits Design Logic That Remembers

Sequential Logic Sequential Logic Circuits

 Memory added to Combinational Logic  Classification
 Memory elements: Output is held in One of  Synchronous: External timing signal
Two Stable States determines output updates
 Latches  Asynchronous: Outputs are updated following
changes in state or inputs after propagation
 Flip Flops
delays
 Identified by the presence of Feedback  Structural Classification:
 Output depends on Inputs & State of the  Moore: Output only derived from Flip Flops
Circuit  Mealy: Output is combinational function of
Flip Flops and inputs

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Hazards and Sequential Logic Latches

 In synchronous sequential circuits, most of  Binary Storage Elements
the glitches that may occur do not cause  Asynchronous in nature: No Clock
problems because they occur in the part of  Types include SR and D
the clock cycle where they do not affect the  NOR and NAND implementations possible
flip-flops.
 However, in asynchronous sequential Set Reset Q Qbar
circuits changes occurring at any time can 1 0 1 0 Latch in Set Reset
Q

affect the signals on the feedback loops and

State
0 0 1 0
0 1 0 1 Reset State
cause the circuit to enter in an incorrect 0 0 0 1
of the Latch

state. 1 1 0 0 Next State

is
Set
Qbar

Undefined

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NAND Implementation of Latch The Clocked Latch

• A control input (called Clock) is added
– Output changes only when this input is HIGH
– Allows more control over the time when state changes
are required

Set Reset Q Qbar Clock Set Reset Q Qbar

Set
0 1 1 0 Latch in Set Set
Q 0 X X 1 0 No change: Q

State Previous state

1 1 1 0 1 0 0 1 0
held Clock
1 0 0 1 Reset State
1 0 1 0 1 Reset State
of the Latch
1 1 0 1 Set State Qbar
Qbar 1 1 0 1 0 Reset
0 0 1 1 Next State Reset
1 1 1 1 1 Undefined
is
Undefined

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

The D Latch D Latch Symbol

• Avoids ambiguous inputs En D Q Q

D Q
• Used as Data (D) storage device enabled by the 0
1
X
0
NC
0
NC
1
clock 1 1 1 0
En Q
• Also called a Transparent Latch NC: No Change
D
Clock D Q Q

0 X 0 No change:
Clock
1 0 0 Reset State
1 1 1 Set State
Qbar

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Latch is Transparent Transparency Property

 D Latch is called “transparent” or “level D Q
sensitive” Transparent
Latch
 Output follows input instantaneously
En
En

Latch acts like a Wire

D
D Q D Q
Q Storage Storage
Cell Cell

En En
Q

Transparent 0 1
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Problem of Transparency Problem of Transparency

D Q Other Logic
Circuits D Q D
Transparent
Transparent
Latch
Latch
En En
1
 A momentary input change tunnels through the latch En
and the entire circuitry
 What problem this can cause? D

Oscillating  Unstable Unstable

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Eliminating Transparency The Flip Flop

 Two ways to design F/F
 Construction Methods
 Master Slave
D Q D Q  Edge-Triggered
Transparent Transparent  Master Slave F/F
Latch Latch  Two Cascaded Latches and an Inverter
 First Latch is enabled during High time of the Clock
En En  Second Latch is enabled during Low time of Clock
 Edge Triggered Latch
Outputs can change only at the Transition of Clock
 Separating the input and output, so they are 
 Hi-to-Low (falling) and Low-to-High (rising) Edge
independently controlled
 Designed for Synchronous Logic
 Only open one gate at a time to avoid tunneling  Time Window for Data to Pass to the Output is Extremely
Short

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Flip-Flop (F/F) The Master-Slave SR Flip Flop

 Two Cascaded Latches and an Inverter
Input D1 Q1 D2 Q2 Output
 First Latch is enabled during High time of the
Clock
 Second Latch is enabled during Low time of
Clock
Enable (or clock) Set
Q Q

Clock

Qbar Qbar
Reset

Input 1-bit Output

Flip Flop

Enable
(or clock)
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Behavior of Master-Slave FF Behavior of Master-Slave FF

D Q D Q D1 Q1 D2 Q2 D1
Storage Storage
Cell Cell (0)

En 1 En 0 En En
En

D1
(initialized to1)

D Q D Q Q1=D2
Storage Storage
Cell (1) Cell
Q2

En 0 En 1
Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Behavior of Master-Slave FF Behavior of Master-Slave FF

D1 Q1 D2 Q2 D1 Q1 D2 Q2

En En En En

En En

D1 D1
(input) (input)

Q1=D2 Q1=D2

Q2 Q2

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

The JK Flip Flop The JK Flip Flop

• SR Flip Flop or Latch has One Prohibited input State • Two AND gates added to the SR FF
• JK overcomes the SR limitation of both inputs being – The current state of the FF allows the RIGHT input to
asserted simultaneously pass through
• The Behavior is described by the following Table
• Both J and K being TRUE cause a TOGGLE of the State

J K Next State J

0 0 Q
Q Q

0 1 0 Clock

1 0 1 Qbar Qbar

1 1 Q’
K

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D-type  Edge Triggered Flip Flop Flip Flops Symbols

 Cascade of a D and an SR Latch

D Q D Q

D D
SET
Q S
SET
Q Q
C Q C Q
CLR
Q R CLR
Q Q'

C Positive Edge Triggered Negative Edge Triggered

D Flip Flop D Flip Flop

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Important FF Parameters The Characteristic Table

 Setup Time: Minimum time that the input  Defines the Logical Properties of the Flip Flop
e.g. D must be present and stable before  Similar to the Truth Table for Combinational
the clock edge Circuits
 Hold Time: Minimum time that the input e.g.
D must be held stable after the clock edge S
0
R
0
Next State Q(t+1)
Q(t) Hold
J
0
K
0
Next State Q(t+1)
Q(t) Hold
 A violation of Setup or Hold Time will result in 0
1
1
0
0
1
Reset
Set
0
1
1
0
0
1
Reset
Set
unpredictable outputs 1 1 ? Undefined 1 1 Q’(t) Toggle

 Propagation Delay or Clock to Q delay:

 The time after the clock edge to the output D Next State Q(t+1) T Next State Q(t+1)
being stable in the new state 0 0 Reset 0 Q(t) Maintain state
1 1 Set 1 Q’(t) Toggle

Digital Logic Design Fall 2005 Lecture 14 Digital Logic Design Fall 2005 Lecture 14

Sequential Circuit Analysis State Table

 Label All Flip Flop Outputs (arbitrarily)
 Write Equations describing combinational  The table shows the present states, inputs, next
states and outputs
logic leading to all Flip Flop Inputs
 One Dimensional (present state and inputs
 Determine the FF Outputs from combined) Moore Model
Characteristic Table  Two Dimensional (present state left column
 Complete the State Table and inputs tabulated across the top) Mealy
 Present State: Inputs: Next State: Outputs Model
 Circuit with m FF and n inputs need 2m+n
entries in the State Table

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2-D State Table

A(t+1)
=DA = AX + BX

B(t+1)
=DB = AX

Y = AX + BX
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Sequential Circuit Analysis: Example

SET
J Q

K CLR
Q
A
A
X

SET
J Q

K CLR
Q
B
B
Clock

Digital Logic Design Fall 2005 Lecture 15 Digital Logic Design Fall 2005 Lecture 15

Sequential Circuit Analysis: Example State and State Diagram

 A state represents the machine snapshot at a given
1. Find the Flip Flop Input Equations clock period
J A  BX  B Y K A  B XY  A clock is typically used to synchronize the state
JB  AX K B  A  XY transition
2. Find the Output Equations  A graph consists of a set of
 Circles:
Z  AXY  BXY  Each represents a state
Use double circle to represent the initial state
Determine the Next State of the Flip Flops

3.  Directed arc: each represents a state transition
from Characteristic Tables  Inputs/outputs
4. Fill the State Table  Mealy machine:
 Label input/output along each arc
5. Draw the State Diagram  Moore machine:
 Label input along each arc
 Label output inside the circle (i.e. state)
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Mealy and Moore Machines State Diagrams

MEALY MACHINE MOORE MACHINE
a/q a
b
Inputs X(t) Outputs Z(t) Inputs X(t)

Combinational
Sk Sj Sk/p Sj/q
Combinational b/p a/q a
circuits circuits

b/p b
Storage Storage A Mealy machine example A Moore machine example
Element Element
S(t) S(t) Example:
Outputs Z(t) State: S(t) {Sk, Sj}
Inputs: X(t)  {a, b}
Z(t) = {S(t), X(t)} Z(t) = {S(t)} Outputs: Z(t) {p, q}
Output is dependent on state only Initial state: S(0) = Sk
Output is dependent on state and input

Digital Logic Design Fall 2005 Lecture 15 Digital Logic Design Fall 2005 Lecture 15

State Diagram Examples (Mealy) State Diagram Examples (Moore)

0/0 0

S0 S1 S0/1 S1/0
1/0 0/0 1 0
1/1 1

0/0 0

0/0, 1/1 S1 0, 1
S0 S0/0 S1/1

1/0 1

Digital Logic Design Fall 2005 Lecture 15 Digital Logic Design Fall 2005 Lecture 15

Design Example: Sequence Recognizer Sequence Recognizer

1, if X(t  3, t)  1101
 A sequential circuit that recognizes the Z(t)  
occurrence of a particular bit sequence 0, Otherwise
Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
 Input: X(t)  {0, 1} X(t) 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1
 Output: Z(t)  {0, 1} Z(t) 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1

1, if X(t  3, t)  1101

Z(t)  
0, Otherwise

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State Diagram & State Table

Sequence Recognizer
1, if X(t  3, t)  1101
Z(t)  
0, Otherwise
Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
X(t) 1 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1
Z(t) 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1

1/1

1/0 0/0
1/0
S0 S1 S2 S3

0/0 0/0 1/0

0/0
A Mealy Machine
Digital Logic Design Fall 2005 Lecture 16 Digital Logic Design Fall 2005 Lecture 16

State Table 1/1

1/0
1/0
00 01 10
0/0 0/0 1/0
0/0
Present State Input Next State
P1 P0 X N1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
Logic Circuits Design Steps
0/0
 Obtain state diagram or state table as requirement
11  Assign binary codes to states
 Generate a Boolean function for
 Each external output
Output  Each state encoded bit
N0 Z
 Simplify the Boolean functions
0 0
 Draw a D F/F (or register) for each state encoded bit
1 0
0 0  Draw logic circuits for
0 0  External outputs
1 0  Each inputs of state encoded bits
0 0  Input of state encoded bits = the next state
0 0  Output of state encoded bits = the current state
1 1

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Logic Circuits Design Logic Circuits Design

Present State Next State N1 N1  XP1P0  P1P0 Z  XP1P0
P1 P0 X N1 N0 Z P1P0 N0  X( P1  P0)  XP1P0
0 0 0 0 0 0
X 00 01 11 10

0 0 1 0 1 0 0 0 0 1
0 1 0 0 0 0
0
N1  XP1P0  P1P0 X
0 1 1 1 0 0 1 0 1 0 1
D0
1 0 0 1 1 0 F/F
N0 P0
1 0 1 1 0 0
1 1 0 0 0 0 N0 clk
P1P0
1 1 1 0 1 1
X 00 01 11 10 Z
0 0 0 0 1 N0  XP1P0  XP1P0  XP1P0
1 1 0 1 0  X( P1  P0 )  XP1P0 D1
N1 F/F P1

clk

Z  XP1P0

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Vending Machine State Machine State Diagram

 Dispense a Coke when depositing 15 ¢
 Inputs 5/N
BC/R
 5 = a nickel
 10 = a dime 0¢
10/C
5¢
BC/R
 BC = bad coin (including quarters in this 5/C
example) 10/C

 Outputs 10/N 5/N

10 ¢
 R = reject
 C = coke
BC/R
 N = no coke

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State Table Logic Circuits Design

Present State Input Next State (0¢, Output Present Input Next State Output
X1X0 N1
(0¢, 5¢, 10¢) 5¢, 10¢) State
5/N (5¢, 10¢ , BC) (C, N, R)
P1P0
00 01 11 10
BC/R P1 P0 X1 X0 N1 N0 C1 C0
P1 P0 X1 X0 N1 N0 C1 C0 0 1 X 0
00
0 0 0 0 0 1 0 0
0¢ 10/C 5¢ 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 01 1 0 X 0
(00) (01) 0 0 1 0 0 0 1 0
BC/R 0 0 0 1 1 0 0 0 X X X X
11
0 1 0 0 1 0 0 0
5/C 0 0 1 0 0 0 1 0 0 0 X 1
10/C 0 1 0 1 0 0 0 1 10

0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0
10/N 5/N 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 N1  P0 X 1X 0  P1P0X 0  P1X 1
10 ¢ 1 0 0 1 0 1 0 1
(10) 0 1 1 0 0 1 1 0 X1X0 N0
1 0 1 0 1 0 1 0
P1P0 00 01 11 10
1 0 0 0 0 0 0 1 X X 1 1 X X X X
00 1 0 X 0
BC/R 1 1 X X X X X X
1 0 0 1 0 1 0 1
01 0 0 X 1
1 0 1 0 1 0 1 0
5: 00 N: 00 11 X X X X
10: 01 C: 01
BC: 10 R: 10 10 0 1 X 0

N0  P1P0 X 1X 0  P1X 0  P0 X 1

Digital Logic Design Fall 2005 Lecture 18 Digital Logic Design Fall 2005 Lecture 18

Logic Circuits Design Logic Circuits for Vending Machine

Present Input Next State Output
X1X0 C1 N1  P0X1X0  P1P0X0  P1X1 C1  X1
State
P1 P0 X1 X0 N1 N0 C1 C0
P1P0
00 01 11 10
N0  P1P0X1X0  P1X0  P0X1 C0  P1X1  P0X0
00 0 0 X 1
0 0 0 0 0 1 0 0
X1 X0 P1 P0
0 0 0 1 1 0 0 0 01 0 0 X 1

0 0 1 0 0 0 1 0 X X X X
11
0 1 0 0 1 0 0 0 D0
0 0 X 1
0 1 0 1 0 0 0 1 10
N0 F/F P0
0 1 1 0 0 1 1 0
C1  X1 clk
1 0 0 0 0 0 0 1

1 0 0 1 0 1 0 1
X1X0 C0
1 0 1 0 1 0 1 0
P1P0 00 01 11 10 D1
X X 1 1 X X X X N1 F/F P1
00 0 0 X 0
1 1 X X X X X X
0 1 X 0 clk
01

11 X X X X
C0
10 1 1 X 0

C0  P1X1  P0X0 C1

Digital Logic Design Fall 2005 Lecture 18 Digital Logic Design Fall 2005 Lecture 18