A B C D E

1 1

LCFC Confidential
2 2

KENOBI NM-A821 Rev2.0 Schematic

Intel KabyLake Processor with DDR4 + PCH-LP

NVIDA N16V-GMR GDDR3 2GB
3 3

2016-08-24 Rev2.0

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 COVER PAGE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 1 of 82
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 A B C D E

Kenobi KBL U Block Diagram

GPU
Page 25~30 PCIe x 1
VRAM DDR5 PCIE x 4 NGFF Card WLAN
GDDR3 (PCIE Lane 1~4) Intel CPU (PCIE Lane 9)
Page 48
1
Page 31~32 NVIDIA Kabylake U USB 2.0 x 1
1

N16V-GMR1-S-A2
N16S-GTR-S-A2 15W (UM A& DIS) (Port 6) 802.11 a/b/g/n
DIS only (SWG) Kabylake PCH-LP BT V4.0 combo
10 USB 2.0/1.1 Ports
6 USB 3.0 Ports
DDR4 3 SATA Ports SATA x 1
12 PCIE Ports HDD
2133/2400 Mhz DDR4 2133/2400MHz Channel A Page42
SODIMM A HD Audio
LPC I/F
Page22
ACPI 3.0

DDR4
2133/2400 Mhz DDR4 2133/2400MHz Channel B
SODIMM B
Page23

Finger Print
USB 2.0 x 1 Page61
Touch Panel (Optional) (Port 9) WORLD FAIR
VAL1167
EDP x 2
15" LCD FHD/HD
USB 2.0 x 1
(Port 5) PCIe x 2 M2 Slot for SSD
(PCIE Lane11/12) Page42
2
2D Camera USB 2.0 x 1
2

DMIC_DATA
(Digital MIC) (Port 7)
DMIC_CLK

IR Camera USB 2.0 x 1

(Optional) (Port 8)

Page37

Card Reader DDI1 HDMI v1.4

PCIe x 1
Page49 Page36
Bayhub (PCIE Lane 5)
OZ621FJ1LN

USB Type-C PD
Right- Fr ont USB 3.0 x 1 Page54
(Port 4) Cypress
JUSB4 (USB3.0) CYPD3125
Page44 USB 2.0 x 1
(Port 4) I2C
Power Control
DDI2
Switch MUX
Right- Back Reserve USB 3.0 x 1 Page55
(Port 3) USB 3.0 x 1
3
JUSB3 (USB3.0) Parade Type C Conn. 3
Page44 PS8743
USB 2.0 x 1 (Port 1) Page55

(Port 3) USB 2.0 x 1

(Port 1)

AOU USB 3.0 x 1

LPC BUS I2C
(Port 2)
JUSB2 (USB2.0) USB charger (AOU)
Page45 USB 2.0 x 1
Page44
TI (Port 2)
TPS2546RTER

Thermal Sensor
RJ45 LAN 10/100/1000 SMBus Page62
PCIe x 1 Fintek
Conn. Page46
F75303M
Realtek (PCIE Lane 10) EC
Page47
R8111GUS Page57

PS2 Click Pad Track Point

ITE
IT8586EX Page63 Page63
MIC IN/GND
Combol Jack HP R/L BGA1356
Page53 40mm*24mm Mirror function SPI BUS Int. K/B Matrix I2C
Page 5~20

SPI BUS Flash ROM FAN Int. KB G-sensor

4M/8M Page61 Page60 Page59
4
Stereo Speaker (2CH 2W/4ohm) HDA Codec Page21
Fintek 4

Page51 HDA
LIS3DSHTR
Page52
CONEXANT
CX11852-11Z
TPM 1.2
Page58

Infineon
SLB9670VQ1.2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
A1 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 2 of 82

www.vinafix.com
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) SMBUS Control Table
Main BATT WLAN Thermal CP G USB
SOURCE VGA (Charger) SODIMM WiMAX Sensor PCH Module LAN PHY sensor Type-C
+5VS
Power Plane +3VS
+VCC_CORE EC_SMB_CK1 IT8580F
+VCC_IO EC_SMB_DA1 +3VL
X V X X X X X X X X
+3VALW
+VCC_SA
1
+3VALW 1

+VCC_ST EC_SMB_CK2 IT8580F

B+ +5VALW +2.5V +VGA_CORE EC_SMB_DA2 +3VL
X X X X X X X X X V
+3VPD_VDD
+3VS_VGA
+3VL +1VALW +1.2V
+1.5VS_VGA EC_SMB_CK3 IT8580F
State +1.8VALW +VCC_STG +3VS_AON EC_SMB_DA3 +3VS
V X X X V V X X V X
+3VS_VGA +3VS +3V_PCH +3VS_GS
+1VS_VGA
+0.6VS
PCH_SMB_CLK PCH
X X V X X X X
PCH_SMB_DATA
+3V_PCH +3VS V X X
+5VS

PCH_SML1CLK PCH
S0 O O O O PCH_SML1DAT X X X X X X X X X X
+3V_PCH

S3 O O O X BOM Structure Table

BOM Structure NOTE
2
S5 S4/AC Only O O X X 2

PCB@ For PCB load BOM

S5 S4 XDP@ Debug port
Battery only O X X X
UMA@ UMA SKU ID

S5 S4 DIS@ Optimus SKU ID

AC & Battery X X X X SSD@ SSD setting
don't exist
FRP@ Finger printer setting
TYPEC@ For USB Type-C function

SIGNAL
ME@ ME Connector
STATE SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON2 EC_ON SUSP# SYSON
EMC@ For EMC function
Full ON HIGH HIGH HIGH HIGH ON ON ON HIGH
EMC_2D@ For EMC function
S1(Power On Suspend) HIGH HIGH HIGH HIGH ON ON ON HIGH
EMC_NS@ For EMC function
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF HIGH
3
RF_NS@ For RF function 3

S4 (Suspend to Disk) LOW LOW LOW HIGH ON ON OFF LOW

S2G@ For VRAM Strap
S5 (Soft OFF) LOW LOW LOW LOW ON ON OFF LOW
CHA@ For VRAMA function
CHB@ For VRAMB function
USB2 Port USB3 Port PCIE Port SATA Port RANKA@ GPU DDR5 Setting
X76@ GPU VRAM Setting
Port Device Port Device Port Device Port Device
3DCCD@ 3D Camera Setting
1 JUSB1 TYPE-C 1 JUSB1 TYPE-C 1 GPU 1 HDD
VGA@ VGA Setting
2 JUSB2 2 JUSB2 2 GPU 2 X
3 JUSB3 3 JUSB3 3 GPU 3 X MUX@ MUX Setting
4 JUSB4 4 JUSB4 4 GPU 4 X
ODD@ ODD Setting
5 Touch Panel 5 CardReader
6 BT 6 X TPM@ Trusted Platform Module (TPM)
7 CMOS 7 X
MIRROR@ For mirror function
4 8 IR CAMERA 8 X 4

9 FP/Smart 9 WLAN NGC6@ For VGA Non GC6 function

10 LAN
GC6@ For VGA GC6 function
11 M.2 SSD
12 M.2 SSD
Security Classification LC Future Center Secret Data Title
Issued Date 2015/10/5 Deciphered Date 2016/12/31 NOTE LIST
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 3 of 82
A B C D E
 5 4 3 2 1

[KENOBI PWR Sequence_SKL-U_DDR4_Non-Deep Sx]

[AC Mode] [DC Mode]

D
BATT+ D

AC_IN
170mS AC_PRESENT

B+
B+
9mS +3VLP/+VL
+3VLP/+VL 200uS
ON/OFFBTN#
MAINPWON_EC
EN_5V/EN_3V T=10ms Moniter ON/OFFBTN#
moniter AC_IN (51_ON)
+5VALW/+3VALW
EC_ON
Min:50nS PCH_PWR_EN moniter EN_3V
+3VALW
+1VALW/+1.8VALW
3V5V_ON
Min:50nS
+5VALW EC_RSMRST# T=10ms Moniter ON/OFFBTN# and EN_3/5V both of risgin edge
15mS
SUSPWRDNACK
EC_ON2
Min:60nS
PBTN_OUT# 20ms T=110ms Moniter ON/OFFBTN# rising edge
+1VALW/+1.8VALW

ON/OFFBTN# 415mS
Moniter ON/OFFBTN# rising edge
PBTN_OUT# 95~100mS 20ms
20mS
EC_RSMRST#

SUSPWRDNACK
C C

AC_PRESENT

PM_SLP_S5# Montier PBTN_OUT# falling edge.

PM_SLP_S4#

PM_SLP_S3#

SYSON

+1.2V

DDR_PG_CTRL immediately, After PM_SLP_S4# falling edge

+0.6VS

SUSP# T=20ms After PM_SLP_S3# moniter SYSON rising edge. immediately, After PM_SLP_S3# falling edge

+5VS

+3VS

+1.5VS

B B

VCCST_PG_EC (ALL_SYS_PWRGD,non CPU code VR) T=20ms After SUSP# risign edge immediately, After SUSP# falling edge

VR_ON immediately, VCCST_PG_PWR & VCCST_PG_EC risign edge

+VCC_CORE Vboot

VGATE

PCH_PWROK T=10ms After VCCST_PG_EC rising edge immediately, After SUSP# falling edge

H_CPUPWRGD_R

SYS_PWROK T=99ms After VCCST_PG_EC assertion immediately, After SUSP# falling edge

PLT_RST#

After CPUPWRGD/PCH_PWRGD/SYS_PWROK assertion

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 Power Sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 4 of 82
5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1A

PCH_HDMI_TX2- E55 C47 CPU_EDP_TX0-

[36] PCH_HDMI_TX2- PCH_HDMI_TX2+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- [37]
F55 C46
[36] PCH_HDMI_TX2+ PCH_HDMI_TX1- DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX1- CPU_EDP_TX0+ [37]
E58 D46
HDMI
[36] PCH_HDMI_TX1- PCH_HDMI_TX1+ F58 DDI1_TXN[1] EDP_TXN[1] C45 CPU_EDP_TX1+ CPU_EDP_TX1- [37] EDP
[36] PCH_HDMI_TX1+ PCH_HDMI_TX0- DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ [37]
F53 EDP A45
[36] PCH_HDMI_TX0- PCH_HDMI_TX0+ DDI1_TXN[2] EDP_TXN[2]
G53 B45
[36] PCH_HDMI_TX0+ PCH_HDMI_TXC- DDI1_TXP[2] EDP_TXP[2]
F56 A47
[36] PCH_HDMI_TXC- PCH_HDMI_TXC+ DDI1_TXN[3] EDP_TXN[3]
G56 B47
[36] PCH_HDMI_TXC+ DDI1_TXP[3] EDP_TXP[3]
DDI2_MUX_TX0- C50 E45 CPU_EDP_AUX#
[55] DDI2_MUX_TX0- DDI2_MUX_TX0+ DDI2_TXN[0] DDI EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# [37]
D50 EDP F45 CPU_EDP_AUX [37]
[55] DDI2_MUX_TX0+ DDI2_MUX_TX1- DDI2_TXP[0] EDP_AUXP
C52
[55] DDI2_MUX_TX1- DDI2_MUX_TX1+ DDI2_TXN[1]
D52 B52
[55] DDI2_MUX_TX1+ DDI2_MUX_TX2- DDI2_TXP[1] EDP_DISP_UTIL
A50
[55] DDI2_MUX_TX2- DDI2_MUX_TX2+ DDI2_TXN[2]
USB TYPE C [55] DDI2_MUX_TX2+
B50
DDI2_TXP[2] DDI1_AUXN
G50
DDI2_MUX_TX3- D51 F50
[55] DDI2_MUX_TX3- DDI2_MUX_TX3+ DDI2_TXN[3] DDI1_AUXP DDI2_MUX_AUX#
C51 E48
[55] DDI2_MUX_TX3+ DDI2_TXP[3] DDI2_AUXN DDI2_MUX_AUX DDI2_MUX_AUX# [55]
F48
DDI2_AUXP DDI2_MUX_AUX [55]
G46
DISPLAY SIDEBANDS DDI3_AUXN F46
HDMI_CLK L13 DDI3_AUXP
[36] HDMI_CLK HDMI_DAT GPP_E18/DDPB_CTRLCLK HDMI_HPD
[36] HDMI_DAT L12 L9 HDMI_HPD [36]
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 PCH_MUX_HPD
GPP_E14/DDPC_HPD1 PCH_MUX_HPD [54,55]
PCH_MUX_CLK N7 L6
PCH_MUX_DAT N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD [37]
+VCC_IO N11
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_EDP_PWM ENBKL [57]
R11
EDP_COMP E52 EDP_BKLTCTL PCH_ENVDD PCH_EDP_PWM [37]
RC1 1 2 24.9_0402_1% U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [37]
C C
[SKL PDG]EDP_RCOMP Pull up to VCCIO via 24.9 ohm resistor SKYLAKE-U_BGA1356 1 OF 20 ? ?
REV = 1
[SKL PDG]EDP_RCOMP @
1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC1 close to MCP

DDPB_CTRLDATA, DDPC_CTRLDATA Internal PD 20K

ENBKL RC2 1 2 100K_0402_5%

+3VS CPU_EDP_HPD RC3 1 2 100K_0402_5%

[SKL PDG]EDP_HPD Pull down to ground via

RC4 1 @ 2 2.2K_0402_5% PCH_MUX_CLK 100k ohm resistor
PCH_MUX_HPD RC5 1 2 100K_0402_5%
RC6 1 2 2.2K_0402_5% PCH_MUX_DAT TYPEC_NS@

RC7 1 2 3.3K_0402_5% HDMI_CLK

RC8 1 2 3.3K_0402_5% HDMI_DAT

20160824
20160218 Change RC5 from @ to TYPEC_NS@
B Staff RC7/RC8 for HDMI detect issue B
(Only for Non Type-C SKU)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(1/16):DDI/EDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 5 of 82
5 4 3 2 1
 5 4 3 2 1

+VCC_STG +VCC_ST +VCC_ST

D D
[SKL PDG]1 K pull- up
THRMTRIP# RC10 2 1 1K_0402_1% to VCCST

1
RC11
1K_0402_5% RC213
1K_0402_5%
@

2
UC1D SKL_ULT

2
+VCC_STG
TC1 1 D63
H_PECI A54 CATERR#
[57] H_PECI VR_HOT# VR_HOT#_R PECI
[57,67,70] VR_HOT# RC13 1 2 499_0402_1% C65 JTAG
1H_THERMTRIP# RC12 1 @ 2 0_0402_5% THRMTRIP# C63 PROCHOT#
TC30 THERMTRIP# XDP_TCLK XDP_TDI
A65 B61 RC14 1 @ 2 51_0402_5%
SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat 1 XDP_BPM#0 C55 A61 XDP_TDO XDP_TMS RC15 1 @ 2 51_0402_5%
condition, and the PCH will immediately transition to an S5 state. CPU_GP can TC2 XDP_BPM#1 BPM#[0] PROC_TDO XDP_TMS
TC3 1 D55 C60
be used from external sensors for the thermal management.
1 XDP_BPM#2 B54 BPM#[1] PROC_TMS B59 XDP_TRST# PCH_JTAG_TDI RC16 1 @ 2 51_0402_5%
TC4 XDP_BPM#3 BPM#[2] PROC_TRST#
TC5 1 C56
BPM#[3] B56 PCH_JTAG_TCK PCH_JTAG_TMS RC17 1 @ 2 51_0402_5%
EC_WAKE# 1 2 EC_WAKE#_L A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI
[57] EC_WAKE# RC18 0_0402_5% A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDO RC19 1 2 100_0402_5%
@ BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST# XDP_TDO RC20 1 @ 2 100_0402_5%
GPP_B4/CPU_GP3 PCH_TRST# A59 PCH_JTAGX
RC21 1 2 49.9_0402_1% PROC_POPIRCOMP AT16 JTAGX PCH_JTAGX RC22 1 @ 2 1K_0402_5%
RC23 1 2 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP
RC24 1 2 49.9_0402_1% OPCE_RCOMP H66 PCH_OPIRCOMP 20160119
RC25 1 2 49.9_0402_1% OPC_RCOMP H65 OPCE_RCOMP Unmount RC16,RC17,RC20
OPC_RCOMP
20160525
C
SKYLAKE-U_BGA1356 ? 4 OF 20 ?
Change RC19/RC20 to100 ohm C
REV = 1 for PROC_TDO termination
@

[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm
∮ 1 %. XDP_TCLK RC26 1 2 51_0402_5%
[SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm
∮ 1 %. XDP_TRST# RC27 1 @ 2 51_0402_5%
[SKL PDG]On Package Interface Compensation (OPI) Guidelines
Should be referenced to VSS plane only. VSS reference planes must be continuous PCH_JTAG_TCK RC28 1 @ 2 51_0402_5%
Require low DC resistance routing <0.2 ohm
Avoid routing next to clock pins or noisy signals.

Termination option

XDP_TCLK PCH_JTAGX
XDP_TCLK
RC29 1 DCI@ 2 0_0402_5%
PROC_TCK Termination:
XDP_TDI RC30 1 DCI@ 2 0_0402_5% PCH_JTAG_TDI 51 ohm +/- 5% pull down to GNG (Ground)
Placed to within 200ps (1100 mil) or PROC_TCK pin
XDP_TDO RC31 1 DCI@ 2 0_0402_5% PCH_JTAG_TDO

XDP_TMS RC32 1 DCI@ 2 0_0402_5% PCH_JTAG_TMS

PCH_JTAG_TDO
XDP_TRST# RC33 1 DCI@ 2 0_0402_5% PCH_JTAG_TRST# PCH_JTAG_TDO Termination:
51ohm +/- 5% pull up to VccSTG or equivalent.
Placed to within 200ps (1100 mil) or PCH_JTAG_TDO pin

Close to UC1
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(2/16):MISC/JTAG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 6 of 82
5 4 3 2 1
 5 4 3 2 1

D D

DDR_A_MA0 DDR_A_MA[0..16] [22]

DDR_A_MA1
SKL_ULT DDR_A_MA2
UC1B
[22] DDR_A_D[63..0] DDR_A_MA3
AU53 DDR_A_DDRCLK0_1866M# DDR_A_MA4
DDR_A_D0 DDR0_CKN[0] DDR_A_DDRCLK0_1866M DDR_A_DDRCLK0_1866M# [22] DDR_A_MA5
AL71 AT53
DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] DDR_A_DDRCLK1_1866M# DDR_A_DDRCLK0_1866M [22] DDR_A_MA6
AL68 AU55
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] DDR_A_DDRCLK1_1866M DDR_A_DDRCLK1_1866M# [22] DDR_A_MA7
AN68 AT55
DDR_A_D3 DDR0_DQ[2] DDR0_CKP[1] DDR_A_DDRCLK1_1866M [22] DDR_A_MA8
AN69
DDR_A_D4 AL70 DDR0_DQ[3] BA56 DDR_A_CKE0 DDR_A_MA9
DDR_A_D5 DDR0_DQ[4] DDR0_CKE[0] DDR_A_CKE1 DDR_A_CKE0 [22] DDR_A_MA10
AL69 BB56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] DDR_A_CKE1 [22] DDR_A_MA11
AN70 AW56
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_A_MA12
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3] DDR_A_MA13
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS0# DDR_A_MA14
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS1# DDR_A_CS0# [22] DDR_A_MA15
AU71 AU43
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[1] DDR_A_ODT0 DDR_A_CS1# [22] DDR_A_MA16
AU68 AT45
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 [22]
AR71 AT43
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[1] DDR_A_ODT1 [22]
AR69
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9
DDR_A_D16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6
DDR_A_D17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR_A_MA8 DDR_A_DQS#0 DDR_A_DQS#[0..7] [22]
AW65 AY52
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 DDR_A_DQS#1
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_A_DQS#2
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 [22] DDR_A_DQS#3
BA65 AW54
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_A_DQS#4
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT_N DDR_A_DQS#5
C DDR_A_D23 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR_A_BG1 DDR_A_ACT_N [22] DDR_A_DQS#6 C
BB63 AY54
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_BG1 [22] DDR_A_DQS#7
BA61
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_DQS0 DDR_A_DQS[0..7] [22]
AY61 AU52
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BA0 [22] DDR_A_DQS1
BA59 AY51
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
? AT48 DDR_A_BA1 DDR_A_DQS2
DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BA1 [22] DDR_A_DQS3
AY39 AT50
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_A_DQS4
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_A_DQS5
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_A_DQS6
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 DDR_A_DQS7
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4]
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4
DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_A_ALERT_N
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# DDR_A_PARITY DDR_A_ALERT_N [22]
AY27 AT52
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_A_PARITY [22]
B AW27 B
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 DDR4_VREF_CA_CPU_A
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA DDR4_VREF_DQ_CPU_A DDR4_VREF_CA_CPU_A [22]
AW25 AY68 1 TC31
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 DDR4_VREF_DQ_CPU_B
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR4_VREF_DQ_CPU_B [23]
BA27
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356 2 OF 20 ?
REV = 1 +1.2V
@

+3VALW +3VS

2
UC2 RC34 RC214
1 6 100K_0402_5% 100K_0402_5%
NC1 Vcc @
DDR_PG_CTRL 2 5
A NC2

1
3 4
GND Y SM_PG_CTRL [69]
74AUP1G07GF_SOT891-6_1X1
1
CC1
0.1U_0402_10V7-K
2

20160118
Reserve RC214 for leakage issue
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(3/16):DDR4 CH.A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 7 of 82
5 4 3 2 1
 5 4 3 2 1

D D

[23] DDR_B_D[0..63] SKL_ULT DDR_B_MA[0..16] [23]

UC1C DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_D0 AF65 AN45 DDR_B_DDRCLK0_1866M# DDR_B_MA3
DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] DDR_B_DDRCLK1_1866M# DDR_B_DDRCLK0_1866M# [23] DDR_B_MA4
AF64 AN46
DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_DDRCLK0_1866M DDR_B_DDRCLK1_1866M# [23] DDR_B_MA5
AK65 AP45
DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] DDR_B_DDRCLK1_1866M DDR_B_DDRCLK0_1866M [23] DDR_B_MA6
AK64 AP46
DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_DDRCLK1_1866M [23] DDR_B_MA7
AF66
DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0 DDR_B_MA8
DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 [23] DDR_B_MA9
AK67 AP55
DDR_B_D7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDR_B_CKE1 [23] DDR_B_MA10
AK66 AN55
DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53 DDR_B_MA11
DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_MA12
DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS0# DDR_B_MA13
DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDR_B_CS1# DDR_B_CS0# [23] DDR_B_MA14
AH68 AY42
DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS1# [23] DDR_B_MA15
AF71 BA42
DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDR_B_ODT1 DDR_B_ODT0 [23] DDR_B_MA16
AF69 AW42
DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 [23]
AH70
DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
DDR_B_D16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_B_D18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_DQS#0 DDR_B_DQS#[0..7] [23]
AP65 BB48
DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 DDR_B_DQS#1
C DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BG0 DDR_B_DQS#2 C
DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_MA12 DDR_B_BG0 [23] DDR_B_DQS#3
AP66 AN50
DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11 DDR_B_DQS#4
DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT_N DDR_B_DQS#5
DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 DDR_B_ACT_N [23] DDR_B_DQS#6
AT61 AN52
DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_BG1 [23] DDR_B_DQS#7
AU61
DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_MA15
DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_MA16
DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BA0 DDR_B_DQS0 DDR_B_DQS[0..7] [23]
AT60 BB44
DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BA0 [23] DDR_B_DQS1
AU60 ? AY47
DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BA1 DDR_B_DQS2
DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10 DDR_B_BA1 [23] DDR_B_DQS3
AT40 AW46
DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1 DDR_B_DQS4
DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0 DDR_B_DQS5
DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3 DDR_B_DQS6
DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4 DDR_B_DQS7
DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1
DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1
DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2
DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3
DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4 +1.2V
DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D52 DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6

2
AP27 AR27
DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7 RC35
DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
B
DDR1_DQ[54] DDR1_DQSP[7] 470_0402_5% B
DDR_B_D55 AP25
DDR_B_D56 AT22 DDR1_DQ[55] AN43 DDR_B_ALERT_N
DDR1_DQ[56] DDR1_ALERT# DDR_B_ALERT_N [23]

1
DDR_B_D57 AU22 AP43 DDR_B_PARITY
DDR_B_D58 DDR1_DQ[57] DDR1_PAR DDR4_DRAMRST_N DDR_B_PARITY [23] DDR4_DRAMRST_N
AU21 AT13 1 2
DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 DDR4_DRAMRST# [22,23]
AT21 AR18 RC36 1 2 121_0402_1% RC37 0_0402_5%
DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1 RC38 1 2 80.6_0402_1% @
DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP2 RC39 1 2 100_0402_1%
DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 3 OF 20 ?
[KBL PDG]for DDR4 COMPENSATION
REV = 1 DDR_RCOMP[0] Pull down 121 ohm resistor
@ DDR_RCOMP[1] Pull down 80.6 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(4/16):DDR4 CH.B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 8 of 82
5 4 3 2 1
 5 4 3 2 1

D D

[KBL PDG]Manufacturing Mode Jumper

1. If strap is sampled low, the security measures defined in
the Flash Descriptor will be in effect (default) 20160408
2. If sampled high, the Flash Descriptor Security will be overridden. 1.Unstaff RC188 and Staff RC211 with 100K resistor

PCH_HDA_RST# RC198 1 2 33_0402_5% HDA_RST#

[51] PCH_HDA_RST# PCH_HDA_BCLK RC199 1 2 33_0402_5% HDA_BCLK +3VS 1 2 DGPU_HOLD_RST#
[51] PCH_HDA_BCLK PCH_HDA_SDOUT RC200 1 2 33_0402_5% HDA_SDOUT RC211 100K_0402_5%
[51] PCH_HDA_SDOUT PCH_HDA_SYNC RC201 1 2 33_0402_5% HDA_SYNC
[51] PCH_HDA_SYNC
1 @ 2 VGA_APWR_ON
1 RC210 10K_0402_5%
CC185 1 @ 2 DGPU_HOLD_RST#
10P_0402_50V8-J EMC_NS@ RC188 10K_0402_5%
1 2
2 [57] ME_FLASH
1 2 VGA_APWR_ON
RC40 RC187 10K_0402_5%
Place RC183.184.185.186 close together 0_0402_5% Reserve PD by NV suggestion

UC1G SKL_ULT

AUDIO
Note: HDA_SYNC BA22
SPKR (PC_BEEP) has an integrated weak pull-down resistor (20 HDA_BCLK AY22 HDA_SYNC/I2S0_SFRM
C K ohm nominal) to disable Top-Block Sway by default. HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK C
SDIO/SDXC
PCH_HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
[51] PCH_HDA_SDIN0 HDA_SDI0/I2S0_RXD
To enable Top-Block Swap, this signal should be pulled up AY21 AB11
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
to V3.3S through a 1k to 2.2 Kohm ∮ 5% resistor. +3VS [28] GC6_FB_EN_GPIO J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
PCH_BEEP RC41 1 @ 2 2.2K_0402_5% AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
VGA_APWR_ON RC208 2 1 0_0402_5% VGA_APWR_ON_R H5 AB7
[33,75] VGA_APWR_ON DGPU_HOLD_RST# GPP_D19/DMIC_CLK0 SD_RCOMP
Note: D7
[28] DGPU_HOLD_RST# GPP_D20/DMIC_DATA0
Internal PD 20K D8 AF13
+VCC_IO C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
PCH_BEEP AW5
[52] PCH_BEEP GPP_B14/SPKR
PCH_HDA_SDIN0 RC44 1 @ 2 1K_0402_5%

SKYLAKE-U_BGA1356 7 OF 20 ? ?
REV = 1
@ [SKL PDG] internal SD Card

Not support internal SD card. Remove SD_RCOMP

Note:
B
HDA_SDO should only be asserted high via B
external pull-up to 3.3A rail in manufacturing/debug
environments ONLY. +VCC_HDA

HDA_SDOUT RC46 1 @ 2 1K_0402_5%

Note:
Internal PD 20K
+3VALW_PCH

HDA_SYNC RC48 1 @ 2 20K_0402_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(5/16):HDA/SDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 9 of 82
5 4 3 2 1
 5 4 3 2 1

RTC External Circuit

+RTCBATT, +RTCVCC
Trace width = 20mils JCMOS, JME Setting, Need Under DDR Door
+RTCBATT +RTCVCC +RTCVCC

D JCMOS1 @ D
1 2 1 2 PCH_RTCRST# 1 2
RC49 0_0402_5%
@ RC50
20K_0402_5% CC3 1 2 1U_0402_10V6K
1 1
CC4 CC5 JME1 @
1U_0402_10V6-K 0.1U_0402_10V6-K 1 2 PCH_SRTCRST# 1 2
2 2
RC51
20K_0402_5% CC6 1 2 1U_0402_10V6K

UC1J SKL_ULT
+3VS
CLOCK SIGNALS
RC53
10K_0402_5% D42
C42 CLKOUT_PCIE_N0
1 2 CLKREQ_PCIE4_VGA# AR10 CLKOUT_PCIE_P0
GPP_B5/SRCCLKREQ0#
CLK_PCIE_SSD# B42
[42] CLK_PCIE_SSD# CLK_PCIE_SSD CLKOUT_PCIE_N1
A42 F43
[42] CLK_PCIE_SSD CLKREQ#_PCIE1_SSD CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
1 @ 2 M.2 SSD [42] CLKREQ#_PCIE1_SSD AT7 E43
C GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P C
RC55 CLK_PCIE_WLAN# D41 BA17 SUSCLK_32K
[48] CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_32K [48]
10K_0402_5% C41
[48] CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN# CLKOUT_PCIE_P2 PCH_XTAL24_IN
WLAN [48] CLKREQ_PCIE2_WLAN# AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 PCH_XTAL24_OUT +1VALW
CLK_PCIE_LAN# D40 XTAL24_OUT
[46] CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N3 DIFFCLK_BIASREF
C40 E42 1 2
[46] CLK_PCIE_LAN CLKREQ_PCIE3_LAN# CLKOUT_PCIE_P3 XCLK_BIASREF
LAN [46] CLKREQ_PCIE3_LAN# AT10
GPP_B8/SRCCLKREQ3# AM18 PCH_RTCX1 RC56
CLK_PCIE_VGA# B40 RTCX1 AM20 PCH_RTCX2 2.7K_0402_1%
[25] CLK_PCIE_VGA# CLK_PCIE_VGA CLKOUT_PCIE_N4 RTCX2
+3VS A40
[25] CLK_PCIE_VGA CLKREQ_PCIE4_VGA# CLKOUT_PCIE_P4 PCH_SRTCRST#
VGA [25] CLKREQ_PCIE4_VGA# AU8 AN18
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 PCH_RTCRST#
RC176 CLK_PCIE_CR# E40 RTCRST#
10K_0402_5% [49] CLK_PCIE_CR# CLK_PCIE_CR CLKOUT_PCIE_N5
CR E38
CLKREQ_PCIE2_WLAN# [49] CLK_PCIE_CR CLKREQ_PCIE5_CR# CLKOUT_PCIE_P5
1 2 [49] CLKREQ_PCIE5_CR# AU7
RC177 GPP_B10/SRCCLKREQ5#
10K_0402_5%
1 2 CLKREQ_PCIE3_LAN# [SKL PDG]External pull-up resistor required if
RC178
10K_0402_5%
used for CLKREQ# functionality. SKYLAKE-U_BGA1356 10 OF 20 ? ?
1 2 CLKREQ_PCIE5_CR# REV = 1
RC209 @
10K_0402_5%
1 2 CLKREQ#_PCIE1_SSD

Place RC176,177,178,209 close together

[SKL PDG] [SKL PDG]

B
1.Space > 15mils 1.A 24 MHz crystal with crystal frequency tolerance and stability of +/ -30 ppm B
2.No trace under crystal 2.Two External Load Capacitors (Ce1 and Ce2)
3.Place on oppsosit side of MCP for temp inf l uence 3.A 1-Mohm bias resistor (Rf)
4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat i ons.
Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.
PCH_RTCX1 PCH_XTAL24_IN

1 2 PCH_RTCX2 PCH_XTAL24_OUT 1 2
RTC Crystal RC57 RC58
10M_0402_5% 1M_0402_5%

1 2 [SKL PDG]Max Crystal ESR = 50k Ohm. 1 3

1 3
YC1 GND1 GND2
32.768KHZ_12.5PF_9H03200042 YC2
2 4 24MHZ_10PF_8Y24000011
1 1 1 1
CC7 CC8 CC9 CC10
6.8P_0402_50V8-D 6.8P_0402_50V8-D 12P_0402_50V8-J 12P_0402_50V8-J
2 2 2 2

A A
20160127
Change CC7/CC8 to 6.8p by vender suggestion

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(6/16):CLOCK SIGNALS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 10 of 82
5 4 3 2 1
 5 4 3 2 1

Functional Strap Definitions

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality).

*H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher
D D
suite (with confidentiality).Support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.

+3VALW_PCH

SMBALERT# 1 2
RC59 1K_0402_5%

GPP_C2, Internal PD 20K SKL_ULT

UC1E
close to CPU SPI - FLASH
SMBUS, SMLINK
SPI_CLK AV2 R7 PCH_SMB_CLK
[21,58] SPI_CLK SPI_SO SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
AW3 R8 DIMM1, DIMM2, Security EEPROM, Click Pad
[21,58] SPI_SO SPI_SI SPI0_MISO GPP_C1/SMBDATA
AV3 R10 SMBALERT#
[21,58] SPI_SI SPI_IO2 SPI0_MOSI GPP_C2/SMBALERT#
AW2
[21] SPI_IO2 SPI_IO3 SPI0_IO2
AU4 R9
[21] SPI_IO3 SPI_CS0#_8MB SPI0_IO3 GPP_C3/SML0CLK
[21] SPI_CS0#_8MB AU3 W2
SPI_CS1#_4MB AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0ALERT#
JTAG ODT [21] SPI_CS1#_4MB SPI0_CS1# GPP_C5/SML0ALERT#
SPI_CS2#_TPM AU1
[58] SPI_CS2#_TPM SPI0_CS2#
+3VALW_PCH W3 PCH_SML1CLK
GPP_C6/SML1CLK V3 PCH_SML1DATA
SPI - TOUCH GPP_C7/SML1DATA AM7 SML1ALERT#
EC,dGPU,Thermal Sensor
M2 GPP_B23/SML1ALERT#/PCHHOT#
SPI_SI 1 @ 2 M3 GPP_D1/SPI1_CLK
SPI0_MOSI GPP_D2/SPI1_MISO
RC62 8.2K_0402_5% J4
RC107 1 2 0_0402_5% All_GPU_PWRGD_R V1 GPP_D3/SPI1_MOSI
[25] All_GPU_PWRGD GPU_EVENT# GPP_D21/SPI1_IO2
[28] GPU_EVENT# V2
EC_SCI# M1 GPP_D22/SPI1_IO3 AY13
[57] EC_SCI# LPC
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [57]
BA13
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [57]
BB13
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 [57]
AY12 RC63
C GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [57] C
G3 BA12 0_0402_5%
[48] CL_CLK_WLAN CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT# LPC_FRAME# [57]
G2 BA11 1 @ 2 1
[48] CL_DATA_WLAN CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC7
[48] CL_RST_WLAN# G1
CL_RST#
+3VALW_PCH AW9 PCH_PCI_CLK_R 1 EMC@ 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC [57]
KBRST# AW13 AY9
[57] KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# RC64
SERIRQ AY11 GPP_A8/CLKRUN# +3VS 22_0402_5%
1 [57,58] SERIRQ GPP_A6/SERIRQ
SPI_SO 1 @ 2 CC183 RC66 1
RC65 8.2K_0402_5% 10P_0402_50V8-J EMC_NS@ 8.2K_0402_5% CC184
SKYLAKE-U_BGA1356 5 OF 20 ? ? 1 2 10P_0402_50V8-J EMC_NS@
2 REV = 1
2
@

Close to UC1

GPP_C5, Internal PD 20K

*L: LPC
H: eSPI +3VALW_PCH

SML0ALERT# 1 @ 2
RC67 1K_0402_5%

B B

SB00000YS00 SB00000YS00
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
+3VS +3VALW_PCH QC1A QC2A
Place RC179,180,181 close together PCH_SMB_CLK 6 1 +3VS PCH_SML1CLK 6 1
CP_SMB_CLK [22,23,63] EC_SMB_CK3 [28,57,59,62]

D
S

S
RC179 1 2 10K_0402_5% SERIRQ
RC180 1 2 10K_0402_5% EC_SCI#
RC181 1 2 10K_0402_5% KBRST#
G

G
2

2
+3VS
RC72 1 2 4.7K_0402_5% CP_SMB_CLK PCH_SMB_CLK RC71 1 2 2.2K_0402_1%
RC76 1 2 4.7K_0402_5% CP_SMB_DAT PCH_SMB_DATA RC73 1 2 2.2K_0402_1% Plan to remove QC1 after SDV
PCH_SML1CLK RC74 1 2 2.2K_0402_1%
RC212 1 2 10K_0402_5% GPU_EVENT# PCH_SML1DATA RC75 1 2 2.2K_0402_1%
5

5
G

G
Add RC212 PU by NV suggestion
SML1ALERT# RC77 1 @ 2 1K_0402_5% PCH_SMB_DATA 3 4 PCH_SML1DATA 3 4
CP_SMB_DAT [22,23,63] EC_SMB_DA3 [28,57,59,62]
S

S
D

D
QC1B QC2B
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
SB00000YS00 SB00000YS00

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(7/16):LPC/SPI/SMBUS/CL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 11 of 82
5 4 3 2 1
 5 4 3 2 1

D +VCC_ST D
SKL_ULT
UC1K
SYSTEM POWER MANAGEMENT
+3VALW_PCH PM_SLP_S0#

1
RC85 AT11 1
GPP_B12/SLP_S0# PM_SLP_S3# TC8
1K_0402_5% AP15
GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# [57]
PLTRST# AN10 BA16
SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [57]
1 2 B5 AY16
EC_RSMRST# SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# [57]
RC78 10K_0402_5% AY17
[57] EC_RSMRST# RSMRST#

2
AN15 PCH_SLP_SUS# 1
H_CPUPWRGD SLP_SUS# PCH_SLP_LAN# TC9
TC10 1 A68 AW15
VCCST_PWRGD PROCPWRGD SLP_LAN# PCH_SLP_LAN# [46]
RC89 1 2 60.4_0402_1% B65 BB17
[57] VCCST_PG_EC VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A#
AN16 1
PCH_SYSPWROK GPD6/SLP_A# TC28
B6
[57] PCH_SYSPWROK PCH_PWROK SYS_PWROK PBTN_OUT#
BA20 BA15
EC_RSMRST# [57] PCH_PWROK EC_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT PBTN_OUT# [57]
RC81 1 2 0_0402_5% BB20 AY15
DSW_PWROK GPD1/ACPRESENT AC_PRESENT [57]
AU13 BATLOW#
RC82 1 2 0_0402_5% SUSPWRDNACK AR13 GPD0/BATLOW#
SUSACK# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +RTCVCC
GPP_A15/SUSACK# AU11 PME# 1
PCIE_WAKE# GPP_A11/PME# PCH_INTRUDER# TC11
BB15 AP16 2 1
TC12 1 AM15 WAKE# INTRUDER# RC83 1M_0402_5%
AW17 GPD2/LAN_WAKE# AM10 EXT_PWR_GATE# 1
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# TC13
AT15 AM11 VRALERT# 1
GPD7/RSVD GPP_B2/VRALERT# TC14
Connect to Power
SKYLAKE-U_BGA1356 11 OF 20 ? ?
REV = 1
@

+3VALW Place RC183.184.185.186 close together

1 2 AC_PRESENT
RC183 10K_0402_5%
C C
1 2 BATLOW#
RC184 10K_0402_5%
1 2 PCIE_WAKE#
RC185 10K_0402_5%
1 2 PCH_SLP_LAN#
RC186 10K_0402_5%

1 @ 2 PBTN_OUT#
RC87 10K_0402_5%
+3VALW
UC3
1 5
NC VCC
+3VS PLTRST# 2
PCH_PWROK EC_RSMRST# IN_A
RC218 1 2 PME# 3 4
GND OUT_Y PLT_RST# [28,42,46,48,49,57,58]
20K_0402_5%

1
2

2
20160408 TC7SG17FE_SON5
1.Add RC218 for PME# by BIOS request RC93 RC94 RC88
10K_0402_5% 10K_0402_5% 100K_0402_5%

2
1

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(8/16):SYSTEM PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 12 of 82
5 4 3 2 1
 D

2.0
Re v

82
of
13
Sheet
KBL(9/16):Decoupling

Thursday, August 25, 2016

1

1
KENOBI
Document Number
Custom
Title

Date:
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

1U_0402_10V6-K
1

2016/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

CC50
1U_0402_10V6-K
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CC49
10U_0603_6.3V6-M 1U_0402_10V6-K
LC Future Center Secret Data
1

1 2
CC180 CC48
10U_0603_6.3V6-M 1U_0402_10V6-K
1

Deciphered Date

1 2
CC179 CC47
10U_0603_6.3V6-M 1U_0402_10V6-K
2

2
1

1 2
CC178 CC46
10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC177 CC45
10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC176 CC44
10U_0603_6.3V6-M 1U_0402_10V6-K
[KBL PDG] EE 10uF x12,1uF x14, Power 47uF x8,22uFx12

2015/09/01
1 2
CC175 CC43
Place decoupling cap on TOP side

10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC174 CC42
10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC173 CC41
10U_0603_6.3V6-M 1U_0402_10V6-K
1

Security Classification
1 2
CC26 CC40
10U_0603_6.3V6-M 1U_0402_10V6-K

Issued Date
1

1 2
CC25 CC39
[KBL PDG]VCCGT

10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC24 CC38
10U_0603_6.3V6-M 1U_0402_10V6-K
1

1 2
CC23 CC37
+VCC_GT
3

3
1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

CC22 CC72
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

CC21 CC36 CC62 CC170

1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
Power 22uF x9, 47uF x8

10U_0402_6.3V6-M
CC20 CC35 CC61 CC71 1

2
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC172
1

10U_0402_6.3V6-M
CC19 CC34 CC60 CC69

Place decoupling cap on bottom side

10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC79
1

2
Place decoupling cap on TOP side

10U_0402_6.3V6-M
CC171 CC33 CC59 CC70

2
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC78
[KBL PDG] EE 10uF x7, 10uF x8, 1uF x35

2
10U_0402_6.3V6-M
CC18 CC32 CC58 CC67

2
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC77
1

2
10U_0402_6.3V6-M
CC17 CC31 CC57 CC68
4

4
1

2
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC76
1

2
10U_0402_6.3V6-M
CC16 CC30 CC56 CC65

2
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
CC75
1

2
[KBL PDG]VCC

CC15 CC29 CC55 CC66 10U_0402_6.3V6-M

10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M

2
1

2
CC74
CC14 CC28 CC54 CC64
10U_0402_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 10U_0402_6.3V6-M
1

2
+VCC_CORE

CC13 CC27 CC53 CC63 CC73

5

5
D

A
 5 4 3 2 1

D GPP_B22, Internal PD 20K Project ID D

*L: SPI +3VS PLANARID0 PLANARID1 PLANARID2

(GPP_C8) (GPP_C9) (GPP_C10)
H: LPC
L 14" UMA Skylake
GSPI1_MOSI 2 @ 1 H 15" DIS Kabylake
RC95 1K_0402_5%

+3VS
To enable boot to LPC, this signal should
be pulled up to V3.3S through a 1k to
2.2 K ∮5 % resistor

1
RC96 RC52 RC99
10K_0402_5% 10K_0402_5% @ 10K_0402_5%
KBL@ DIS@

2
GPP_B18, Internal PD 20K
PLANARID0
*L: Disable ¨ No Reboot〃 mode +3VS
〃 mod
H: Enable ¨ No Reboot e PLANARID1

PLANARID2
GSPI0_MOSI 2 @ 1

1
RC102 1K_0402_5%
RC101 RC54 RC104
10K_0402_5% 10K_0402_5% 10K_0402_5%
SKL@ UMA@
To enable no reboot on TCO Timer expiration

2
, this signal should be pulled-up to V3.3S
C through a 1k to 2.2 K ∮5 % resisto r C

? SKL_ULT
UC1F
LPSS ISH

RF_OFF# AN8 P2
[48] RF_OFF# GPP_B15/GSPI0_CS# GPP_D9
AP7 P3
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 DCI_CLK
GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11 DCI_DATA DCI_CLK [55]
AR7 P1
GPP_B18/GSPI0_MOSI GPP_D12 DCI_DATA [55]
AM5 M4
AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
BT_ON AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
[48] BT_ON GSPI1_MOSI GPP_B21/GSPI1_MISO
AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
PLANARID0 AB1 GPP_D8/ISH_I2C1_SCL
PLANARID1 AB2 GPP_C8/UART0_RXD AD11
PLANARID2 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
UART2_RX AD1 U1
[48] UART2_RX UART2_TX GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD2 U2
[48] UART2_TX F4_LED# GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
B AD3 U3 B
[60] F4_LED# PCH_TSOFF# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
AD4 U4
[37] PCH_TSOFF# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 F1_LED#
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD F1_LED# [60]
U6 AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U9 GPP_C18/I2C1_SDA AY8
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
AH9 GPP_A19/ISH_GP1 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL 6 OF 20 GPP_A21/ISH_GP3
SKYLAKE-U_BGA1356 AY7
MIC_HW_EN AH11 REV = 1 ? GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 1
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 TC17
2

AF11
RC108 AF12 GPP_F8/I2C4_SDA
@ GPP_F9/I2C4_SCL
0_0402_5%
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(10/16):GPIO/CPU/MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 14 of 82
5 4 3 2 1
 5 4 3 2 1

D D

USB Port Number

USB_OC0# Reserve
SKL_ULT
UC1H USB_OC1# Port2
SSIC / USB3
USB_OC2# Port3
PCIE/USB3/SATA
H8 USB3P1_RXN USB_OC3# Port4
USB3_1_RXN USB3P1_RXP USB3P1_RXN [55]
G8
PCIE_CRX_GTX_N1 USB3_1_RXP USB3P1_TXN USB3P1_RXP [55]
[25] PCIE_CRX_GTX_N1 H13 C13 TYPE C
PCIE_CRX_GTX_P1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3P1_TXP USB3P1_TXN [55]
[25] PCIE_CRX_GTX_P1 G13 D13
PCIE_CTX_GRX_N1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3P1_TXP [55]
CC86 1 2 0.22U_0402_10V6-K B17
[25] PCIE_CTX_C_GRX_N1 PCIE_CTX_GRX_P1 PCIE1_TXN/USB3_5_TXN USB3P2_RXN
CC87 1DIS@ 2 0.22U_0402_10V6-K A17 J6
[25] PCIE_CTX_C_GRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3P2_RXP USB3P2_RXN [44]
DIS@ H6
PCIE_CRX_GTX_N2 USB3_2_RXP/SSIC_1_RXP USB3P2_TXN USB3P2_RXP [44]
[25] PCIE_CRX_GTX_N2 G11 B13 On Board (Lef t)
PCIE_CRX_GTX_P2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN USB3P2_TXP USB3P2_TXN [44] +3VALW_PCH
[25] PCIE_CRX_GTX_P2 F11 A13
PCIE_CTX_GRX_N2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3P2_TXP [44]
CC88 1 2 0.22U_0402_10V6-K D16
[25] PCIE_CTX_C_GRX_N2 PCIE_CTX_GRX_P2 PCIE2_TXN/USB3_6_TXN
CC89 1DIS@ 2 0.22U_0402_10V6-K C16 J10
[25] PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
DIS@ H10
PCIE_CRX_GTX_N3 H16 USB3_3_RXP/SSIC_2_RXP B15 USB_OC0# RC190 1 2 10K_0402_5%
GPU [25]
[25]
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15 USB_OC1# RC191 1 2 10K_0402_5%
CC90 1 2 0.22U_0402_10V6-K PCIE_CTX_GRX_N3 D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB_OC2# RC192 1 2 10K_0402_5%
[25] PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_P3 PCIE3_TXN USB3P4_RXN USB_OC3#
CC91 1DIS@ 2 0.22U_0402_10V6-K C17 E10 RC193 1 2 10K_0402_5%
[25] PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN USB3P4_RXP USB3P4_RXN [44]
DIS@ F10
PCIE_CRX_GTX_N4 USB3_4_RXP USB3P4_TXN USB3P4_RXP [44]
[25] PCIE_CRX_GTX_N4 G15 C15 On Board (Right-Front)
PCIE_CRX_GTX_P4 PCIE4_RXN USB3_4_TXN USB3P4_TXP USB3P4_TXN [44]
[25] PCIE_CRX_GTX_P4 F15 D15
PCIE_CTX_GRX_N4 PCIE4_RXP USB3_4_TXP USB3P4_TXP [44]
CC92 1 2 0.22U_0402_10V6-K B19
[25] PCIE_CTX_C_GRX_N4 PCIE_CTX_GRX_P4 PCIE4_TXN
CC93 1DIS@ 2 0.22U_0402_10V6-K A19 AB9 USB20_N1
C [25] PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_N1 [55] C
DIS@ AB10 USB20_P1 TYPE C
PCIE_PRX_DTX_N5 USB2P_1 USB20_P1 [55]
[49] PCIE_PRX_DTX_N5 F16 20160308
PCIE_PRX_DTX_P5 E16 PCIE5_RXN AD6 USB20_N2 +3VS
[49] PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 [44] 1. Add RC215,RC217 for SSD detect
1 2 PCIE_PTX_DRX_N5 C19 AD7 USB20_P2
Card Reader [49] PCIE_PTX_C_DRX_N5
CC84 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 [44] On Board (AOU) SSD_DEVSLP1 RC216 2 @ 1 10K_0402_5%
[49] PCIE_PTX_C_DRX_P5 PCIE5_TXP
CC85 0.1U_0402_10V7-K AH3 USB20_N3
USB2N_3 USB20_N3 [45]
G18 AJ3 USB20_P3 On Board (Right-Back)
PCIE6_RXN USB2P_3 USB20_P3 [45]
F18
D20 PCIE6_RXP AD9 USB20_N4
PCIE6_TXN USB2N_4 USB20_N4 [44]
C20 AD10 USB20_P4 On Board (Right-Front) SSD_DET# RC215 2 1 10K_0402_5%
PCIE6_TXP USB2P_4 USB20_P4 [44]
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
[42] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 [37]
[42] SATA_PRX_DTX_P0 E20 AJ2 Touch Panel
SATA_PTX_DRX_N0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 [37]
B21 USB2
HDD [42]
[42]
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6 HDD_DEVSLP0 RC110 2 1 10K_0402_5%
PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 [48]
AF7 USB20_P6 BT
USB2P_6 USB20_P6 [48]
G21
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 [37]
D21 AH2 USB20_P7 CAMERA
PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 [37]
C21 PIRQA# RC113 2 1 10K_0402_5%
PCIE8_TXP/SATA1A_TXP AF8 USB20_N8
PCIE_PRX_DTX_N9 USB2N_8 USB20_N8 [37]
[48] PCIE_PRX_DTX_N9 E22 AF9 USB20_P8 IR CAMERA
PCIE_PRX_DTX_P9 PCIE9_RXN USB2P_8 USB20_P8 [37]
[48] PCIE_PRX_DTX_P9 E23
1 2 PCIE_PTX_DRX_N9 B23 PCIE9_RXP AG1 USB20_N9
WLAN [48] PCIE_PTX_C_DRX_N9
CC82 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P9 A23 PCIE9_TXN USB2N_9 AG2 USB20_P9
USB20_N9 [61]
FPR SSD_DEVSLP1 RC217 2 1 10K_0402_5%
[48] PCIE_PTX_C_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 [61]
CC83 0.1U_0402_10V7-K
PCIE_PRX_DTX_N10 F25 AH7
[46] PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PCIE10_RXN USB2N_10
[46] PCIE_PRX_DTX_P10 E25 AH8
1 2 PCIE_PTX_DRX_N10 D23 PCIE10_RXP USB2P_10
LAN [46] PCIE_PTX_C_DRX_N10
CC80 1 2 0.1U_0402_10V7-K PCIE_PTX_DRX_P10 C23 PCIE10_TXN AB6 USBCOMP 1 2
[46] PCIE_PTX_C_DRX_P10 PCIE10_TXP USB2_COMP
CC81 0.1U_0402_10V7-K AG3 USB2_ID RC114 113_0402_1%
1 2 PCIE_RCOMP F5 USB2_ID AG4 USB2_VBUSSENSE
RC115 100_0402_1% E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0# USB2_ID
TC18 1 XDP_PRDY_N D56 GPP_E9/USB2_OC0# C9 USB_OC1#
B B
XDP_PREQ_N PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# [44] USB2_VBUSSENSE
TC19 1 D61 D9
PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# [44]
PIRQA# BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3# USB_OC3# [44]
PCIE_PRX_DTX_N11 E28 J1 HDD_DEVSLP0
[42] PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 HDD_DEVSLP0 [42]

2
[42] PCIE_PRX_DTX_P11 E27 J2
PCIE_PTX_DRX_N11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 SSD_DEVSLP1 RC116 RC117
[42] PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 SSD_DEVSLP1 [42]
[42] PCIE_PTX_DRX_P11 C24 1K_0402_5% 1K_0402_5%
PCIE_PRX_DTX_N12 E30 PCIE11_TXP/SATA1B_TXP H2
M.2 SSD [42]
[42]
PCIE_PRX_DTX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_P12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1

1
PCIE_PTX_DRX_N12 A25 G4 SSD_DET#
[42] PCIE_PTX_DRX_N12 PCIE_PTX_DRX_P12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 SSD_DET# [42]
[42] PCIE_PTX_DRX_P12 B25
PCIE12_TXP/SATA2_TXP H1
GPP_E8/SATALED#

SKYLAKE-U_BGA1356 8 OF 20 ? ?
REV = 1
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(11/16):PCIE/USB/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 15 of 82
5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1L
+VCC_CORE CPU POWER 1 OF 4
+VCC_CORE

A30 G32
A34 VCC_A30 VCC_G32 G33
A39 VCC_A34 VCC_G33 G35
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
D D
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42 +VCC_ST [KBL PDG]VIDSOUT
AK38 VCC_AK37 VCC_G42 J30
AK40 VCC_AK38 VCC_J30 J33
VCC_AK40 VCC_J33
Rpu2

1
AL33 J37
AL37 VCC_AL33 VCC_J37 J40 +VCC_CORE RC119
AL40 VCC_AL37 VCC_J40 K33 100_0402_1%
AM32 VCC_AL40 VCC_K33 K35
VCC_AM32 VCC_K35

1
AM33 K37
VCC_AM33 VCC_K37

2
AM35 K38 RC120 VR_SVID_DAT
VCC_AM35 VCC_K38 VR_SVID_DAT [70]
AM37 K40 100_0402_1%
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43

2
+VCC_ST [KBL PDG]VIDSCK
K32 E32 VCC_SENSE_R 1 @ 2 RC121 0_0402_5%
RSVD_K32 VCC_SENSE VCC_SENSE [70]
E33 VSS_SENSE_R 1 @ 2 RC122 0_0402_5% Rpu1
VSS_SENSE VSS_SENSE [70]

1
AK32
RSVD_AK32 B63 VR_SVID_ALRT#_R

1
RC124
AB62 VIDALERT# A63 VR_SVID_CLK @ 100_0402_1%
P62 VCCOPC_AB62 VIDSCK D64 VR_SVID_DAT RC123
V62 VCCOPC_P62 VIDSOUT 100_0402_1%
VCCOPC_V62

2
G20 VR_SVID_CLK
VCCSTG_G20 +VCC_STG VR_SVID_CLK [70]

2
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61 +VCC_ST [KBL PDG]VIDALERT#
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE
Rpu1

1
AE62 RC125
AG62 VCCEOPIO_AE62 56_0402_1%
VCCEOPIO_AG62
Rs1
AL63
VCCEOPIO_SENSE

2
AJ62 VR_SVID_ALRT#_R 1 2 VR_SVID_ALRT#
C VSSEOPIO_SENSE VR_SVID_ALRT# [70] C
RC126 220_0402_1%

SKYLAKE-U_BGA1356 12 OF 20 ? ?
REV = 1
@
+VCC_GT Place CC109
SKL_ULT
+VCC_GT UC1M on bottom side
+1.2V
CPU POWER 2 OF 4
N70 +VCC_IO
A48 VCCGT_N70 N71 [KBL PDG]VCCIO
A53 VCCGT_A48 VCCGT_N71 R63

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
[KBL PDG]VDDQ [KBL PDG]1uF x4
A58 VCCGT_A53 VCCGT_R63 R64
VCCGT_A58 VCCGT_R64
[KBL PDG]10uF x4 Place decoupling cap

1
A62 R65

CC97

CC98

CC99

CC100
VCCGT_A62 VCCGT_R65 on TOP side
A66 R66

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VCCGT_A66 VCCGT_R66 1 1 1 1
AA63 R67

CC102

CC104

CC103

CC105
VCCGT_AA63 VCCGT_R67

2
AA64 R68
AA66 VCCGT_AA64 VCCGT_R68 R69 UC1N SKL_ULT
+VCC_STG +VCC_ST +VCC_ST +VCC_SFR AA67 VCCGT_AA66 VCCGT_R69 R70 2 2 2 2
VCCGT_AA67 VCCGT_R70 CPU POWER 3 OF 4
RC127 AA69 R71
1 2 AA70 VCCGT_AA69 VCCGT_R71 T62 AU23 AK28
AA71 VCCGT_AA70 VCCGT_T62 U65 AU28 VDDQ_AU23 VCCIO_AK28 AK30
AC64 VCCGT_AA71 VCCGT_U65 U68 AU35 VDDQ_AU28 VCCIO_AK30 AL30
1U_0402_10V6K

1U_0402_10V6K

0_0402_5%
1U_0402_10V6K

1 1 1 +VCC_SA
AC65 VCCGT_AC64 VCCGT_U68 U71 AU42 VDDQ_AU35 VCCIO_AL30 AL42
CC108

CC109

CC110

[KBL PDG]VCCSA
AC66 VCCGT_AC65 VCCGT_U71 W63 BB23 VDDQ_AU42 VCCIO_AL42 AM28 [KBL PDG]10uF x13, 1uF x7
AC67 VCCGT_AC66 VCCGT_W63 W64 BB32 VDDQ_BB23 VCCIO_AM28 AM30

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
2 2 2 AC68 VCCGT_AC67 VCCGT_W64 W65 BB41 VDDQ_BB32 VCCIO_AM30 AM42
VCCGT_AC68 VCCGT_W65 VDDQ_BB41 VCCIO_AM42
Place decoupling cap

1
AC69 W66 BB47

CC114

CC115

CC116

CC117

CC118

CC119
Place CC109 Place CC110 VCCGT_AC69 VCCGT_W66 VDDQ_BB47 on TOP side
on bottom side on bottom side AC70 W67 BB51 AK23
AC71 VCCGT_AC70 VCCGT_W67 W68 VDDQ_BB51 VCCSA_AK23 AK25
VCCGT_AC71 VCCGT_W68 VCCSA_AK25

2
J43 W69 G23
[SKL PDG]VCCSTG [SKL PDG]VCCST [SKL PDG]VCCPLL J45 VCCGT_J43 VCCGT_W69 W70 AM40 VCCSA_G23 G25
VCCGT_J45 VCCGT_W70 +1.2V VDDQC VCCSA_G25
[SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 J46 W71 G27
J48 VCCGT_J46 VCCGT_W71 Y62 A18 VCCSA_G27 G28
B +VCC_ST B
J50 VCCGT_J48 VCCGT_Y62 VCCST VCCSA_G28 J22

10U_0603_6.3V6-M
+1.2V +1.2V +VCC_SFROC J52 VCCGT_J50 A22 VCCSA_J22 J23

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VCCGT_J52 +VCC_STG VCCSTG_A22 VCCSA_J23 1 1 1 1 1 1 1

1
RC128 J53 AK42 J27

CC120

CC121

CC122

CC124

CC123

CC126

CC125

CC127
+VCC_SFROC should be VCCGT_J53 VCCGTX_AK42 VCCSA_J27
1 2 sourced from the VDDQ VR J55 AK43 +VCC_SFROC AL23 K23
J56 VCCGT_J55 VCCGTX_AK43 AK45 VCCPLL_OC VCCSA_K23 K25
10U_0603_6.3V6-M

VCCGT_J56 VCCGTX_AK45 VCCSA_K25

2
0_0402_5% J58 AK46 K20 K27 2 2 2 2 2 2 2
1U_0402_10V6K

1 VCCGT_J58 VCCGTX_AK46 +VCC_SFR VCCPLL_K20 VCCSA_K27

1

J60 AK48 K21 K28

CC129

CC130

K48 VCCGT_J60 VCCGTX_AK48 AK50 VCCPLL_K21 VCCSA_K28 K30

K50 VCCGT_K48 VCCGTX_AK50 AK52 VCCSA_K30
VCCGT_K50 VCCGTX_AK52
2

2 K52 AK53 AM23 VCCIO_SENSE RC129 1 2 100_0402_1%

VCCGT_K52 VCCGTX_AK53 VCCIO_SENSE VSSIO_SENSE +VCC_IO
Place CC129 Place CC130 K53 AK55 AM22 RC130 1 2 100_0402_1%
K55 VCCGT_K53 VCCGTX_AK55 AK56 VSSIO_SENSE RC131
on bottom side on bottom side VCCGT_K55 VCCGTX_AK56
K56 AK58 H21VSSSA_SENSE_R 1 @ 2 0_0402_5%
K58 VCCGT_K56 VCCGTX_AK58 AK60 VSSSA_SENSE H20VCCSA_SENSE_R 1 @ 2 +VCC_SA
[SKL PDG]VDDQC [SKL PDG]VCCPLL K60 VCCGT_K58 VCCGTX_AK60 AK70 VCCSA_SENSE
[SKL PDG]10uF x1 [SKL PDG]1uF x1 L62 VCCGT_K60 VCCGTX_AK70 AL43 0_0402_5% RC132
VCCGT_L62 VCCGTX_AL43

1
L63 AL46 SKYLAKE-U_BGA1356 14 OF 20 ? ?
L64 VCCGT_L63 VCCGTX_AL46 AL50 REV = 1 RC133
L65 VCCGT_L64 VCCGTX_AL50 AL53 100_0402_1%
Preferred to place the 10uF cap VCCGT_L65 VCCGTX_AL53 @
on the secondary under L66 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
the package shadow near VCCGT_L67 VCCGTX_AL60

2
VDDQC pin and short to L68 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
VDDQ rail under with a shape +VCC_GT L70 VCCGT_L69 VCCGTX_AM50 AM52
VSSSA_SENSE [70]
VCCGT_L70 VCCGTX_AM52 VCCSA_SENSE [70]
L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
VCCGT_M62 VCCGTX_AM56
1

N63 AM58
VCCGT_N63 VCCGTX_AM58

1
RC134 N64 AU58
100_0402_1% N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57 RC135
N69 VCCGT_N67 VCCGTX_BB57 BB66 100_0402_1%
VCCGT_N69 VCCGTX_BB66
2

2
RC136 1 @ 2 0_0402_5% J70 AK62
[70] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
RC137 1 @ 2 0_0402_5% J69 AL61
A [70] VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE A
1

SKYLAKE-U_BGA1356 13 OF 20 ? ?
RC138 REV = 1
100_0402_1% @
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(12/16):POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 16 of 82
5 4 3 2 1
 5 4 3 2 1

+1VALW_PCH

D D
VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated 85mA
Reserve for Sense Resistor primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.) +3VALW_PCH
1 1 SKL_ULT
+VCC_MPHYGT +VCC_MPHYGT UC1O
+1.8VALW +1.8VALW_PCH CC181 CC131
CPU POWER 4 OF 4
RC139 0_0603_5% 22U_0603_6.3V6-M 22U_0603_6.3V6-M
1 2 2 2 AB19 161mA
CC132 please close to N18 +PCH_CORE VCCPRIM_1P0_AB19 +1.8VALW_PCH
CC133 & CC134 please close to N15 AB20 1100mA AK15
+3VALW +3VALW_PCH P18 VCCPRIM_1P0_AB20 VCCPGPPA AG15

1U_0402_10V6K
1 VCCPRIM_1P0_P18 VCCPGPPB
RC140 0_0805_5% Y16
1 2 AF18 VCCPGPPC Y15

CC132

1U_0402_10V6K
1 1 VCCPRIM_CORE_AF18 VCCPGPPD
[SKL PDG]VccMPHYGT AF19 T16 +3VALW_PRIM
2 V20 VCCPRIM_CORE_AF19 VCCPGPPE AF16

CC133
[SKL PDG]1uF x1 CC134 1 1 600mA
+1VALW +1VALW_PCH [SKL PDG]Close N15, 47U_0805_6.3V6-M V21 VCCPRIM_CORE_V20 VCCPGPPF AD15
Placement type:Edge<3mm(118mil) 2 2 VCCPRIM_CORE_V21 VCCPGPPG 135mA
RC141 0_0805_5% [SKL PDG]VccAPLLEBB CC182 CC135 +1VALW_PCH
1 2 [SKL PDG]1uF x1 [SKL PDG]47uF x1 22U_0603_6.3V6-M 22U_0603_6.3V6-M +DCPDSW AL1 V19
[SKL PDG]Close N18, [SKL PDG]Close N15, 2 2 DCPDSW_1P0 22mA VCCPRIM_3P3_V19
Placement type:Edge<3mm(118mil) Placement type:Edge<10mm(394mil) K17 T1 +1.8VALW_PCH
+1VALW +VCC_MPHYGT +VCC_MPHYGT L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
RC202 0_0805_5% SRAM Primary Well 1.0 V. Dedicated SRAM rail and can Mod PHY Always On Primary 1.0 V: Always on primary VCCMPHYAON_1P0_L1 AA1 +3VALW_RTCPRIM
1 2 have on board power down gate control. supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic N15 VCCATS_1P8
N16 VCCMPHYGT_1P0_N15 AK17 +RTCVCC
+VCC_MPHYGT +1VALW_PCH N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
VCCMPHYGT_1P0_N17 1500mA
P15 AK19
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
CC136 please close to AF20 VCCMPHYGT_1P0_P16 VCCRTC_BB14
CC137 please close to K17 +VCC_AMPHYPLL K15 BB10

1U_0402_10V6K
1 +DCPRTC
@ L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L1588mA A14

CC136

1U_0402_10V6K
1 +1VALW_PLL VCCCLK1
V15
2 VCCAPLL_1P0 26mA K19

CC137
AB17 VCCCLK2
2 +VCC_DSW3P3 Y18 VCCPRIM_1P0_AB17 L21
[SKL PDG]VccSRAM [SKL PDG]VccMPHYAON VCCPRIM_1P0_Y18 VCCCLK3
[SKL PDG]1uF x1 [SKL PDG]1uF x1 AD17 N20
[SKL PDG]Close AF20, [SKL PDG]Close K17, AD18 VCCDSW_3P3_AD17 VCCCLK4
Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil) VCCDSW_3P3_AD18 118mA
AJ17 L19
+VCC_HDA VCCDSW_3P3_AJ17 VCCCLK5
Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM AJ19 A10
+VCC_MPHYGT power, USB AFE Digital Logic, JTAG, Thermal Sensor and VCCHDA 68mA VCCCLK6
MIPI DPHY. AJ16 AN11 1
C +3V_SPI C
VCCSPI GPP_B0/CORE_VID0 T1
RC1451 2 0_0402_5% +VCC_AMPHYPLL +3VALW_PCH +1VALW_PCH AN13 1
GPP_B1/CORE_VID1 T2
AF20
AF21 VCCSRAM_1P0_AF20
+1VALW_PCH T19 VCCSRAM_1P0_AF21
please close to AG15 , Y16 & T16 CC143 please close to AB19 VCCSRAM_1P0_T19
565mA
+3VALW_PRIM T20
RC1461 2 0_0402_5% +1VALW_PLL VCCSRAM_1P0_T20
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1 1 1
AJ21

1U_0402_10V6K
1 VCCPRIM_3P3_AJ21 75mA
CC140

CC141

CC142

AK20

CC143
2 2 2 VCCPRIM_1P0_AK20 33mA
2 N18
[SKL PDG]VCCPRIM VCCAPLLEBB 33mA
[SKL PDG]1uF x1
[SKL PDG]Close AB19, SKYLAKE-U_BGA1356 15 OF 20 ? ?
Placement type:Edge<10mm(394mil) REV = 1
@

Primary Well 3.3 V HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Thermal Sensor Primary Well 1.8 V Deep Sx Well 1.0 V: This rail is generated by on die DSW RTC de-coupling capacitor only. This rail should NOT
Definition Audio. +1.8VALW_PCH low dropout (LDO) linear voltage regulator to supply DSW be driven.
GPIOs, DSW core logic and DSW USB2 logic. Board needs to
+3VALW_PCH +3VALW_PCH connect 1 uF capacitor to this rail and power should NOT
B +3VALW_PRIM +VCC_HDA be driven from the board. When primary well power is up, +DCPRTC B
this rail is bypassed from VCCPRIM_1p0.

1U_0402_10V6K
1
RC147 1 2 0_0402_5% RC148 1 2 0_0402_5% 1
+DCPDSW
1U_0402_10V6K

CC144
1
1U_0402_10V6K

1U_0402_10V6K
@ @ 1 1 CC146
2 0.1U_0402_10V6-K
CC145

[SKL PDG]VCCPRIM [SKL PDG]VccHDA [SKL PDG]VccATS [SKL PDG]DcpDSW [SKL PDG]DcpRTC
2
CC147

CC148
[SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]0.1uF x1
[SKL PDG]Close V19, 2 [SKL PDG]Close AJ19, [SKL PDG]Close AA1, [SKL PDG]Close AL1, [SKL PDG]Close BB10,
Placement type:Edge<3mm(118mil) Placement type:Edge<10mm(394mil) 2 Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil) 2 Placement type:Edge<3mm(118mil)

Deep Sx Well for GPD GPIOs and USB2 RTC Logic Primary Well 3.3 V. This power supplies the RTC RTC Logic Primary Well 3.3 V. This power supplies
Core Logic Primary Well: This rail scales from 0.85 V internal VRM. It will be off during Deep Sx mode. the RTC internal VRM. It will be off during Deep
to 1.0 V. +3VALW_PCH Sx mode.
+3VALW_RTCPRIM
+PCH_CORE
+VCC_AMPHYPLL +1VALW +RTCVCC
1 2
RC150 0_0402_5%
1 2 0_0805_5%
1U_0402_10V6K

1U_0402_10V6K

0.1U_0402_10V6-K

0.1U_0402_10V6-K

1U_0402_10V6K
1 RC151 @ 1 1 1 1
@ 1 +3VALW_PCH 1 2 +VCC_DSW3P3
CC149

1U_0402_10V6K

CC151

CC152

CC153

CC154
RC152 0_0402_5% [SKL PDG]VccRTC
CC150

[SKL PDG]VccPRIM_Core @ [SKL PDG]VccRTCPRIM [SKL PDG]1uF x1

2 [SKL PDG]1uF x1 [SKL PDG]1uF x1,0.1uF x2 2 2 2 [SKL PDG]Close AK19, 2
[SKL PDG]Close AF18, 2 [SKL PDG]VccDSW [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)
Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(13/16):POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A2 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 17 of 82
5 4 3 2 1
 5 4 3 2 1

D D

UC1P UC1Q UC1R

SKL_ULT SKL_ULT
SKL_ULT
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT68 VSS_AT63 VSS_BA49 BA53 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AT71 VSS_AT68 VSS_BA53 BA57 G22 VSS_G10 VSS_L2 L20
AA2 VSS_A70 VSS_AM13 AM21 AU10 VSS_AT71 VSS_BA57 BA6 G43 VSS_G22 VSS_L20 L4
AA4 VSS_AA2 VSS_AM21 AM25 AU15 VSS_AU10 VSS_BA6 BA62 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU20 VSS_AU15 VSS_BA62 BA66 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU32 VSS_AU20 VSS_BA66 BA71 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AU38 VSS_AU32 VSS_BA71 BB18 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV1 VSS_AU38 VSS_BB18 BB26 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV68 VSS_AV1 VSS_BB26 BB30 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV69 VSS_AV68 VSS_BB30 BB34 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV70 VSS_AV69 VSS_BB34 BB38 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AV71 VSS_AV70 VSS_BB38 BB43 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW10 VSS_AV71 VSS_BB43 BB55 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW12 VSS_AW10 VSS_BB55 BB6 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW14 VSS_AW12 VSS_BB6 BB60 H18 VSS_H15 VSS_P20 P21
C
AD21 VSS_AD20 VSS_AN20 AN23 AW16 VSS_AW14 VSS_BB60 BB64 H71 VSS_H18 VSS_P21 R13 C
AD62 VSS_AD21 VSS_AN23 AN28 AW18 VSS_AW16 VSS_BB64 BB67 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW21 VSS_AW18 VSS_BB67 BB70 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW23 VSS_AW21 VSS_BB70 C1 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW26 VSS_AW23 VSS_C1 C25 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW28 VSS_AW26 VSS_C25 C5 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW30 VSS_AW28 VSS_C5 D10 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW32 VSS_AW30 VSS_D10 D11 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW34 VSS_AW32 VSS_D11 D14 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW36 VSS_AW34 VSS_D14 D18 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW38 VSS_AW36 VSS_D18 D22 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW41 VSS_AW38 VSS_D22 D25 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW43 VSS_AW41 VSS_D25 D26 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW45 VSS_AW43 VSS_D26 D30 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW47 VSS_AW45 VSS_D30 D34 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW49 VSS_AW47 VSS_D34 D39 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW51 VSS_AW49 VSS_D39 D44 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW53 VSS_AW51 VSS_D44 D45 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW55 VSS_AW53 VSS_D45 D47 K67 VSS_K66 VSS_V18 W13
AG19 VSS_AG18 VSS_AP35 AP38 AW57 VSS_AW55 VSS_D47 D48 K68 VSS_K67 VSS_W13 W6
AG20 VSS_AG19 VSS_AP38 AP42 AW6 VSS_AW57 VSS_D48 D53 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW60 VSS_AW6 VSS_D53 D58 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW62 VSS_AW60 VSS_D58 D6 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW64 VSS_AW62 VSS_D6 D62 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW66 VSS_AW64 VSS_D62 D66 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AW8 VSS_AW66 VSS_D66 D69 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 AY66 VSS_AW8 VSS_D69 E11
AH67 VSS_AH64 VSS_AR15 AR16 B10 VSS_AY66 VSS_E11 E15
AJ15 VSS_AH67 VSS_AR16 AR20 B14 VSS_B10 VSS_E15 E18
AJ18 VSS_AJ15 VSS_AR20 AR23 B18 VSS_B14 VSS_E18 E21 SKYLAKE-U_BGA1356 18 OF 20
AJ20 VSS_AJ18 VSS_AR23 AR28 B22 VSS_B18 VSS_E21 E46 REV = 1 ? ?
AJ4 VSS_AJ20 VSS_AR28 AR35 B30 VSS_B22 VSS_E46 E50
AK11 VSS_AJ4 VSS_AR35 AR42 B34 VSS_B30 VSS_E50 E53
AK16 VSS_AK11 VSS_AR42 AR43 B39 VSS_B34 VSS_E53 E56
AK18 VSS_AK16 VSS_AR43 AR45 B44 VSS_B39 VSS_E56 E6
B B
AK21 VSS_AK18 VSS_AR45 AR46 B48 VSS_B44 VSS_E6 E65
AK22 VSS_AK21 VSS_AR46 AR48 B53 VSS_B48 VSS_E65 E71
AK27 VSS_AK22 VSS_AR48 AR5 B58 VSS_B53 VSS_E71 F1
AK63 VSS_AK27 VSS_AR5 AR50 B62 VSS_B58 VSS_F1 F13
AK68 VSS_AK63 VSS_AR50 AR52 B66 VSS_B62 VSS_F13 F2
AK69 VSS_AK68 VSS_AR52 AR53 B71 VSS_B66 VSS_F2 F22
AK8 VSS_AK69 VSS_AR53 AR55 BA1 VSS_B71 VSS_F22 F23
AL2 VSS_AK8 VSS_AR55 AR58 BA10 VSS_BA1 VSS_F23 F27
AL28 VSS_AL2 VSS_AR58 AR63 BA14 VSS_BA10 VSS_F27 F28
AL32 VSS_AL28 VSS_AR63 AR8 BA18 VSS_BA14 VSS_F28 F32
AL35 VSS_AL32 VSS_AR8 AT2 BA2 VSS_BA18 VSS_F32 F33
AL38 VSS_AL35 VSS_AT2 AT20 BA23 VSS_BA2 VSS_F33 F35
AL4 VSS_AL38 VSS_AT20 AT23 BA28 VSS_BA23 VSS_F35 F37
AL45 VSS_AL4 VSS_AT23 AT28 BA32 VSS_BA28 VSS_F37 F38
AL48 VSS_AL45 VSS_AT28 AT35 BA36 VSS_BA32 VSS_F38 F4
AL52 VSS_AL48 VSS_AT35 AT4 F68 VSS_BA36 VSS_F4 F40
AL55 VSS_AL52 VSS_AT4 AT42 BA45 VSS_F68 VSS_F40 F42
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA45 VSS_F42 BA41
AL64 VSS_AL58 VSS_AT56 AT58 VSS_BA41
VSS_AL64 VSS_AT58

SKYLAKE-U_BGA1356 16 OF 20 SKYLAKE-U_BGA1356 17 OF 20
REV = 1 ? ? REV = 1 ? ?

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(14/16):GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 18 of 82
5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1I

CSI-2

C C
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 1 @ 2
EMMC_RCOMP
SKYLAKE-U_BGA1356 9 OF 20 ? ? RC153
REV = 1 200_0402_1%
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(15/16):CSI-2/EMMC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 19 of 82
5 4 3 2 1
 5 4 3 2 1

[SKL EDS]
D D

CFG0 +VCC_IO

SKL_ULT
UC1S CFG0 RC154 2 @ 1 1K_0402_5%

RESERVED SIGNALS-1 RC155 2 @ 1 1K_0402_1%

CFG0 E68 BB68

B67 CFG[0] RSVD_TP_BB68 BB69
CFG[1] RSVD_TP_BB69
L:Stall.
D65 *H:(Default) Normal Operation; No stall.
CFG3 D67 CFG[2] AK13
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12
C68 CFG[4] RSVD_TP_AK12
D68 CFG[5] BB2
C67 CFG[6] RSVD_BB2 BA3 +VCC_IO
CFG[7] RSVD_BA3
CFG4
F71
G69 CFG[8]
F70 CFG[9] AU5 CFG4 RC156 2 @ 1 1K_0402_5%
G68 CFG[10] TP5 AT5
H70 CFG[11] TP6 RC157 2 1 1K_0402_1%
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4
*L: Embedded DisplayPort Enabled
B2 H: Embedded DisplayPort Disabled
E63 RSVD_B2 C2
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
CFG[19]
CFG3
AW1
RC158 2 1 49.9_0402_1% CFG_RCOMP E60 RSVD_AW1 CFG3 RC159 1 @ 2 1K_0402_5%
CFG_RCOMP E1
RC160 2 1 1.5K_0402_5% ITP_PMODE E8 RSVD_E1 E2
C +1VALW_PCH ITP_PMODE RSVD_E2 C
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
RSVD_AY1 RSVD_BB4
CFG3 require >= 0.5"
D1 A4 CPU Debug Consent Strap
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69 RC161
RSVD_AL27 AY3 RSVD_AY3 1 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71 @
RSVD_B70 RSVD_D71 C70 TABLE
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54 CFG0 : Stall Reset Sequence
BA70
RSVD_TP_BA70 TP1
AY4 after PCU PLL Lock until de-asserted
BA68 BB3
RSVD_TP_BA68 TP2 RC162 1 : No Stall
J71
RSVD_J71 VSS_AY71
AY71 VSS_AY71 1 @ 2 0_0402_5% +VCC_ST 0 : Stall
J68 AR56 ZVM# 1 TC21
RSVD_J68 ZVM#
F65 AW71
G65 VSS_F65 RSVD_TP_AW71 AW70
VSS_G65 RSVD_TP_AW70 CFG4 : eDP Enable
F61
RSVD_F61 MSM#
AP56 MSM# 1 TC22 1 : Disabled
E61 C64 PROC_SELECT 2 @ 1
RSVD_E61 PROC_SELECT# RC163 100K_0402_1% 0 : Enabled

B SKYLAKE-U_BGA1356 19 OF 20 ? ? B
REV = 1
@

UC1T SKL_ULT

SPARE

AW69 F6
AW68 RSVD_AW69 RSVD_F6 E3
AU56 RSVD_AW68 RSVD_E3 C11
AW48 RSVD_AU56 RSVD_C11 B11
C7 RSVD_AW48 RSVD_B11 A11
U12 RSVD_C7 RSVD_A11 D12
U11 RSVD_U12 RSVD_D12 C12
H11 RSVD_U11 RSVD_C12 F52
RSVD_H11 RSVD_F52

SKYLAKE-U_BGA1356 20 OF 20 ? ?
REV = 1
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KBL(16/16):CFG/RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 20 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+3VALW +3V_SPI

RC164 1 2 0_0603_5%

0.085 A

4MB(32Mb) Reserve 8MB(64Mb) [SKL]SPI0_CS0#: SPI FLASH

SPI0_CS1#: SPI FLASH
SPI0_CS2#: SPI TPM

+3V_SPI
+3V_SPI
UC8M1 UC4M1
SPI_CS0#_8MB 1 8 +3V_SPI SPI_CS1#_4MB 1 8 +3V_SPI
[11] SPI_CS0#_8MB CS# VCC [11] SPI_CS1#_4MB SPI_SO_4MB CS# VCC SPI_IO3_4MB
2 7
SPI_SO_8MB 2 7 SPI_IO3_8MB SPI_IO2_4MB 3 DO HOLD# 6 SPI_CLK_4MB
C DO HOLD# 1 WP# CLK 1 C
4 5 SPI_SI_4MB CC157
SPI_IO2_8MB 3 6 SPI_CLK_8MB CC156 GND DI 0.1U_0402_10V7-K
WP# CLK 0.1U_0402_10V7-K W25Q32FVSSIQ_SO8 4M@
4 5 SPI_SI_8MB 2 2
GND DI 4M@

W25Q64FVSSIQ_SO8

Place RC194,195,196,197 close together Place RC203,204,205,206 close together

SPI_IO3_8MB RC194 1 2 33_0402_5% SPI_IO3 SPI_IO3_4MB RC203 1 4M@ 2 33_0402_5% SPI_IO3
SPI_CLK_8MB SPI_CLK SPI_IO3 [11] SPI_CLK_4MB SPI_CLK
RC195 1 2 33_0402_5% SPI_CLK [11,58] RC204 1 4M@ 2 33_0402_5%
SPI_SI_8MB RC196 1 2 33_0402_5% SPI_SI SPI_SI_4MB RC205 1 4M@ 2 33_0402_5% SPI_SI
SPI_IO2_8MB SPI_IO2 SPI_SI [11,58] SPI_IO2_4MB SPI_IO2
RC197 1 2 33_0402_5% RC206 1 4M@ 2 33_0402_5%
SPI_IO2 [11]

Near SPI ROM

Near SPI ROM

SPI_SO_8MB 1 2 SPI_SO SPI_SO_4MB 1 4M@ 2 SPI_SO
SPI_SO [11,58]
RC165 33_0402_5% RC166 33_0402_5%

B B

+3V_SPI
Mirror Code

RC167 1 2 0_0402_5% SPI_CS0#_8MB SPI_IO2 RC168 2 1 1K_0402_5%

[57] FSCE#
RC169 1 2 0_0402_5% SPI_SI_8MB SPI_IO3 2 1
[57] SPI_FMOSI#
RC170 1K_0402_5%
RC171 1 2 0_0402_5% SPI_SO_8MB
[57] SPI_FMISO
RC172 1 2 0_0402_5% SPI_CLK_8MB SPI_IO3 RC173 1 @ 2 1K_0402_5%
[57] SPI_FSCK

Close to SPI ROM (UC8M1).

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 SPI ROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 21 of 82
5 4 3 2 1
 5 4 3 2 1

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. Place decoupling cap on DRAM side.
330uF placeholder
[KBL PDG]VDDQ [KBL PDG]VPP
+1.2V [KBL PDG] EE 10uF x16, 1uF x16. 330uF x1 +2.5V [KBL PDG] EE 10uF x2, 1uF x2.

1
CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12
10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K

2
D +1.2V Place decoupling on the VTT plane close to SODIMM D

1
+0.6VS [KBL PDG]VTT
+@ [KBL PDG] EE 10uF x2, 1uF x4.
CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD26
1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 330U_D2_2VM_R9M
2

1
CD22 CD23 CD24 CD63 CD64 CD65
10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K

2
DDR_A_D[0..63] [7]

DDR_A_MA[0..16] [7]

DDR_A_DQS#[0..7] [7]

DDR_A_DQS[0..7] [7]
+1.2V
+2.5V +1.2V +1.2V +0.6VS

+1.2V +1.2V

2
+1.2V
RD5
JDIMM1B ME@ 240_0402_1%

JDIMM1A ME@

1
DDR_A_MA3 131 132 DDR_A_MA2
DDR_A_MA1 133 A3 A2 134 EVENT_n_1
1 2 135 A1 EVENT_n/NF 136
DDR_A_D5 3 VSS_1 VSS_2 4 DDR_A_D0 DDR_A_DDRCLK0_1866M 137 VDD_9 VDD_10 138 DDR_A_DDRCLK1_1866M
DQ5 DQ4 [7] DDR_A_DDRCLK0_1866M DDR_A_DDRCLK0_1866M# CK0_t CK1_t/NF DDR_A_DDRCLK1_1866M# DDR_A_DDRCLK1_1866M [7]
5 6 139 140
DDR_A_D1 7 VSS_3 VSS_4 8 DDR_A_D4 [7] DDR_A_DDRCLK0_1866M# 141 CK0_c CK1_c/NF 142 DDR_A_DDRCLK1_1866M# [7]
C
9 DQ1 DQ0 10 DDR_A_PARITY 143 VDD_11 VDD_12 144 DDR_A_MA0 C
DDR_A_DQS#0 VSS_5 VSS_6 [7] DDR_A_PARITY Parity A0
11 12
DDR_A_DQS0 13 DQS0_C DM0_n/DBl0_n 14
15 DQS0_t VSS_7 16 DDR_A_D6 DDR_A_BA1 145 146 DDR_A_MA10
DDR_A_D2 17 VSS_8 DQ6 18 [7] DDR_A_BA1 147 BA1 A10/AP 148
19 DQ7 VSS_9 20 DDR_A_D3 DDR_A_CS0# 149 VDD_13 VDD_14 150 DDR_A_BA0
DDR_A_D7 VSS_10 DQ2 [7] DDR_A_CS0# DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 [7]
21 22 151 152
23 DQ3 VSS_11 24 DDR_A_D8 153 A14/WE_n A16/RAS_n 154
DDR_A_D9 25 VSS_12 DQ12 26 DDR_A_ODT0 155 VDD_15 VDD_16 156 DDR_A_MA15
27 DQ13 VSS_13 28 DDR_A_D13 [7] DDR_A_ODT0 DDR_A_CS1# 157 ODT0 A15/CAS_n 158 DDR_A_MA13
DDR_A_D12 VSS_14 DQ8 [7] DDR_A_CS1# CS1_n A13
29 30 159 160
31 DQ9 VSS_15 32 DDR_A_DQS#1 DDR_A_ODT1 161 VDD_17 VDD_18 162
VSS_16 DQS1_c DDR_A_DQS1 [7] DDR_A_ODT1 ODT1 C0/CS2_n/NC M_VREF_CA_DIMMA
33 34 163 164
35 DM1_n/DBl1_n DQS1_t 36 165 VDD_19 VREFCA 166 SA2_CHA_P
DDR_A_D10 37 VSS_17 VSS_18 38 DDR_A_D11 167 C1/CS3_n/NC SA2 168

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
39 DQ15 DQ14 40 DDR_A_D37 169 VSS_53 VSS_54 170 DDR_A_D33
DDR_A_D15 41 VSS_19 VSS_20 42 DDR_A_D14 171 DQ37 DQ36 172 +1.2V
43 DQ10 DQ11 44 +3VS +3VS +3VS DDR_A_D32 173 VSS_55 VSS_56 174 DDR_A_D36
DDR_A_D16 45 VSS_21 VSS_22 46 DDR_A_D17 175 DQ33 DQ32 176
47 DQ21 DQ20 48 DDR_A_DQS#4 177 VSS_57 VSS_58 178
DDR_A_D20 VSS_23 VSS_24 DDR_A_D21 DDR_A_DQS4 DQS4_c DM4_n/DBl4_n
1

1
49 50 179 180
51 DQ17 DQ16 52 RD6 RD7 RD8 181 DQS4_t VSS_59 182 DDR_A_D35
DDR_A_DQS#2 53 VSS_25 VSS_26 54 10K_0402_5% DDR_A_D38 183 VSS_60 DQ39 184
DQS2_c DM2_n/DBl2_n 10K_0402_5% 10K_0402_5% DQ38 VSS_61 1 2
DDR_A_DQS2 55 56 @ @ @ 185 186 DDR_A_D34
57 DQS2_t VSS_27 58 DDR_A_D22 DDR_A_D39 187 VSS_62 DQ35 188 CD27 CD28
VSS_28 DQ22 DQ34 VSS_63
2

2
DDR_A_D23 59 60 189 190 DDR_A_D41
61 DQ23 VSS_29 62 DDR_A_D19 SA0_CHA_P SA1_CHA_P SA2_CHA_P DDR_A_D40 191 VSS_64 DQ45 192 2@ 1@
DDR_A_D18 63 VSS_30 DQ18 64 193 DQ44 VSS_65 194 DDR_A_D45
65 DQ19 VSS_31 66 DDR_A_D29 DDR_A_D44 195 VSS_66 DQ41 196
DDR_A_D25 VSS_32 DQ28 DQ40 VSS_67 DDR_A_DQS#5
1

1
67 68 197 198
69 DQ29 VSS_33 70 DDR_A_D28 RD9 RD10 RD11 199 VSS_68 DQS5_c 200 DDR_A_DQS5
DDR_A_D24 71 VSS_34 DQ24 72 201 DM5_n/DBl5_n DQS5_t 202
DQ25 VSS_35 0_0402_5% 0_0402_5% 0_0402_5% VSS_69 VSS_70
73 74 DDR_A_DQS#3 DDR_A_D43 203 204 DDR_A_D42
75 VSS_36 DQS3_c 76 DDR_A_DQS3 205 DQ46 DQ47 206
DM3_n/DBl3_n DQS3_t VSS_71 VSS_72
2

2
77 78 DDR_A_D46 207 208 DDR_A_D47
DDR_A_D30 79 VSS_37 VSS_38 80 DDR_A_D31 209 DQ42 DQ43 210
81 DQ30 DQ31 82 DDR_A_D49 211 VSS_73 VSS_74 212 DDR_A_D48 +1.2V
DDR_A_D26 83 VSS_39 VSS_40 84 DDR_A_D27 213 DQ52 DQ53 214
85 DQ26 DQ27 86 DDR_A_D52 215 VSS_75 VSS_76 216 DDR_A_D53
87 VSS_41 VSS_42 88 217 DQ49 DQ48 218
89 CB5/NC CB4/NC 90 DDR_A_DQS#6 219 VSS_77 VSS_78 220
91 VSS_43 VSS_44 92 DDR_A_DQS6 221 DQS6_c DM6_n/DBl6_n 222
DDR_A_DQS#8
93
95
CB1/NC
VSS_45
CB0/NC
VSS_46
94
96
SPD Address = 0H DDR_A_D50
223
225
DQS6_t
VSS_80
VSS_79
DQ54
224
226
DDR_A_D54

B DDR_A_DQS8 97 DQS8_c DM8_n/DBl8_n/NC 98 227 DQS5 VSS_81 228 DDR_A_D51 B

99 DQS8_t VSS_47 100 DDR_A_D55 229 VSS_82 DQ50 230
101 VSS_48 CB6/NC 102 231 DQ51 VSS_83 232 DDR_A_D57
103 CB2/NC VSS_49 104 DDR_A_D56 233 VSS_84 DQ60 234
105 VSS_50 CB7/NC 106 235 DQ61 VSS_85 236 DDR_A_D61
107 CB3/NC VSS_51 108 +3VS DDR_A_D60 237 VSS_86 DQ57 238
DDR_A_CKE0 VSS_52 RESET_n DDR4_DRAMRST# [8,23] DQ56 VSS_87 DDR_A_DQS#7
109 110 239 240
[7] DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 [7] VSS_88 DQS7_c DDR_A_DQS7
111 112 241 242
DDR_A_BG1 VDD_1 VDD_2 DDR_A_ACT_N DM7_n/DBl7_n DQS7_t
2

113 114 243 244

[7] DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT_N DDR_A_ACT_N [7] DDR_A_D59 VSS_89 VSS_90 DDR_A_D63
115 116 RD12 245 246
[7] DDR_A_BG0 117 BG0 ALERT_n 118 DDR_A_ALERT_N [7] 247 DQ62 DQ63 248
@ 0_0402_5%
DDR_A_MA12 119 VDD_3 VDD_4 120 DDR_A_MA11 DDR_A_D58 249 VSS_91 VSS_92 250 DDR_A_D62
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7 251 DQ58 DQ59 252
A9 A7 VSS_93 VSS_94
1

123 124 CP_SMB_CLK 253 254 CP_SMB_DAT

DDR_A_MA8 VDD_5 VDD_6 DDR_A_MA5 [11,23,63] CP_SMB_CLK VDDSPD_1 SCL SDA SA0_CHA_P CP_SMB_DAT [11,23,63]
125 126 255 256
DDR_A_MA6 127 A8 A5 128 DDR_A_MA4 257 VDDSPD SA0 258
129 A6 A4 130 259 VPP_1 VTT 260 SA1_CHA_P
VDD_7 VDD_8 VPP_2 SA1
1 1
[KBL PDG]VDDSPD 261 262
[KBL PDG] EE 0.1uF x1, 2.2uF x1. CD29 CD30 GND_1 GND_2
FOX_AS0A826-H4RB-7H 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M FOX_AS0A826-H4RB-7H
RF
2 2

Place decoupling cap close to DIMM

+1.2V
1

RD1
1K_0402_1%
+1.2V
2

RD2
A A
2_0402_1%
1 2 M_VREF_CA_DIMMA
[7] DDR4_VREF_CA_CPU_A
1

1
RD13 RD14
CD13 240_0402_1% 240_0402_1%
1

0.022U_0402_25V7-K
2
1

RD3
2

2
1

1K_0402_1% CD25
RD4 0.1U_0402_16V7-K DDR_A_DQS#8
2

24.9_0402_1% @
2

DDR_A_DQS8
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 CH-A PRIMARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 22 of 82
5 4 3 2 1
 5 4 3 2 1

Place 10uF/1uF decoupling cap, 4 near each side of the DIMM connector close to VDD pins. Place decoupling cap on DRAM side.
330uF placeholder
+1.2V [KBL PDG]VDDQ [KBL PDG]VPP
[KBL PDG] EE 10uF x16, 1uF x16. 330uF x1 +0.6VS [KBL PDG] EE 10uF x2, 1uF x2.

1
CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD32 CD33 CD42
10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K

2
D +1.2V D
Place decoupling on the VTT plane close to SODIMM
1
+2.5V
+ [KBL PDG]VTT
CD49 CD50 CD51 CD52 CD53 CD54 CD55 CD56 CD57 [KBL PDG] EE 10uF x2, 1uF x4.
1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 330U_D2_2VM_R9M
2

1
CD45 CD46 CD47 CD48 CD68 CD66 CD67
10U_0603_6.3V6-M 10U_0603_6.3V6-M 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K 1U_0402_6.3V6-K

2
DDR_B_D[0..63] [8]

DDR_B_MA[0..16] [8]

Layout Node: DDR_B_DQS#[0..7] [8]

+1.2V
Place Close DIMMs DDR_B_DQS[0..7] [8]
+2.5V +1.2V +1.2V +0.6VS

+1.2V +1.2V

1
+1.2V
RD19
JDIMM2B ME@ 240_0402_1%

JDIMM2A ME@

2
DDR_B_MA3 131 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 EVENT_n_2
1 2 135 A1 EVENT_n 136
DDR_B_D13 3 VSS_1 VSS_2 4 DDR_B_D8 DDR_B_DDRCLK0_1866M 137 VDD_9 VDD_10 138 DDR_B_DDRCLK1_1866M
DQ5 DQ4 [8] DDR_B_DDRCLK0_1866M DDR_B_DDRCLK0_1866M# CK0_t CK1_t DDR_B_DDRCLK1_1866M# DDR_B_DDRCLK1_1866M [8]
5 6 139 140
DDR_B_D12 VSS_3 VSS_4 DDR_B_D9 [8] DDR_B_DDRCLK0_1866M# CK0_c CK1_c DDR_B_DDRCLK1_1866M# [8]
7 8 141 142
9 DQ1 DQ0 10 DDR_B_PARITY 143 VDD_11 VDD_12 144 DDR_B_MA0
C DDR_B_DQS#1 VSS_5 VSS_6 [8] DDR_B_PARITY Parity A0 C
11 12
DDR_B_DQS1 13 DQS0_C DM0_n/DBIO_n 14
15 DQS0_t VSS_7 16 DDR_B_D15 DDR_B_BA1 145 146 DDR_B_MA10
DDR_B_D10 VSS_8 DQ6 [8] DDR_B_BA1 BA1 A10/AP
17 18 147 148
19 DQ7 VSS_9 20 DDR_B_D11 DDR_B_CS0# 149 VDD_13 VDD_14 150 DDR_B_BA0
DDR_B_D14 VSS_10 DQ2 [8] DDR_B_CS0# DDR_B_MA14 CS0_n BA0 DDR_B_MA16 DDR_B_BA0 [8]
21 22 151 152
23 DQ3 VSS_11 24 DDR_B_D1 153 WE_n/A14 RAS_n/A16 154
DDR_B_D4 25 VSS_12 DQ12 26 DDR_B_ODT0 155 VDD_15 VDD_16 156 DDR_B_MA15
DQ13 VSS_13 DDR_B_D5 [8] DDR_B_ODT0 DDR_B_CS1# ODT0 CAS_n/A15 DDR_B_MA13
27 28 157 158
DDR_B_D0 29 VSS_14 DQ8 30 [8] DDR_B_CS1# 159 CS1_n A13 160
31 DQ9 VSS_15 32 DDR_B_DQS#0 DDR_B_ODT1 161 VDD_17 VDD_18 162
VSS_16 DQS1_c DDR_B_DQS0 [8] DDR_B_ODT1 ODT1 C0/CS2_n/NC M_VREF_CA_DIMMB
33 34 163 164
35 DM1_n/DBl1_n DQS1_t 36 165 VDD_19 VREFCA 166 SA2_CHB_P
DDR_B_D6 37 VSS_17 VSS_18 38 DDR_B_D3 167 C1/CS3_n/NC RFU 168

2.2U_0402_6.3V6-M

0.1U_0402_10V7-K
39 DQ15 DQ14 40 DDR_B_D37 169 VSS_53 VSS_54 170 DDR_B_D36 +1.2V
DDR_B_D2 41 VSS_19 VSS_20 42 DDR_B_D7 171 DQ37 DQ36 172
43 DQ10 DQ11 44 DDR_B_D33 173 VSS_55 VSS_56 174 DDR_B_D32
DDR_B_D21 45 VSS_21 VSS_22 46 DDR_B_D20 +3VS +3VS +3VS 175 DQ33 DQ32 176
47 DQ21 DQ20 48 DDR_B_DQS#4 177 VSS_57 VSS_58 178
DDR_B_D16 49 VSS_23 VSS_24 50 DDR_B_D17 DDR_B_DQS4 179 DQS4_c DM4_n/DBl4_n 180
DQ17 DQ16 DQS4_t VSS_59 DDR_B_D35
1

1
51 52 181 182
DDR_B_DQS#2 53 VSS_25 VSS_26 54 RD20 RD21 RD22 DDR_B_D34 183 VSS_60 DQ39 184
DDR_B_DQS2 DQS2_c DM2_n/DBl2_n DQ38 VSS_61 DDR_B_D39 1 1
55 56 10K_0402_5% 10K_0402_5% 10K_0402_5% 185 186
57 DQS2_t VSS_27 58 DDR_B_D23 @ @ DDR_B_D38 187 VSS_62 DQ35 188 CD58 CD59
DDR_B_D18 59 VSS_28 DQ22 60 189 DQ34 VSS_63 190 DDR_B_D45
DQ23 VSS_29 VSS_64 DQ45
2

2
61 62 DDR_B_D19 DDR_B_D41 191 192 2@ 2 @
DDR_B_D22 63 VSS_30 DQ18 64 SA0_CHB_P SA1_CHB_P SA2_CHB_P 193 DQ44 VSS_65 194 DDR_B_D44
65 DQ19 VSS_31 66 DDR_B_D28 DDR_B_D40 195 VSS_66 DQ41 196
DDR_B_D29 67 VSS_32 DQ28 68 197 DQ40 VSS_67 198 DDR_B_DQS#5
DQ29 VSS_33 DDR_B_D24 VSS_68 DQS5_c DDR_B_DQS5
1

1
69 70 199 200
DDR_B_D25 71 VSS_34 DQ24 72 RD23 RD24 RD25 201 DM5_n/DBl5_n DQS5_t 202
73 DQ25 VSS_35 74 DDR_B_DQS#3 DDR_B_D43 203 VSS_69 VSS_70 204 DDR_B_D42
VSS_36 DQS3_c 0_0402_5% 0_0402_5% 0_0402_5% DQ46 DQ47
75 76 DDR_B_DQS3 205 206
77 DM3_n/DBl3_n DQS3_t 78 @ DDR_B_D47 207 VSS_71 VSS_72 208 DDR_B_D46
VSS_37 VSS_38 DQ42 DQ43
2

2
DDR_B_D30 79 80 DDR_B_D31 209 210
81 DQ30 DQ31 82 DDR_B_D53 211 VSS_73 VSS_74 212 DDR_B_D52 +1.2V
DDR_B_D26 83 VSS_39 VSS_40 84 DDR_B_D27 213 DQ52 DQ53 214
85 DQ26 DQ27 86 DDR_B_D48 215 VSS_75 VSS_76 216 DDR_B_D49
87 VSS_41 VSS_42 88 217 DQ49 DQ48 218
89 CB5/NC CB4/NC 90 DDR_B_DQS#6 219 VSS_77 VSS_78 220
91 VSS_43 VSS_44 92 SPD Address = 2H DDR_B_DQS6 221 DQS6_c DM6_n/DBl6_n 222
93 CB1/NC CB0/NC 94 223 DQS6_t VSS_79 224 DDR_B_D51
DDR_B_DQS#8 95 VSS_45 VSS_46 96 DDR_B_D50 225 VSS_80 DQ54 226
DDR_B_DQS8 97 DQS8_c DBI8_n 98 227 DQ55 VSS_81 228 DDR_B_D54
B 99 DQS8_t VSS_47 100 DDR_B_D55 229 VSS_82 DQ50 230 B
101 VSS_48 CB6/NC 102 231 DQ51 VSS_83 232 DDR_B_D56
103 CB2/NC VSS_49 104 +3VS DDR_B_D60 233 VSS_84 DQ60 234
105 VSS_50 CB7/NC 106 235 DQ61 VSS_85 236 DDR_B_D57
107 CB3/NC VSS_51 108 DDR_B_D61 237 VSS_86 DQ57 238
DDR_B_CKE0 109 VSS_52 RESET_n 110 DDR4_DRAMRST# [8,22] 239 DQ56 VSS_87 240 DDR_B_DQS#7
[8] DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 [8] VSS_88 DQS7_c DDR_B_DQS7
2

111 112 241 242

DDR_B_BG1 113 VDD_1 VDD_2 114 RD26 243 DM7_n/DBl7_n DQS7_t 244
[8] DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ACT_N [8] DDR_B_D59 VSS_89 VSS_90 DDR_B_D62
115 116 @ 0_0402_5% 245 246
[8] DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT_N [8] DQ62 DQ63
117 118 247 248
DDR_B_MA12 119 VDD_3 VDD_4 120 DDR_B_MA11 DDR_B_D58 249 VSS_91 VSS_92 250 DDR_B_D63
A12 A11 DQ58 DQ59
1

DDR_B_MA9 121 122 DDR_B_MA7 251 252

123 A9 A7 124 CP_SMB_CLK 253 VSS_93 VSS_94 254 CP_SMB_DAT
DDR_B_MA8 VDD_5 VDD_6 DDR_B_MA5 [11,22,63] CP_SMB_CLK VDDSPD_2 SCL SDA SA0_CHB_P CP_SMB_DAT [11,22,63]
125 126 255 256
DDR_B_MA6 127 A8 A5 128 DDR_B_MA4 257 VDDSPD SA0 258
129 A6 A4 130 259 VPP_1 Vtt 260 SA1_CHB_P
VDD_7 VDD_8 VPP_2 SA1
1 1
[KBL PDG]VDDSPD 261 262
[KBL PDG] EE 0.1uF x1, 2.2uF x1. CD60 CD61 GND_1 GND_2
FOX_AS0A826-H4SB-7H 0.1U_0402_10V7-K 2.2U_0402_6.3V6-M FOX_AS0A826-H4SB-7H
2 2
SP071407011 SP071407011

Place decoupling cap close to DIMM

+1.2V
1

+1.2V

RD15
1K_0402_1%
2

RD16
1

2_0402_1%
1 2 M_VREF_CA_DIMMB RD27 RD28
[7] DDR4_VREF_DQ_CPU_B
240_0402_1% 240_0402_1%
1
A A
2

CD43
DDR_B_DQS#8
1

0.022U_0402_25V7-K
2
1
1

RD17 CD44
RD18 1K_0402_1% 0.1U_0402_16V7-K DDR_B_DQS8
2

24.9_0402_1%
@
2
2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DDR4 CH-B PRIMARY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 23 of 82
5 4 3 2 1
 5 4 3 2 1

Pull-up to DEVID_SEL SMBUS_ALT_ADDR

Resistor Values +3VGS Pull-down to Gnd
4.99K 1000 0000 0 (Default) 0 0x9E (Default)
10K 1001 0001
1 1 0x9C (Multi-GPU usage)
D
15K 1010 0010 D

20K 1011 0011

24.9K 1100 0100
PCIE_CFG VGA_DEVICE
30.1K 1101 0101 0 (Default) 0 3D Device (Class Code 302h)
34.8K 1110 0110
1 1 VGA Device (Default)
45.3K 1111 0111

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_AON SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SI +3VS_AON RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_AON DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
C C
STRAP0 +3VS_AON Reserved(keep pull-up and pull-down footprint and stuff 50Kohm pull-up)
STRAP1 +3VS_AON
STRAP2 +3VS_AON
Reserved(keep pull-up and pull-down footprint and not stuff by default)
STRAP3 +3VS_AON
STRAP4 +3VS_AON

X76

GPU FB Memory (GDDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

Samsung K4W4G1646E-BC1A(E-Die)256MX16 PD 24.9K

SD03424928T
B PD 5K PD 5K PU 50K NC NC NC NC B

N16S-GTR Hynix H5TC4G63CFR-N0C(C-Die)256Mx16 PD 30.1K

N16V-GMR SD03430128T

Micron MT41J256M16LY-091G:N PD 20K

SD02820028T

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 VGA NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 24 of 82
5 4 3 2 1
 1 2 3 4 5

+3VS_AON UV1A
PCIE_CTX_C_GRX_N[1..4] +1VS_VGA
[15] PCIE_CTX_C_GRX_N[1..4] PCIE_CTX_C_GRX_P[1..4]
Midway between GPU
[15] PCIE_CTX_C_GRX_P[1..4] Under GPU Near GPU and power supply

1
COMMON

RV19

10K_0402_5%
PCIE_CRX_GTX_N[1..4] 1/14 PCI_EXPRESS
[15] PCIE_CRX_GTX_N[1..4] PCIE_CRX_GTX_P[1..4]

10U_0603_6.3V6-M

22U_0603_6.3V6-M
1U_0402_6.3VA-K

4.7U_0603_6.3VA-K
[15] PCIE_CRX_GTX_P[1..4]
@
AB6

CV1

CV3

CV4

CV6
PEX_WAKE*_NC 1 1 1 1

2
DIS@ AA22
VGA_PEX_RST# 1 2 RV11 0_0402_5% AC7 PEX_IOVDD_1 AB23
[28] VGA_PEX_RST# PEX_RST* PEX_IOVDD_2 2 2 2 2
AC24

DIS@

DIS@

DIS@

DIS@
CLKREQ_VGA# AC6 PEX_IOVDD_3 AD25
PEX_CLKREQ* PEX_IOVDD_4 AE26
CLK_PCIE_VGA AE8 PEX_IOVDD_5 AE27
[10] CLK_PCIE_VGA CLK_PCIE_VGA# PEX_REFCLK PEX_IOVDD_6
A AD8 A
[10] CLK_PCIE_VGA# PEX_REFCLK*
PCIE_CRX_GTX_P1 CV8 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_P1 AC9
PCIE_CRX_GTX_N1 CV9 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_N1 AB9 PEX_TX0
PEX_TX0*
PCIE_CTX_C_GRX_P1 AG6
PCIE_CTX_C_GRX_N1 AG7 PEX_RX0 AA10
PEX_RX0* PEX_IOVDDQ_1 AA12
PCIE_CRX_GTX_P2 CV10 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_P2 AB10 PEX_IOVDDQ_2 AA13

10U_0603_6.3V6-M

22U_0603_6.3V6-M
1U_0402_6.3VA-K

4.7U_0603_6.3VA-K
PCIE_CRX_GTX_N2 CV11 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_N2 AC10 PEX_TX1 PEX_IOVDDQ_3 AA16
PEX_TX1* PEX_IOVDDQ_4 AA18 NVVDD Decoupling

CV14

CV16

CV18

CV19
PEX_IOVDDQ_5 1 1 1 1
PCIE_CTX_C_GRX_P2 AF7 AA19 Capactior GB2B-64
PCIE_CTX_C_GRX_N2 AE7 PEX_RX1 PEX_IOVDDQ_6 AA20 Type NV DG Actual
PEX_RX1* PEX_IOVDDQ_7 AA21 4.7uF_0603 1 1
PCIE_CRX_GTX_P3 CV12 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_P3 AD11 PEX_IOVDDQ_8 AB22 2 2 2 2 1uF_0402 1 1

DIS@

DIS@

DIS@

DIS@
PCIE_CRX_GTX_N3 CV13 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_N3 AC11 PEX_TX2 PEX_IOVDDQ_9 AC23 22uF_0805 1 1
PEX_TX2* PEX_IOVDDQ_10 AD24 10uF_0805 1 1
PCIE_CTX_C_GRX_P3 AE9 PEX_IOVDDQ_11 AE25
PCIE_CTX_C_GRX_N3 AF9 PEX_RX2 PEX_IOVDDQ_12 AF26
PEX_RX2* PEX_IOVDDQ_13 AF27
PCIE_CRX_GTX_P4 CV21 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_P4 AC12 PEX_IOVDDQ_14
PCIE_CRX_GTX_N4 CV22 1 2 DIS@ 0.22U_0402_10V6-K PCIE_CRX_C_GTX_N4 AB12 PEX_TX3
PEX_TX3*
PCIE_CTX_C_GRX_P4 AG9
PCIE_CTX_C_GRX_N4 AG10 PEX_RX3
PEX_RX3*
AB13
AC13 NC_AB13
NC_AC13
AF10
AE10 NC_AF10 +3VS_AON
NC_AE10
B AD14 NC FOR GF119 B
AC14 NC_AD14
NC_AC14 PEX_PLL_HVDD_1
AA8 Place near GPU
AA9
PEX_PLL_HVDD_2

NC FOR GM108
AE12

0.1U_0402_16V7-K

4.7U_0603_6.3VA-K

4.7U_0603_6.3VA-K
AF12 NC_AE12
NC_AF12 AB8

CV23

CV24

CV25
PEX_SVDD_3V3 1 1 1
AC15
AB15 NC_AC15
NC_AB15
AG12 2 2 2

DIS@

DIS@

DIS@
AG13 NC_AG12
NC_AG13
AB16
AC16 NC_AB16
NC_AC16
+3VS_AON AF13 +VGA_CORE
AE13 NC_AF13
NC_AE13

1
100_0402_1%
2

AD17 RV2
RV21 AC17 NC_AD17

DIS@
NC_AC17
10K_0402_5%
DIS@ AE15
DV1 NC_AE15

2
AF15
NC_AF15
1

DGFX_PWRGD 2 F2
[28,75] DGFX_PWRGD All_GPU_PWRGD VDD_SENSE GFXCORE_VDD_SENSE_D [75]
1 AC18
All_GPU_PWRGD [11] NC_AC18
VDDQPWRGD 3 AB18
[79] VDDQPWRGD NC_AB18 F1
GND_SENSE GFXCORE_GND_SENSE_D [75]
AG15
BAT54AW_SOT323-3 AG16 NC_AG15 to VGA CORE Power IC sense pin

100_0402_1%
NC_AG16

1
+3VS DIS@ RV3
AB19
C AC19 NC_AB19 C

DIS@
NC_AC19
AF16
NC_AF16

2
AE16
NC_AE16
RV922 2 DIS@ 10K_0402_5%
1 VDDQPWRGD AD20
AC20 NC_AD20
NC_AC20
NC FOR GF117/GK208/GM108

AE18
AF18 NC_AE18
NC_AF18
+3VS_AON AC21
NC_AC21 RV6
AB21 @
NC_AB21 AF22 PEX_TSTCLK 1 2 200_0402_5%
NV Suggest AG18 PEX_TSTCLK AE22 PEX_TSTCLK#
AG19 NC_AG18 PEX_TSTCLK*
+3VS_AON NC_AG19
AD23 +1VS_VGA
NC_AD23
2

AE23
RV5 NC_AE23 AA14
Under GPU Near GPU
AF19 PEX_PLLVDD_1 AA15
10K_0402_5% NC_AF19 PEX_PLLVDD_2
AE19

1U_0402_6.3VA-K
0.1U_0402_16V7-K

4.7U_0603_6.3VA-K
DIS@ NC_AE19
2
G

AF24

CV26

CV27

CV28
NC_AF24 1 1 1
DIS@ AE24
NC_AE24
1 3 CLKREQ_VGA# AE21
[10] CLKREQ_PCIE4_VGA# NC_AE21 2 2 2
AF21 AD9 GPU_TESTMODE

DIS@

DIS@

DIS@
D

NC_AF21 TESTMODE
QV1

1
AG24
2N7002KW_SOT323-3 AG25 NC_AG24 10K_0402_5% RV8
NC_AG25
2

DIS@
D RV9 @ AG21 D
AG22 NC_AG21
10K_0402_5% NC_AG22
2

AF25 GPU_PEX_TERMP1 2
PEX_TERMP
1

2.49K_0402_1%
RV10 DIS@
N15S-GM-A1_FCBGA595
Security Classification LC Future Center Secret Data Title
DIS@

1 2 0_0402_5%
Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
RV139 @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 25 of 82
1 2 3 4 5
 5 4 3 2 1

UV1G

N15S-GM-A1_FCBGA_595P UV1J
COMMON N15S-GM-A1_FCBGA_595P
4/14 IFPAB COMMON
UV1K 7/14 IFPEF

N15S-GM-A1_FCBGA_595P AC4 GF119/GK208

COMMON NC_AC4 AC3
NC_AC3 DVI-DL DVI-SL/HDMI DP
3/14 DACA
AA6 I2CY_SDA I2CY_SDA J3
GF117/GM108 GF117 GM108/GK208 NC_AA6 Y3 NC_J3 J2
NC_Y3 I2CY_SCL I2CY_SCL NC_J2
W5 NC NC
B7 Y4 J7
NC_W5 I2CA_SCL A7 NC_Y4 NC_J7
NC I2CA_SDA
AE2 TSEN_VREF
V7 J1
NC_AE2 NC_V7 AA2
TXC TXC NC_J1 K1
AF2 AE3 W7 NC_AA2 AA3 K7
TXC TXC NC_K1
D NC NC D
NC_AF2 NC_AE3 AE4 NC_W7 NC_AA3 NC_K7 K3
NC NC_AE4 TXD0 TXD0 NC_K3 K2
AA1 TXD0 TXD0 NC_K2
AG3 NC_AA1 AB1 K6 M3
NC NC_AG3 NC_AB1 NC_K6 TXD1 TXD1 NC_M3 M2

NC FOR GF117/GM108
AF4
TXD1 TXD1 NC_M2
NC NC_AF4

GF117/GM108
AA5 M1
AF3 NC_AA5 AA4 TXD2 TXD2 NC_M1 N1
NC NC_AF3 NC_AA4 TXD2 TXD2 NC_N1

NC FOR
GM108 IFPE

NC FOR GF117/GM108
GK208 NC FOR GK208
GF117 AB4
NC_AB4 AB5
NC_AB5
HPD_E
C2
W6 AB2
HPD_E GPIO18
NC_W6 NC_AB2

NC FOR GF117/GK208/GM108
N15S-GM-A1_FCBGA595 AB3
Y6 NC_AB3 NC FOR GF117
NC_Y6
AD2 H6
NC_AD2 AD3 NC_H6 GF119/GK208
NC_AD3 J6
NC_J6 DVI-DL DVI-SL/HDMI DP
AD1 I2CZ_SDA
H4
NC_AD1 AE1 NC_H4 H3
NC_AE1 I2CZ_SCL NC_H3

AD5 TXC J5
NC_AD5 AD4 NC_J5 J4
NC_AD4 TXC NC_J4
TXD3 TXD0
K5
NC_K5 K4
TXD3 TXD0 NC_K4
GF117
TXD4 TXD1 L4
B3 IFPF NC_L4 L3

NC FOR GF117/GM108
NC TXD4 TXD1
C
IFPAB GPIO14
TXD5 TXD2
NC_L3
M5
C

NC_M5 M4
TXD5 TXD2 NC_M4
N15S-GM-A1_FCBGA595
NC FOR GK208

HPD_F
F7
GPIO19

NC FOR GF117

N15S-GM-A1_FCBGA595

UV1I

N15S-GM-A1_FCBGA_595P
COMMON
UV1H
6/14 IFPD
N15S-GM-A1_FCBGA_595P
COMMON
U6 GF119/GK208
B B
NC_U6
5/14 IFPC
DVI/HDMI DP IFPC
T7 I2CX_SDA P4 T6 GF119/GK208
NC_T7 NC_P4 P3 NC_T6
I2CX_SCL NC_P3
R7 DVI/HDMI DP
NC_R7
TXC
R5 M7 I2CW_SDA N5
NC_R5 NC_M7 NC_N5

NC FOR GF117/GM108
TXC
R4 N7 I2CW _SCL N4
NC_R4 NC_N7 NC_N4
NC FOR GF117/GM108

T5
TXD0 NC_T5 T4 N3
TXD0 NC_T4 TXC NC_N3
TXC
N2
U4 NC_N2
TXD1 NC_U4
IFPD TXD1 NC_U3
U3
TXD0 NC_R3
R3
R2

NC FOR GF117/GM108
TXD0 NC_R2
V4
TXD2 NC_V4 V3 R1
TXD2 TXD1

NC FOR GF117/GM108
NC_V3 NC_R1 T1
TXD1 NC_T1
GF117 T3
R6 D4
TXD2 NC_T3 T2
NC_R6 NC GPIO17 TXD2 NC_T2

GF117
P6 C3
NC_P6 NC GPIO15

N15S-GM-A1_FCBGA595

N15S-GM-A1_FCBGA595

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 26 of 82
5 4 3 2 1
 1 2 3 4 5

UV1B

[31,32] FBA_D[63..0] N15S-GM-A1_FCBGA_595P

COMMON
2/14 FBA
FBA_D0 E18 F3 GPU_FB_CLAMP
FBA_D1 FBA_D0 NC FB_CLAMP
F18
FBA_D2 E16 FBA_D1
FBA_D2 GF119
FBA_D3 F17

10K_0402_5%
FBA_D4 FBA_D3

2
D20 RV12
FBA_D5 D21 FBA_D4 DIS@
FBA_D6 F20 FBA_D5
FBA_D7 E21 FBA_D6
FBA_D8 E15 FBA_D7
FBA_D8

1
FBA_D9 D15
FBA_D10 F15 FBA_D9
FBA_D11 F13 FBA_D10
FBA_D12 C13 FBA_D11
A A
FBA_D13 B13 FBA_D12
FBA_D14 E13 FBA_D13
FBA_D15 D13 FBA_D14
FBA_D16 B15 FBA_D15
FBA_D17 C16 FBA_D16
FBA_D18 A13 FBA_D17
FBA_D19 A15 FBA_D18
FBA_D20 B18 FBA_D19
FBA_D21 A18 FBA_D20
FBA_D22 A19 FBA_D21
FBA_D23 C19 FBA_D22
FBA_D24 B24 FBA_D23
FBA_D25 C23 FBA_D24
FBA_D26 A25 FBA_D25
FBA_D27 A24 FBA_D26
FBA_D28 A21 FBA_D27
FBA_D29 B21 FBA_D28
FBA_D30 C20 FBA_D29
FBA_D31 C21 FBA_D30
FBA_D32 R22 FBA_D31
FBA_D33 R24 FBA_D32 C27 FBA_CSA0#
FBA_D34 FBA_D33 FBA_CMD0 FBA_CSA0# [31] FBA_MA[0..14] [31,32]
T22 C26
FBA_D35 R23 FBA_D34 FBA_CMD1 E24 FBA_ODTA0
FBA_D36 FBA_D35 FBA_CMD2 FBA_CKEA0 FBA_ODTA0 [31]
N25 F24
FBA_D37 FBA_D36 FBA_CMD3 FBA_MA14 FBA_CKEA0 [31]
N26 D27
FBA_D38 N23 FBA_D37 FBA_CMD4 D26 FBA_RST#
FBA_D39 FBA_D38 FBA_CMD5 FBA_MA9 FBA_RST# [31,32]
N24 F25
FBA_D40 V23 FBA_D39 FBA_CMD6 F26 FBA_MA7
FBA_D41 V22 FBA_D40 FBA_CMD7 F23 FBA_MA2
FBA_D42 T23 FBA_D41 FBA_CMD8 G22 FBA_MA0
FBA_D43 U22 FBA_D42 FBA_CMD9 G23 FBA_MA4
FBA_D44 Y24 FBA_D43 FBA_CMD10 G24 FBA_MA1
FBA_D45 AA24 FBA_D44 FBA_CMD11 F27 FBA_BA0
FBA_D46 FBA_D45 FBA_CMD12 FBA_WE# FBA_BA0 [31,32]
Y22 G25
B FBA_D47 FBA_D46 FBA_CMD13 FBA_WE# [31,32] B
AA23 G27
FBA_D48 AD27 FBA_D47 FBA_CMD14 G26 FBA_CAS#
FBA_D49 FBA_D48 FBA_CMD15 FBA_CSA1# FBA_CAS# [31,32]
AB25 M24
FBA_D50 FBA_D49 FBA_CMD16 FBA_CSA1# [32]
AD26 M23
FBA_D51 AC25 FBA_D50 FBA_CMD17 K24 FBA_ODTA1
FBA_D52 FBA_D51 FBA_CMD18 FBA_CKEA1 FBA_ODTA1 [32]
AA27 K23
FBA_D53 FBA_D52 FBA_CMD19 FBA_MA13 FBA_CKEA1 [32]
AA26 M27
FBA_D54 W26 FBA_D53 FBA_CMD20 M26 FBA_MA8
FBA_D55 Y25 FBA_D54 FBA_CMD21 M25 FBA_MA6
FBA_D56 R26 FBA_D55 FBA_CMD22 K26 FBA_MA11
FBA_D57 T25 FBA_D56 FBA_CMD23 K22 FBA_MA5
FBA_D58 N27 FBA_D57 FBA_CMD24 J23 FBA_MA3
FBA_D59 R27 FBA_D58 FBA_CMD25 J25 FBA_BA2
FBA_D60 FBA_D59 FBA_CMD26 FBA_BA1 FBA_BA2 [31,32]
V26 J24
FBA_D61 FBA_D60 FBA_CMD27 FBA_MA12 FBA_BA1 [31,32] FBA_RST#
V27 K27
FBA_D62 W27 FBA_D61 FBA_CMD28 K25 FBA_MA10 FBA_ODTA0
FBA_D63 W25 FBA_D62 FBA_CMD29 J27 FBA_RAS# FBA_ODTA1
FBA_D63 FBA_CMD30 FBA_RAS# [31,32] FBA_CKEA0
J26
[31,32] FBA_DQM[7..0] FBA_CMD31 FBA_CKEA1
FBA_DQM0 D19
FBA_DQM1 D14 FBA_DQM0

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
FBA_DQM2 C17 FBA_DQM1

RV13

RV14

RV15

RV16

RV20
FBA_DQM2 GF117/GF119
FBA_DQM3

2
C22 GK208
FBA_DQM4 P24 FBA_DQM3 +1.5VS_VGA
FBA_DQM5 W24 FBA_DQM4 B19
FBA_DQM6 FBA_DQM5 NC FBA_CMD32 RV17
AA25

DIS@

DIS@

DIS@

DIS@

DIS@
FBA_DQM7 FBA_DQM6 FBA_CMD34 RV18
U25 FBA_DEBUG0
F22 1 2 @ 0_0402_5%
FBA_DQM7 FBA_CMD34

1
J22 FBA_CMD35 1 2 @ 0_0402_5%
[31,32] FBA_DQS[7..0] FBA_DEBUG1 FBA_CMD35
FBA_DQS0 E19 For Debug
FBA_DQS1 C15 FBA_DQS_WP0
FBA_DQS2 B16 FBA_DQS_WP1 D24 FBA_CLKA0
FBA_DQS3 FBA_DQS_WP2 FBA_CLK0 FBA_CLKA0# FBA_CLKA0 [31]
B22 D25
FBA_DQS4 FBA_DQS_WP3 FBA_CLK0* FBA_CLKA1 FBA_CLKA0# [31]
R25 N22
FBA_DQS5 FBA_DQS_WP4 FBA_CLK1 FBA_CLKA1# FBA_CLKA1 [32]
C W23 M22 C
FBA_DQS6 FBA_DQS_WP5 FBA_CLK1* FBA_CLKA1# [32]
AB26
FBA_DQS7 T26 FBA_DQS_WP6
FBA_DQS_WP7
[31,32] FBA_DQS#[7..0]
FBA_DQS#0 F19 D18
FBA_DQS#1 C14 FBA_DQS_RN0 FBA_WCK01 C18
FBA_DQS#2 A16 FBA_DQS_RN1 FBA_WCK01* D17
FBA_DQS#3 A22 FBA_DQS_RN2 FBA_WCK23 D16
FBA_DQS#4 P25 FBA_DQS_RN3 FBA_WCK23* T24
FBA_DQS#5 W22 FBA_DQS_RN4 FBA_WCK45 U24
FBA_DQS#6 AB27 FBA_DQS_RN5 FBA_WCK45* V24
FBA_DQS#7 T27 FBA_DQS_RN6 FBA_WCK67 V25
FBA_DQS_RN7 FBA_WCK67* +1VS_VGA
LV3
GF119 DIS@
F16 FB_PLL 1 2
FB_PLLAVDD_1
NC
P22

22U_0603_6.3V6-M
0.1U_0402_16V7-K

0.1U_0402_16V7-K

0.1U_0402_16V7-K
FB_PLLAVDD_2 MPZ1608S300AT_2P~D
H22

CV39

CV40

CV41

CV42
FB_PLLAVDD FB_DLLAVDD 1 1 1 1

GF117
2 2 2 2

DIS@

DIS@

DIS@

DIS@
PTP1
1 D23
FB_VREF

Test_Point_12MIL Under GPU

N15S-GM-A1_FCBGA595
D D

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT MEM Interface
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 27 of 82
1 2 3 4 5
 5 4 3 2 1

RV127 @
LV1 DIS@ +3VS_VGA 1 2 10K_0402_1%
1 2 GPU_CORE_PLLVDD
+1VS_VGA
@ RV200 NGC6@ 0_0402_5%
MPZ1608S300AT_2P DGFX_PWRGD 1 2 0_0402_5% 1 2

22U_0603_6.3V6-M

0.1U_0402_16V7-K
[25,75] DGFX_PWRGD
RV925

CV107

CV108
UV1M
1 1 DIS@
VGA_ON 1 2 0_0402_5% 2
N15S-GM-A1_FCBGA_595P [33,75] VGA_ON
COMMON +3VS_AON RV143 1 FB_PWR_EN
+1VS_VGA GC6_FB_EN FB_PWR_EN [79]
1 2 0_0402_5% 3 GC6@

DIS@

DIS@
9/14 XTAL_PLL
2 2

10K_0201_5%

1
L6 RV138 DV101 DAN222MGT2L_VMD3
GPU_SP_PLLVDD M6 CORE_PLLVDD GC6@ RV926
SP_PLLVDD

RV125 @
200K_0402_5%
1 2 1 2GPU_VID_PLLVDD N6 @
VID_PLLVDD NC GC6_FB_EN_GPIO

22U_0603_6.3V6-M

0.1U_0402_25V7K
@ GC6_FB_EN_GPIO [9]

2
0.1U_0402_25V7K
LV2

DIS@ CV103

DIS@ CV104
1

10U_0603_6.3V6-M
RV104 GF119/GK208 GF117/GM108
PBY160808T-301Y-N_2P

CV101
1 2 2 0_0402_5%

1
D CV102 D
DIS@ +3VS_AON

DIS@

DIS@
2 GPU_XTAL_SSIN A10 C10 GPU_XTAL_OUTBUFF
2 1 1 XTAL_SSIN XTAL_OUTBUFF

C11 B10
XTAL_IN XTAL_OUT

10K_0201_5%

DIS@
N15S-GM-A1_FCBGA595

10K_0402_1%
1

2
@ CV109 @

RV108

2
+3VS_AON 1M_0402_5% 0.1U_0402_10V6-K RV141

G
RV110

RV109
2
GPU_XTAL_IN 1 2 GPU_XTAL_OUT
DIS@ 0_0402_5%

1
GC6_FB_EN 3 1 GC6_FB_EN_R 2 1

D
49.9K_0402_1%

QV102 @ @
10K_0402_1%

10K_0402_1%
10K_0402_1%

10K_0402_1%

0_0201_5% 2N7002KW_SOT323-3
Strap0 = H
1

RV970
RV129

RV113
RV111

RV112

DIS@ RV114

enable GC6
Crystal DIS@

2
4 3 GPU_XTAL_OUT_R
GND2 OUT +3VS_AON
@ @ @ @ 1 2
IN GND1
2

STRAP0
STRAP1
STRAP2 DIS@ YV1

2.2K_0402_5%

2.2K_0402_5%
STRAP3 1 27MHZ_7PF_8Y27000005 1
STRAP4
CV105 CV106
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

6.8P_0402_50V8-D 6.8P_0402_50V8-D +3VS_AON

2 2
1

1
DIS@ DIS@
RV115

RV116

RV117

RV118

RV119

SMBUS to EC for Thermal , ID: 0X9E

RV120

DIS@ RV121
@ @ @ @ @ 20160419
2

2
DIS@
Add RV970 to reduce crystal driving level UV1N

5
G
N15S-GM-A1_FCBGA_595P
COMMON
C 8/14 MISC1 C
+3VS_VGA D9 I2CS_SCL 4 3 EC_SMB_CK3

S
UV1L I2CS_SCL I2CS_SDA EC_SMB_CK3 [11,57,59,62]
D8

D
I2CS_SDA

2
G
N15S-GM-A1_FCBGA_595P A9 QV2B
COMMON I2CC_SCL B9 2N7002KDWH_SOT363-6

10K_0402_1%
I2CC_SDA

4.99K_0402_1%
10/14 MISC2 DIS@
1 EC_SMB_DA3

1
1 6
RV101

RV102

RV106
10K_0402_1%

S
GF117 EC_SMB_DA3 [11,57,59,62]
E12

D
THERMDN C9 DIS@
NC I2CB_SCL QV2A
E10 F12 C8
NC_E10 THERMDP NC I2CB_SDA
F10 D12
@

@ @
NC_F10 ROM_CS*
2

2
2N7002KDWH_SOT363-6
B12 ROM_SI TP1 1 Test_Point_12MIL AE5
+3VS_AON ROM_SI A12 ROM_SO TP2 1 Test_Point_12MIL AD6 JTAG_TCK +3VS_AON
STRAP0 D1 ROM_SO C12 ROM_SCLK TP3 1 Test_Point_12MIL AE6 JTAG_TMS
STRAP1 D2 STRAP0 ROM_SCLK TP4 1 Test_Point_12MIL AF6 JTAG_TDI VGA_MPWR_ON 1 2 RV130 DIS@ 10K_0402_1%
4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
STRAP2 E4 STRAP1 AG4 JTAG_TDO C6 GC6_FB_EN
10K_0402_1%

NC FOR
STRAP3 E3 STRAP2 JTAG_TRST* GPIO0 B2 SYS_PEX_RST_MON 1 2 RV123 @ 10K_0402_1%
GM108
STRAP3 GPIO1
1

STRAP4 D3 D6
RV920

RV105

RV103

RV107

STRAP4 GPIO2 C7 VGA_OVERT# 1 2 RV122 DIS@ 10K_0402_1%

10K_0402_5%
GPIO3

2
F9
DIS@ DIS@ GPIO4 A3 VGA_MPWR_ON VGA_ALERT# 1 2 RV131 DIS@ 10K_0402_1%
RV146 GPIO5 VGA_EVENT# VGA_MPWR_ON [33]
X76@

@ C1 GK208
A4
NC_C1 GPIO6
2

D11 DIS@ B6 VGA_PWR_LIM_D 1 2 RV132 DIS@ 100K_0402_5%

BUFRST* GM108 GPIO7 A6 VGA_OVERT#
OVERT OVERT

1
MULTI_STRAP_REF1_GNDMLS_REF1
F6 D10 F8 VGA_ALERT# VGA_PSI 1 2 RV133 DIS@ 10K_0402_1%
MULTI_STRAP_REF0_GND NC PGOOD GPIO9
GF117 VRAM BOM Option C5
GPIO10 VGA_PWM_VID GPU_PEX_RST_HOLD1
2

GK208 GF117 GF119 E7 2 RV134 DIS@ 10K_0402_1%

GPIO11 VGA_PWR_LIM_D VGA_PWM_VID [75]
RV124 GM108 GK208 D7
F4 GM108 GPIO12 B4 VGA_PSI VGA_EVENT# 1 2 RV135 DIS@ 10K_0402_1%
40.2K_0402_1% NC
MULTI_STRAP_REF1_GNDMLS_REF1 GPIO13 VGA_PSI [75]
DIS@ F5 +3VS_AON GC6_FB_EN 1 2 RV166 GC6@ 10K_0402_1%
MULTI_STRAP_REF2_GND NC
1

GM108 GK208 GF117 GF119

GPIO16 GPIO16
D5 UV101 GC6@
NC GPIO16
GPIO20 GPIO20
E6
NC GPIO20 GPU_PEX_RST_HOLD
GPIO21 GPIO8
C4 1 5
NC GPIO21 B VCC
N15S-GM-A1_FCBGA595
DIS@ E9 SYS_PEX_RST_MON 2
GPIO8 NC NC GPIO8 A
DV102
B VGA_PWR_LIM_D VGA_PWR_LIM VGA_PEX_RST# B
2 1 RB751V-40_SOD323-2 VGA_PWR_LIM [57] 3 4
GND Y VGA_PEX_RST# [25]

GC6@ RV128

0_0402_5%
2
DV103 N15S-GM-A1_FCBGA595 74LVC1G08GW_SOT353-1-5
VGA_ALERT# 2 1 RB751V-40_SOD323-2 NGC6@
RV1401 2 0_0402_5% SYS_PEX_RST_MON_R
@

1
SYS_PEX_RST_MON_R
+3VS_AON
@
VGA_PEX_RST# 1 2 0_0402_5% UV102 DIS@ GPIO from PCH to reset GPU when exit Optimus

RV210 5 1 DGPU_HOLD_RST#
VCC B DGPU_HOLD_RST# [9]
PLT_RST#
2

2
G

A PLT_RST# [12,42,46,48,49,57,58]
4 3
Y GND
VGA_OVERT# 3 1
WRST# [57]
S

74LVC1G08GW_SOT353-1-5
QV103 @
1
2N7002KW_SOT323-3
CV112
.01U_0402_16V7-K 20160307 +3VS_AON
2 @
1. Unmount QV103,RV210,CV112

X76 1
CV110 DIS@

2
GPU FB Memory (GDDR3) ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4 0.1U_0402_10V6-K RV145
G 2
GC6@
0_0402_5%
VGA_EVENT# 3 1 GPU_EVENT#_R 2 1 GPU_EVENT#
Samsung K4W4G1646E-BC1A(E-Die)256MX16 PD 24.9K GPU_EVENT# [11]
S

A SD03424928T A
QV101 DIS@
PD 5K PD 5K PU 50K NC NC NC NC RV144 2N7002KW_SOT323-3 Connect to EC or PCH to indicate the GC6 status
0_0402_5% of GPU to the system
@
N16S-GTR Hynix H5TC4G63CFR-N0C(C-Die)256Mx16 PD 30.1K 1 2
N16V-GMR SD03430128T

Micron MT41J256M16LY-091G:N PD 20K Security Classification LC Future Center Secret Data Title
SD02820028T
Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 28 of 82
5 4 3 2 1
 1 2 3 4 5

UV1D

N15S-GM-A1_FCBGA_595P +VGA_CORE
UV1E
+1.5VS_VGA COMMON
12/14 FBVDDQ N15S-GM-A1_FCBGA_595P
COMMON
B26 11/14 NVVDD
C25 FBVDDQ_01 K10
E23 FBVDDQ_02 K12 VDD_001
1 1 1 1 FBVDDQ_03 VDD_002
E26 K14

CV237

CV235

CV230

CV226
1 1 1 1 1

1U_0402_6.3V7-K

1U_0402_6.3V7-K
0.1U_0402_16V7-K

0.1U_0402_16V7-K

4.7U_0603_6.3V6-K
F14 FBVDDQ_04 K16 VDD_003

CV231

CV227

CV229

CV233

CV217
A A

1U_0402_6.3V7-K

1U_0402_6.3V7-K

1U_0402_6.3V7-K

1U_0402_6.3V7-K
F21 FBVDDQ_05 K18 VDD_004
2 2 2 2 G13 FBVDDQ_06 L11 VDD_005
G14 FBVDDQ_07 2 2 2 2 2 L13 VDD_006

DIS@

DIS@

DIS@

DIS@
G15 FBVDDQ_08 L15 VDD_007

DIS@

DIS@

DIS@

DIS@

DIS@
G16 FBVDDQ_09 L17 VDD_008
G18 FBVDDQ_10 M10 VDD_009
G19 FBVDDQ_11 M12 VDD_010
G20 FBVDDQ_12 M14 VDD_011
G21 FBVDDQ_13 M16 VDD_012
L22 FBVDDQ_14 M18 VDD_013
L24 FBVDDQ_19 N11 VDD_014
L26 FBVDDQ_20 N13 VDD_015
M21 FBVDDQ_21 N15 VDD_016
1 1 1 1 1

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K
N21 FBVDDQ_22 N17 VDD_017

CV211

CV209

CV218

CV222

CV213
4.7U_0603_6.3V6-K 1 1

4.7U_0603_6.3V6-K
R21 FBVDDQ_23 P10 VDD_018

CV224

CV219
T21 FBVDDQ_24 P12 VDD_019
V21 FBVDDQ_25 2 2 2 2 2 P14 VDD_020
2 2 W21 FBVDDQ_26 P16 VDD_021

DIS@

DIS@

DIS@

DIS@

DIS@
FBVDDQ_27 P18 VDD_022
DIS@

DIS@
R11 VDD_023
GF117
R13 VDD_024
GF119
R15 VDD_025
GK208
R17 VDD_026
H24 T10 VDD_027
FBVDDQ_AON_H24 FBVDDQ VDD_028
Place under GPU H26 FBVDDQ
T12
J21 FBVDDQ_AON_H26 T14 VDD_029
FBVDDQ_AON_J21 FBVDDQ VDD_030
K21 1 1 1 1 T16

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K
FBVDDQ_AON_K21 FBVDDQ VDD_031
T18

CV223

CV214

CV208

CV216
U11 VDD_032
U13 VDD_033
2 2 2 2 U15 VDD_034
U17 VDD_035

DIS@

DIS@

DIS@

DIS@
V10 VDD_036
V12 VDD_037
B
V14 VDD_038 B
V16 VDD_039
V18 VDD_040
10U_0603_6.3V6-M

22U_0603_6.3V6-M

Place under GPU VDD_041

CV206

CV204

1 1
N15S-GM-A1_FCBGA595
2 2
DIS@

DIS@

+1.5VS_VGA
1 1 1 1 1

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K
40.2_0402_1%

CV212

CV220

CV221

CV210

CV225
RV203
D22 FB_CAL_VDDQ
1 2 DIS@
FB_CAL_VDDQ 2 2 2 2 2
RV202
Place near GPU 42.2_0402_1%

DIS@

DIS@

DIS@

DIS@

DIS@
C24 FB_CAL_GND1 2 DIS@
FB_CAL_GND
RV201
51.1_0402_1%
B25 FB_CAL_TERM
1 2 DIS@
FB_CAL_TERM

N15S-GM-A1_FCBGA595

22U_0603_6.3V6-M

CV205

CV203
47U_0805_4V6-M
1 1
+ CV201
330U_D2_2V_Y
DIS@
2 2 2

DIS@

DIS@
UV1C
C C
Place near GPU
N15S-GM-A1_FCBGA_595P
COMMON
+3VS_VGA
14/14 XVDD/VDD33
Under GPU check with power team for >22UF CAP placement
AD10 G8
AD7 NC_AD10 VDD33_MAIN_G8 G9
NC_AD7 GM108VDD33_MAIN_G9
G10 1 1 1 1
1U_0402_6.3V7-K
0.1U_0402_16V7-K

0.1U_0402_16V7-K

4.7U_0603_6.3V6-K

3V3_AON
VDD33_AON_G10 G12
CV234

CV236

CV228

CV207

3V3_AON
VDD33_AON_G12
F11
NC_F11 2 2 2 2
V5
DIS@

DIS@

DIS@

DIS@

V6 FERMI_RSVD1
FERMI_RSVD2

CONFIGURABLE
POWER CHANNELS
* nc on substrate

G1
G2 NC_G1 +3VS_AON
G3 NC_G2 Under GPU
G4 NC_G3
G5 NC_G4
G6 NC_G5
G7 NC_G6
NC_G7
1 1 1
1U_0402_6.3V7-K
0.1U_0402_16V7-K

4.7U_0603_6.3V6-K
CV238

CV232

CV215

V1
V2 NC_V1
NC_V2 2 2 2
D D
DIS@

DIS@

DIS@

W1
W2 NC_W1
W3 NC_W2
W4 NC_W3
NC_W4

Security Classification LC Future Center Secret Data Title

N15S-GM-A1_FCBGA595 N16S-GT Core Power
Issued Date 2015/08/28 Deciphered Date 2016/08/27
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 29 of 82
1 2 3 4 5
 5 4 3 2 1

D D

UV1F

N15S-GM-A1_FCBGA_595P
COMMON
13/14 GND
A2 M13
AB17 GND_001 GND_071 M15
AB20 GND_005 GND_072 M17
AB24 GND_006 GND_073 N10
AC2 GND_007 GND_074 N12
AC22 GND_008 GND_075 N14
AC26 GND_009 GND_076 N16
AC5 GND_010 GND_077 N18
AC8 GND_011 GND_078 P11
AD12 GND_012 GND_079 P13
AD13 GND_013 GND_080 P15
A26 GND_014 GND_081 P17
AD15 GND_002 GND_082 P2
AD16 GND_015 GND_083 P23
AD18 GND_016 GND_084 P26
AD19 GND_017 GND_085 P5
AD21 GND_018 GND_086 R10
AD22 GND_019 GND_087 R12
AE11 GND_020 GND_088 R14
AE14 GND_021 GND_089 R16
AE17 GND_022 GND_090 R18
AE20 GND_023 GND_091 T11
AB11 GND_024 GND_092 T13
AF1 GND_003 GND_093 T15
AF11 GND_025 GND_094 T17
AF14 GND_026 GND_095 U10
C
AF17 GND_027 GND_096 U12 C
AF20 GND_028 GND_097 U14
AF23 GND_029 GND_098 U16
AF5 GND_030 GND_099 U18
AF8 GND_031 GND_100 U2
AG2 GND_032 GND_101 U23
AG26 GND_033 GND_102 U26
AB14 GND_034 GND_103 U5
B1 GND_004 GND_104 V11
B11 GND_035 GND_105 V13
B14 GND_036 GND_106 V15
B17 GND_037 GND_107 V17
B20 GND_038 GND_108 Y2
B23 GND_039 GND_109 Y23
B27 GND_040 GND_110 Y26
B5 GND_041 GND_111 Y5
B8 GND_042 GND_112
E11 GND_043
E14 GND_044
E17 GND_045
E2 GND_046
E20 GND_047
E22 GND_048
E25 GND_049
E5 GND_050
E8 GND_051
H2 GND_052
H23 GND_053
H25 GND_054
H5 GND_055
K11 GND_056
K13 GND_057
K15 GND_058
K17 GND_059
L10 GND_060
B B
L12 GND_061
L14 GND_062
L16 GND_063
L18 GND_064
L2 GND_065
L23 GND_066
L25 GND_067
L5 GND_068 AA7
M11 GND_069 GND_AA7 AB7
GND_070 GND_AB7

N15S-GM-A1_FCBGA595

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 30 of 82

5 4 3 2 1
 1 2 3 4 5

Memory Partition A - Lower 32 bits

FBA_MA[14..0] [27,32]
UV5 X76@
UV4 X76@
+FBA_VREFCA0 FBA_D9 FBA_BA[2..0] [27,32]
M8 E3
+FBA_VREFCA0 M8 E3 FBA_D2 +FBA_VREFDQ0 H1 VREFCA DQL0 F7 FBA_D10
+FBA_VREFDQ0 VREFCA DQL0 FBA_D5 VREFDQ DQL1 FBA_D12 FBA_DQS[7..0] [27,32]
H1 F7 F2
VREFDQ DQL1 F2 FBA_D7 FBA_MA0 N3 DQL2 F8 FBA_D8
A
FBA_MA0 DQL2 FBA_D4 FBA_MA1 A0 DQL3 FBA_D11
Byte1 FBA_DQM[7..0] [27,32] A
N3 F8 P7 H3
FBA_MA1 P7 A0 DQL3 H3 FBA_D3 FBA_MA2 P3 A1 DQL4 H8 FBA_D13
FBA_MA2 A1 DQL4 FBA_D1
Byte 0 FBA_MA3 A2 DQL5 FBA_D15 FBA_DQS#[7..0] [27,32]
P3 H8 N2 G2
FBA_MA3 N2 A2 DQL5 G2 FBA_D0 FBA_MA4 P8 A3 DQL6 H7 FBA_D14
FBA_MA4 A3 DQL6 FBA_D6 FBA_MA5 A4 DQL7 FBA_D[0..63] [27,32]
P8 H7 P2
FBA_MA5 P2 A4 DQL7 FBA_MA6 R8 A5
FBA_MA6 R8 A5 FBA_MA7 R2 A6 D7 FBA_D20
FBA_MA7 R2 A6 D7 FBA_D31 FBA_MA8 T8 A7 DQU0 C3 FBA_D16
FBA_MA8 T8 A7 DQU0 C3 FBA_D27 FBA_MA9 R3 A8 DQU1 C8 FBA_D23
FBA_MA9 R3 A8 DQU1 C8 FBA_D30 FBA_MA10 L7 A9 DQU2 C2 FBA_D19
FBA_MA10 A9 DQU2 FBA_D25 FBA_MA11 A10/AP DQU3 FBA_D21
Byte2
L7 C2 R7 A7
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D28 FBA_MA12 N7 A11 DQU4 A2 FBA_D18
FBA_MA12 A11 DQU4 FBA_D26
Byte3 FBA_MA13 A12/BC DQU5 FBA_D22
N7 A2 T3 B8
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D29 FBA_MA14 T7 A13 DQU6 A3 FBA_D17
FBA_MA14 T7 A13 DQU6 A3 FBA_D24 A14 DQU7
A14 DQU7 +1.5VS_VGA
+1.5VS_VGA
FBA_BA0 M2 B2 +1.5VS_VGA
FBA_BA0 M2 B2 FBA_BA1 N8 BA0 VDD_1 D9
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA2 M3 BA1 VDD_2 G7

RV702

1.33K_0402_1%
FBA_BA2 BA1 VDD_2 BA2 VDD_3

1
M3 G7 K2
BA2 VDD_3 K2 VDD_4 K8
VDD_4 K8 VDD_5 N1
VDD_5 N1 FBA_CLKA0 J7 VDD_6 N9

DIS@
FBA_CLKA0 J7 VDD_6 N9 FBA_CLKA0# K7 CK VDD_7 R1
[27] FBA_CLKA0 CK VDD_7 CK VDD_8

2
FBA_CLKA0# K7 R1 FBA_CKEA0 K9 R9 +FBA_VREFCA0
[27] FBA_CLKA0# FBA_CKEA0 CK VDD_8 CKE VDD_9
K9 R9
[27] FBA_CKEA0 CKE VDD_9

DIS@ RV701

1.33K_0402_1%
FBA_ODTA0

1
K1 A1 1
FBA_ODTA0 K1 A1 FBA_CSA0# L2 ODT VDDQ_1 A8 DIS@
[27] FBA_ODTA0 FBA_CSA0# ODT VDDQ_1 FBA_RAS# CS VDDQ_2
L2 A8 J3 C1 CV701
[27] FBA_CSA0# FBA_RAS# CS VDDQ_2 FBA_CAS# RAS VDDQ_3 .01U_0402_16V7-K
J3 C1 K3 C9
[27,32] FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_WE# CAS VDDQ_4 2
K3 C9 L3 D2
[27,32] FBA_CAS# CAS VDDQ_4 WE VDDQ_5

2
FBA_WE# L3 D2 E9
B [27,32] FBA_WE# WE VDDQ_5 VDDQ_6 B
E9 F1
VDDQ_6 F1 FBA_DQS1 F3 VDDQ_7 H2
FBA_DQS0 F3 VDDQ_7 H2 FBA_DQS2 C7 DQSL VDDQ_8 H9
FBA_DQS3 C7 DQSL VDDQ_8 H9 DQSU VDDQ_9
DQSU VDDQ_9
FBA_DQM1 E7 A9
FBA_DQM0 E7 A9 FBA_DQM2 D3 DML VSS_1 B3 +1.5VS_VGA
FBA_DQM3 D3 DML VSS_1 B3 DMU VSS_2 E1
DMU VSS_2 E1 VSS_3 G8

RV703

1.33K_0402_1%
VSS_3 FBA_DQS#1 VSS_4

1
G8 G3 J2
FBA_DQS#0 G3 VSS_4 J2 FBA_DQS#2 B7 DQSL VSS_5 J8
FBA_DQS#3 B7 DQSL VSS_5 J8 DQSU VSS_6 M1
DQSU VSS_6 M1 VSS_7 M9

DIS@
VSS_7 M9 VSS_8 P1
VSS_8 VSS_9

2
P1 FBA_RST# T2 P9 +FBA_VREFDQ0
FBA_RST# T2 VSS_9 P9 RESET VSS_10 T1
[27,32] FBA_RST# RESET VSS_10 VSS_11
T1 L8 T9

RV704

1.33K_0402_1%
VSS_11 ZQ VSS_12

1
L8 T9 1
ZQ VSS_12 DIS@
J1 B1 CV702
NC1 VSSQ_1
1

1
J1 B1 L1 B9 .01U_0402_16V7-K

DIS@
RV705 L1 NC1 VSSQ_1 B9 RV706 J9 NC2 VSSQ_2 D1 2
NC2 VSSQ_2 NC3 VSSQ_3

2
243_0402_1% J9 D1 243_0402_1% L9 D8
DIS@ L9 NC3 VSSQ_3 D8 DIS@ M7 NC4 VSSQ_4 E2
M7 NC4 VSSQ_4 E2 NC5 VSSQ_5 E8
NC5 VSSQ_5 VSSQ_6
2

2
E8 F9
VSSQ_6 F9 VSSQ_7 G1
VSSQ_7 G1 VSSQ_8 G9
VSSQ_8 G9 VSSQ_9
VSSQ_9 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W4G1646D-BC1A_FBGA96
K4W4G1646D-BC1A_FBGA96
FBA_CLKA0
C C

1
+1.5VS_VGA UV4 SIDE
+1.5VS_VGA UV5 SIDE RV708

DIS@
CV720 CV721 CV706 CV707 CV708 CV709 CV704 162_0402_1%
CV723 CV722 CV712 CV713 CV714 CV715 CV710
0.1U_0402_10V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M

2
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M
1 1 1 1 1 1 1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
2 2 2 2 2 2 2

FBA_CLKA0#

Under UV4 Under UV5

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT DDR3L VRAM L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 31 of 82
1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Upper 32 bits

UV7 X76@
FBA_MA[14..0] [27,31]
UV6 X76@
+FBA_VREFCA1 M8 E3 FBA_D32
+FBA_VREFDQ1 VREFCA DQL0 FBA_D39 +FBA_VREFCA1 FBA_D52 FBA_BA[2..0] [27,31]
H1 F7 M8 E3
VREFDQ DQL1 F2 FBA_D35 +FBA_VREFDQ1 H1 VREFCA DQL0 F7 FBA_D53
A A
FBA_MA0 DQL2 FBA_D36 VREFDQ DQL1 FBA_D49 FBA_DQS[7..0] [27,31]
N3 F8 F2
FBA_MA1 P7 A0 DQL3 H3 FBA_D37 FBA_MA0 N3 DQL2 F8 FBA_D50
FBA_MA2 A1 DQL4 FBA_D33
Byte 4 FBA_MA1 A0 DQL3 FBA_D54 FBA_DQM[7..0] [27,31]
P3 H8 P7 H3 Byte6
FBA_MA3 N2 A2 DQL5 G2 FBA_D34 FBA_MA2 P3 A1 DQL4 H8 FBA_D48
FBA_MA4 A3 DQL6 FBA_D38 FBA_MA3 A2 DQL5 FBA_D55 FBA_DQS#[7..0] [27,31]
P8 H7 N2 G2
FBA_MA5 P2 A4 DQL7 FBA_MA4 P8 A3 DQL6 H7 FBA_D51
FBA_MA6 A5 FBA_MA5 A4 DQL7 FBA_D[0..63] [27,31]
R8 P2
FBA_MA7 R2 A6 D7 FBA_D56 FBA_MA6 R8 A5
FBA_MA8 T8 A7 DQU0 C3 FBA_D60 FBA_MA7 R2 A6 D7 FBA_D44
FBA_MA9 R3 A8 DQU1 C8 FBA_D58 FBA_MA8 T8 A7 DQU0 C3 FBA_D40
FBA_MA10 L7 A9 DQU2 C2 FBA_D62 FBA_MA9 R3 A8 DQU1 C8 FBA_D46
FBA_MA11 R7 A10/AP DQU3 A7 FBA_D57 FBA_MA10 L7 A9 DQU2 C2 FBA_D41
FBA_MA12 A11 DQU4 FBA_D63
Byte7 FBA_MA11 A10/AP DQU3 FBA_D45
N7 A2 R7 A7 Byte5
FBA_MA13 T3 A12/BC DQU5 B8 FBA_D59 FBA_MA12 N7 A11 DQU4 A2 FBA_D43 +1.5VS_VGA
FBA_MA14 T7 A13 DQU6 A3 FBA_D61 FBA_MA13 T3 A12/BC DQU5 B8 FBA_D47
A14 DQU7 FBA_MA14 T7 A13 DQU6 A3 FBA_D42

RV802

1.33K_0402_1%
+1.5VS_VGA A14 DQU7

1
+1.5VS_VGA
FBA_BA0 M2 B2
FBA_BA1 N8 BA0 VDD_1 D9 FBA_BA0 M2 B2

DIS@
FBA_BA2 M3 BA1 VDD_2 G7 FBA_BA1 N8 BA0 VDD_1 D9
BA2 VDD_3 BA1 VDD_2

2
K2 FBA_BA2 M3 G7 +FBA_VREFCA1
VDD_4 K8 BA2 VDD_3 K2
VDD_5 N1 VDD_4 K8

DIS@ RV801

1.33K_0402_1%
FBA_CLKA1 J7 VDD_6 VDD_5

1
N9 N1 1
[27] FBA_CLKA1 FBA_CLKA1# K7 CK VDD_7 FBA_CLKA1 VDD_6
R1 J7 N9 DIS@
[27] FBA_CLKA1# FBA_CKEA1 K9 CK VDD_8 FBA_CLKA1# CK VDD_7
R9 K7 R1 CV801
[27] FBA_CKEA1 CKE VDD_9 FBA_CKEA1 CK VDD_8 .01U_0402_16V7-K
K9 R9
CKE VDD_9 2

2
FBA_ODTA1 K1 A1
[27] FBA_ODTA1 FBA_CSA1# ODT VDDQ_1 FBA_ODTA1
L2 A8 K1 A1
[27] FBA_CSA1# FBA_RAS# CS VDDQ_2 FBA_CSA1# ODT VDDQ_1
J3 C1 L2 A8
[27,31] FBA_RAS# FBA_CAS# RAS VDDQ_3 FBA_RAS# CS VDDQ_2
K3 C9 J3 C1
[27,31] FBA_CAS# FBA_WE# CAS VDDQ_4 FBA_CAS# RAS VDDQ_3
L3 D2 K3 C9
B [27,31] FBA_WE# WE VDDQ_5 FBA_WE# CAS VDDQ_4 B
E9 L3 D2
VDDQ_6 F1 WE VDDQ_5 E9
FBA_DQS4 F3 VDDQ_7 H2 VDDQ_6 F1 +1.5VS_VGA
FBA_DQS7 C7 DQSL VDDQ_8 H9 FBA_DQS6 F3 VDDQ_7 H2
DQSU VDDQ_9 FBA_DQS5 C7 DQSL VDDQ_8 H9

RV803

1.33K_0402_1%
DQSU VDDQ_9

1
FBA_DQM4 E7 A9
FBA_DQM7 D3 DML VSS_1 B3 FBA_DQM6 E7 A9
DMU VSS_2 E1 FBA_DQM5 D3 DML VSS_1 B3

DIS@
VSS_3 G8 DMU VSS_2 E1
VSS_4 VSS_3

2
FBA_DQS#4 G3 J2 G8 +FBA_VREFDQ1
FBA_DQS#7 B7 DQSL VSS_5 J8 FBA_DQS#6 G3 VSS_4 J2
DQSU VSS_6 M1 FBA_DQS#5 B7 DQSL VSS_5 J8

RV804

1.33K_0402_1%
VSS_7 DQSU VSS_6

1
M9 M1 1
VSS_8 P1 VSS_7 M9 DIS@
FBA_RST# T2 VSS_9 P9 VSS_8 P1 CV802
[27,31] FBA_RST# RESET VSS_10 FBA_RST# VSS_9 .01U_0402_16V7-K
T1 T2 P9

DIS@
L8 VSS_11 T9 RESET VSS_10 T1 2
ZQ VSS_12 VSS_11

2
L8 T9
ZQ VSS_12
1

J1 B1
NC1 VSSQ_1

1
RV805 L1 B9 J1 B1
243_0402_1% J9 NC2 VSSQ_2 D1 RV806 L1 NC1 VSSQ_1 B9
DIS@ L9 NC3 VSSQ_3 D8 243_0402_1% J9 NC2 VSSQ_2 D1
M7 NC4 VSSQ_4 E2 DIS@ L9 NC3 VSSQ_3 D8
NC5 VSSQ_5 NC4 VSSQ_4
2

E8 M7 E2
VSSQ_6 NC5 VSSQ_5

2
F9 E8 FBA_CLKA1
VSSQ_7 G1 VSSQ_6 F9
VSSQ_8 G9 VSSQ_7 G1
VSSQ_9 VSSQ_8 G9
96-BALL VSSQ_9
SDRAM DDR3 96-BALL

1
K4W4G1646D-BC1A_FBGA96 SDRAM DDR3
K4W4G1646D-BC1A_FBGA96 RV808

DIS@
C 162_0402_1% C

2
+1.5VS_VGA UV7 SIDE
+1.5VS_VGA UV6 SIDE
CV817 CV816 CV806 CV807 CV808 CV809 CV804
CV823 CV822 CV812 CV813 CV814 CV815 CV810 FBA_CLKA1#
0.1U_0402_10V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M
1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

10U_0603_6.3V6-M
1 1 1 1 1 1 1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
1 1 1 1 1 1 1
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

2 2 2 2 2 2 2

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
2 2 2 2 2 2 2

Under UV7

Under UV6

D D

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT DDR3L VRAM U
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 32 of 82
1 2 3 4 5
 1 2 3 4 5

+3VS to +3VS_AON +5VALW +3VS +3VS_AON

+1.5VS_VGA

1
3 1

D
RV916
DIS@ 47K_0402_5% QV6
AO3413_SOT23-3

G
2

1
DIS@ DIS@

2
RV917 RV923
470_0402_5% 100_0603_5%

2
DIS@
A RV914 A

2
10K_0402_5%
DIS@

1
D

1
DGPU_PWREN_AON# 2DGPU_PWREN_AON#_R

6
D RV909 QV104
QV12A 2DGPU_PWREN_AON#_R 2 1 DGPU_PWREN_AON# 2N7002KW_SOT323-3 G
2N7002KDWH_SOT363-6 G DIS@

3
D 1 10K_0402_5% S

3
VGA_APWR_ON 5 QV12B CV909 DIS@ S DIS@
[9,75] VGA_APWR_ON

1
G 2N7002KDWH_SOT363-6 0.1U_0402_16V7-K

1
From PCH GPIO PIN RV915 S
DIS@
2
DIS@ SB00000YS00

4
100K_0402_5%
@
SB00000YS00

2
RV918 GC6@

0_0402_5%
+3VS_VGA [28] VGA_MPWR_ON
VGA_MPWR_ON 2 1
VGA_ON [28,75]
VGA_APWR_ON 2 1

RV919 NGC6@
B B
0_0402_5%
+5VALW +3VS_AON +3VS_VGA
1

3 1 RV921 1 2 0_0805_5%
S

RV903
DIS@ 47K_0402_5% QV5 DIS@
AO3413_SOT23-3
G
2

2
DIS@ DIS@
2

RV907
470_0402_5%
2

RV904

1
10K_0402_5%
DIS@
1

DGPU_PWREN_MAIN# 6 D RV908
QV8A 2DGPU_PWREN_MAIN#_R 2 1 DGPU_PWREN_MAIN#
2N7002KDWH_SOT363-6 G
3

D 1 10K_0402_5%
VGA_ON 0_0402_5% 1 2 RV905 5 QV8B CV908 DIS@ S DIS@
1

G 2N7002KDWH_SOT363-6 0.1U_0402_16V7-K
1

DIS@
RV906 S
DIS@
2
DIS@ SB00000YS00
4

100K_0402_5%
@
SB00000YS00
2

C C

+1VALW to +1VS_VGA
+5VS +1VALW +1VS_VGA

QV9 DIS@
AO4430L_SO8
8 1
7 2
+5VALW
1

6 3
RV901 5
10K_0402_5% 1 1
DIS@ CV902 CV903
4

4.7U_0603_6.3V6-K 0.1U_0402_10V7-K
2

+0.95VS_VGA_GATE_R RV910 DIS@ @

2 2
1

300_0402_5%
2

RV912 DIS@
100K_0402_5%
0_0402_5%
1

DIS@
RV902
2

+0.95VS_VGA_GATE D
1

RV911
QV11 2 DGPU_PWREN#_R 2 1 DGPU_PWREN#
2N7002KW_SOT323-3 G
3

D 1 SB00000YY00 S 10K_0402_5%
3

DGPU_PWREN# 5 QV10B CV901 DIS@ DIS@

G 2N7002KDWH_SOT363-6 DIS@ 0.22U_0402_10V6-K
DIS@
S 2
4

D D
6

VGA_ON 2
D SB00000YS00
QV10A
G 2N7002KDWH_SOT363-6
S DIS@
1

SB00000YS00
Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/28 Deciphered Date 2016/08/27 N16S-GT swich power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 33 of 82
1 2 3 4 5
 5 4 3 2 1

I/O Termination
GPIO I/O Functional Description
GPIO0
O FB Enable for GC6 2.0, Open source 10K pull-down
Pull-up/pull down to set the FBVDD/Q
GPIO1 boot voltage
O Memory voltage control
GPIO2
T1>0
O Panel Backlight PWM Brightness Control 100K pull down
GPIO3
O Panel Power Enable 100K pull down
D GPIO4 O All GPU Power Stable D
Panel Backlight Enable 100K pull down
GPIO5
O GPU Power Sequence for GC6 2.0, Open Drain 10k pull-up to 3V3_AON
GPIO6
T2>0
I GPU wake signal for GC6 2.0 10k pull-up to 3V3_AON
GPIO7
PLT_RST#
O 3D Vision L/R signal 100K pull down
GPIO8
O System side PCIe rest monitor 10k pull-up to 3V3_AON
GPIO9
I/O Active low thermal alert, open drain 10k pull-up to 3V3_AON
GPIO10
GPU PCIE Reset
O Memory VREF Control 100K pull down
GPIO11
O GPU Core VDD PWM control signal
GPIO12
I AC power detect or power supply overdraw input 100k pull-up to 3V3_AON Cold boot reset
GPIO13 10K pull-up to 3V3_AON to
O Phase Shedding enable two phase
GPIO14 Hot Plug Detect for IFPA used as DisplayPort
I for IFPAB when used as Dual Link DVI
GPIO15
I Hot Plug Detect for IFPC
GPIO16
I Active Low Frame Lock, Open Drain 10k pull-up to 3V3_AON
GPIO17
I Hot Plug Detect for IFPD
GPIO18
I Hot Plug Detect for IFPE PEX_RST#
Hot Plug Detect for IFPF or for IPFB 0<T0<5ms
GPIO19 T1
C GPIO20
GPIO21
I

O
when used as DisplayPort

Reserved

GPU PCIe self-reset control, Open Drain 10k pull-up to 3V3_AON VGA_PWR_EN
T0
... C

OVERT
I/O Catastrophic Over Temperature 100k pull-up to 3V3_AON

All_VGA_PWRGD
...
FB_CKE
Normal Self-refresh
...
Self-refresh Normal
...
PCIE LINK

PCIE LINK
X ... X

Active X ... X Detect Train GPU POWER OFF GPU POWER ON

Optimus entry and exit sequence

PEX_RST#

B
... B

...
GC6_FB_EN

3VS_MAIN_EN
...
All_VGA_PWRGD
T1 0.04<T1<4ms

...
VGA_EVENT#
T0
GC6 entry GC6 exit

GC6 entry and exit sequence T0>0.001ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/28 Deciphered Date 2016/08/27 GPU GPIO table & sequence
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 34 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 35 of 82
5 4 3 2 1
 5 4 3 2 1

L2 EMC@ L3 EMC@
HDMI_TX0- 1 2 HDMI_TX0-_CON HDMI_TX2- 1 2 HDMI_TX2-_CON
1 2 1 2

HDMI_TX0+ 4 3 HDMI_TX0+_CON HDMI_TX2+ 4 3 HDMI_TX2+_CON

4 3 4 3
EXC24CH900U_4P EXC24CH900U_4P

D D
L4 EMC@ L5 EMC@
HDMI_TX1- 1 2 HDMI_TX1-_CON HDMI_TXC- 1 2 HDMI_TXC-_CON
1 2 1 2

HDMI_TX1+ 4 3 HDMI_TX1+_CON HDMI_TXC+ 4 3 HDMI_TXC+_CON

4 3 4 3
EXC24CH900U_4P EXC24CH900U_4P

+3VS HDMI_HPD_CON R510 1 2 100K_0402_5%

D1 RCLAMP0524PATCT_SLP2510P8-10-9
@
1U_0402_6.3V6-K C361

+5VS_HDMI 9 1 +5VS_HDMI
HDMI_HPD_CON 8 2 HDMI_HPD_CON
HDMI_CLK_CON 7 4 HDMI_CLK_CON
HDMI_DAT_CON 6 5 HDMI_DAT_CON
U15
+5VS 11
HDMI_DAT 1 GND 10 HDMI_DAT_CON +5VS_HDMI
[5] HDMI_DAT HDMI_CLK A1 B1 HDMI_CLK_CON
2 9
[5] HDMI_CLK HDMI_HPD A2 B2 HDMI_HPD_CON
EMC@ 3 8
[5] HDMI_HPD HPDO HPDI
3

4 7
5 VCCA NC 6
IN OUT
G5260ARE1U_TDFN10_3X3 1
C360 C362
1U_0402_6.3V6-K 22U_0603_6.3V6-M
C 2 C
D3 RCLAMP0524PATCT_SLP2510P8-10-9

HDMI_TXC+_CON 9 1 HDMI_TXC+_CON
HDMI_TXC-_CON 8 2 HDMI_TXC-_CON
HDMI_TX0+_CON 7 4 HDMI_TX0+_CON
HDMI_TX0-_CON 6 5 HDMI_TX0-_CON
+5VS_HDMI

PCH_HDMI_TX0+ C371 1 2 0.1U_0402_10V7-K HDMI_TX0+

[5] PCH_HDMI_TX0+
EMC@
3

[5] PCH_HDMI_TX0-
PCH_HDMI_TX0- C370 1 2 0.1U_0402_10V7-K HDMI_TX0- HDMI CONN.
JHDMI1 ME@
HDMI_HPD_CON 19
PCH_HDMI_TX1+ C372 1 2 0.1U_0402_10V7-K HDMI_TX1+ 18 HP_DET
[5] PCH_HDMI_TX1+ +5V
17
D4 RCLAMP0524PATCT_SLP2510P8-10-9 HDMI_DAT_CON 16 DDC/CEC_GND
HDMI_CLK_CON 15 SDA
PCH_HDMI_TX1- C373 1 2 0.1U_0402_10V7-K HDMI_TX1- 14 SCL
[5] PCH_HDMI_TX1- Reserved
13
HDMI_TX1-_CON 9 1 HDMI_TX1-_CON HDMI_TXC-_CON 12 CEC 20
HDMI_TX1+_CON 8 2 HDMI_TX1+_CON 11 CK- GND1 21
HDMI_TX2-_CON 7 4 HDMI_TX2-_CON PCH_HDMI_TX2+ C374 1 2 0.1U_0402_10V7-K HDMI_TX2+ HDMI_TXC+_CON 10 CK_shield GND2 22
HDMI_TX2+_CON HDMI_TX2+_CON [5] PCH_HDMI_TX2+ HDMI_TX0-_CON CK+ GND3
6 5 9 23
8 D0- GND4
HDMI_TX0+_CON 7 D0_shield
PCH_HDMI_TX2- C375 1 2 0.1U_0402_10V7-K HDMI_TX2- HDMI_TX1-_CON 6 D0+
[5] PCH_HDMI_TX2- D1-
5
EMC@ HDMI_TX1+_CON 4 D1_shield
B B
D1+
3

HDMI_TX2-_CON 3
PCH_HDMI_TXC+ C377 1 2 0.1U_0402_10V7-K HDMI_TXC+ 2 D2-
[5] PCH_HDMI_TXC+ HDMI_TX2+_CON D2_shield
1
D2+
SINGA_2HE3Y37-000111F
PCH_HDMI_TXC- C376 1 2 0.1U_0402_10V7-K HDMI_TXC-
[5] PCH_HDMI_TXC-
475_0402_1%

475_0402_1%

475_0402_1%

475_0402_1%

475_0402_1%

475_0402_1%

475_0402_1%

475_0402_1%
1

1
R402

R403

R404

R405

R409

R406

R408

R407
2

2
+3VS
1

D
2
G 2N7002KW_SOT323-3
Q8
S
3

Need to confirm if 2n7002 can be used here.

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 36 of 82
5 4 3 2 1
 5 4 3 2 1

Touch Panel +3VS

2
L27
USB20_N5 1 2 USB20_N5_CON R177
[15] USB20_N5 1 2
10K_0402_5%
TS@
LCDVDD Circuit [15] USB20_P5
USB20_P5 4
4 3
3 USB20_P5_CON

1
EXC24CH900U_4P
+LCDVDD_CON TS@
EMC_TP@
+3VS R315 1 2 0_0402_5% TS_OFF#
D
U1 2A 80 mil [14] PCH_TSOFF# D
2A 80 mil 20160621
5 1 +LCDVDD_CON
IN OUT Mount L27 as EMC_TP@ for EMI
When lid# active. BIOS turn off touch screen.
1 2
GND
C62 PCH_ENVDD 4 3

4.7U_0603_6.3V6-K
[5] PCH_ENVDD EN OC
1U_0402_6.3VA-K 1
2
From PCH G524B1T11U_SOT23-5 C64

1
R72 2
@
100K_0402_5%
CMOS Camera

2
For 2D CCD
+3VS CMOS_VDD
2DCCD@
R70 1 2 0_0402_5%

C C

B+ +LEDVDD
R73
CMOS USB Port 2A 80 mil 0_0805_5% 2A 80 mil
1 2 C66

L32

4.7U_0805_25V6-K
USB20_N7 1 2 USB20_N7_CMOS
1 1
1 2 eDP CONN.
C67 EMC_NS@
USB20_P7 4 3 USB20_P7_CMOS 2200P_0402_50V7-K
4 3 2 2 I-PEX_20439-040E-01
EXC24CH900U_4P +LEDVDD W= 80 mil 40 51
39 40 GND11 50
Co-lay R414/R415 38 39 GND10 49
W= 60 mil 37 38 GND9 48
20160621 +LCDVDD_CON
36 37 GND8 47
Mount L32 for EMI issue CMOS_VDD 35 36 GND7 46
R75 1 2 0_0402_5% +3VDMIC 34 35 GND6 45
1 +3VS W= 40 mil
+3VS R395 1 2 0_0402_5% +3VS_TOUCH
W= 50 mil 33 34 GND5 44
EMC_NS@ C68 +3VS R350 1 2 0_0402_5% +3VS_IR 32 33 GND4 43
+3VALW 2200P_0402_50V7-K R525 1 @ 2 2.2K_0402_1% LOGO_LED_CON 31 32 GND3 42
+3VALW
[15] USB20_N7
USB20_N7 R414 1 2 0_0402_5% USB20_N7_CMOS 2
[51] DMIC_DATA
DMIC_DATA 30 31 GND2 41
DMIC_CLK 29 30 GND1
[51] DMIC_CLK TS_OFF# 28 29

1
@
[15] USB20_P7
USB20_P7 R415 1 2 0_0402_5% USB20_P7_CMOS CPU_EDP_HPD 27 28
2.2K_0402_1% [5] CPU_EDP_HPD
[5] PCH_EDP_PWM
PCH_EDP_PWM 26 27
@ R78
[57] BKOFF# BKOFF# 25 26
2D camera module mount choke already @ @ 24 25
23 24

2
Q29 22 23
2N7002KW_SOT323-3 USB20_N7_CMOS 21 22

1
D
[57] LOGO_LED#
LOGO_LED# 2 USB20_P7_CMOS 20 21
B G 19 20 B
USB20_N5_CON 18 19
S USB20_P5_CON 17 18
16 17

3
R516 1.5K_0402_5% CPU_EDP_AUX# C69 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON 15 16

LOGO_LED_CON
[5] CPU_EDP_AUX#
1 2 CPU_EDP_AUX C70 1 2 0.1U_0402_10V7-K CPU_EDP_AUX_CON 14 15
[5] CPU_EDP_AUX
13 14
CPU_EDP_TX1- C71 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 12 13
[5] CPU_EDP_TX1- CPU_EDP_TX1+ C72 1 2 0.1U_0402_10V7-K CPU_EDP_TX1+_CON 11 12
[5] CPU_EDP_TX1+
10 11
IR camera USB Port [5] CPU_EDP_TX0-
CPU_EDP_TX0- C73 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 9 10
CPU_EDP_TX0+ C74 1 2 0.1U_0402_10V7-K CPU_EDP_TX0+_CON 8 9
[5] CPU_EDP_TX0+
7 8
L28 20160424 USB20_N8_IR 6 7
USB20_N8 1 2 USB20_N8_IR USB20_P8_IR 5 6
[15] USB20_N8 1 2 1. Change R516 from 100 to 1.5Kohm 4 5
for LED brightness 3 4
USB20_P8 4 3 USB20_P8_IR 2 3
[15] USB20_P8 4 3 1 2
EXC24CH900U_4P 1
+3VS_TOUCH JLCD1 ME@
EMC_IR@

1
R77 2 1 100K_0402_5% BKOFF# EMC_NS@
C421
2200P_0402_50V7-K
2

ESD request
+3VDMIC +3VS_IR

1 1
EMC_NS@ EMC_NS@
LOGO_LED# C422 C420
A A
2200P_0402_50V7-K 2200P_0402_50V7-K
2 2
3

D5
EMC@
PESD5V0U2BT_SOT23-3
1

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 eDP CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 37 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2014/09/07 HDMI RP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 38 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 CRT CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 39 of 82
5 4 3 2 1
 2 1

B B

BLANK

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 DP to VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 40 of 82
2 1
 A B C D E F G H

1 1

2 2

BLANK

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 Mux IC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 41 of 82
A B C D E F G H
 5 4 3 2 1

D D
SATA HDD CONN.
HIGHS_FC5AF141-3181H

14 16
SATA_PTX_DRX_P0 C79 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 13 14 GND16 15
[15] SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 13 GND15
[15] SATA_PTX_DRX_N0 C77 1 2 .01U_0402_16V7-K 12
11 12
SATA_PRX_DTX_N0 C80 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 10 11

+5VS
SATA HDD CONN. [15]
[15]
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PRX_DTX_P0 C81 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 9
8
10
9
HDD_DEVSLP0 7 8
[15] HDD_DEVSLP0 HDD_DETECT# 7
6
[57] HDD_DETECT# 5 6
4 5
3 4
+5VS 3
1 1 1 1 2
C78 C82 C83 C84 1 2
@ @ @ 1
10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6-K 0.1U_0402_25V6-K
2 2 2 2 JHDD1 ME@

C C

R305
1A
1 @ 2
+3VS +3.3V_NGFF
0_0603_5%

22U_0603_6.3V6-M
1 1

C302
C301 SSD@
SSD@
0.1U_0402_25V6-K
2 2 M.2 SSD(SATA/PCIE)

B SSD@ R306 +3.3V_NGFF B

SSD_DEVSLP1 2 1 SSD_DEVSLP1_R
[15] SSD_DEVSLP1
0_0402_5%

@ FOX_GS12301-10111-9H
CLK_PCIE_SSD# 30 34
[10] CLK_PCIE_SSD# CLK_PCIE_SSD 30 GND4
29 33
[10] CLK_PCIE_SSD 29 GND3
28 32
PCIE_PTX_DRX_P11 C501 2 1 0.22U_0402_10V6-K PCIE_PTX_C_DRX_P11 27 28 GND2 31
20160308 [15] PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_N11 27 GND1
C500 2SSD@1 0.22U_0402_10V6-K 26
1. Remove R300,R301,R302 and put it to CPU side [15] PCIE_PTX_DRX_N11
SSD@ 25 26
PCIE_PRX_DTX_N11 24 25
[15] PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 24
23
[15] PCIE_PRX_DTX_P11 23
22
PCIE_PTX_DRX_P12 C503 2 1 0.22U_0402_10V6-K PCIE_PTX_C_DRX_P12 21 22
[15] PCIE_PTX_DRX_P12 PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_N12 21
C502 2SSD@1 0.22U_0402_10V6-K 20
[15] PCIE_PTX_DRX_N12 20
SSD@ 19
PCIE_PRX_DTX_N12 18 19
[15] PCIE_PRX_DTX_N12 PCIE_PRX_DTX_P12 18
17
[15] PCIE_PRX_DTX_P12 17
16
PLT_RST# 15 16
[12,28,46,48,49,57,58] PLT_RST# CLKREQ#_PCIE1_SSD 15
14
[10] CLKREQ#_PCIE1_SSD SSD_DEVSLP1_R 14
13
SSD_DET 12 13
SSD_DET_EC# 11 12
[57] SSD_DET_EC# 11
10
9 10
20160121 9
8
R304
1. Follow M.2 adpater pin define to 7 8
SSD_DET# 2 1 SSD_DET modify pin assignment 6 7
[15] SSD_DET# 6
5
0_0402_5% 4 5
3 4
3
2

2
A
R303 1 2 A
1
10K_0402_5% @ PEDET (PE_DTCT) JSSD1
SATA Device GND
PCIe Device Open
1

SSD_DET#
0 - SATA Security Classification LC Future Center Secret Data Title
1 - PCIE Issued Date 2015/09/01 Deciphered Date 2016/12/31 SATA HDD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 42 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 ODD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 43 of 82
5 4 3 2 1
 5 4 3 2 1

USB3 PORT4 POWER SWITCH

+5VALW +USB_VCCA

D6 +USB_VCCA
W=80mils U4
5 1
W=80mils
IN OUT 1 USB3P4_TXP_CON
2 CH1
GND 1
EMC@ USB3P4_TXP_CON 9 2 USB3P4_TXN_CON
1 1 NC_4 CH2 1
C91 USB_ON# 4 3 USB_OC2# C92 + C94 C93
[57] USB_ON# EN OC USB_OC2# [15] USB3P4_TXN_CON
1U_0402_10V6-K EMC@ 8
NC_3

2
G524B2T11U_SOT23-5 0.1U_0402_10V6-K 150U_B2_6.3VM_R35M 470P_0402_50V7-K
2 R220 2 3 2 2
Low Act i ve 2. 5A VN
D 0_0402_5% D
USB3P4_RXP_CON 7
USB_OC3# NC_2
USB_OC3# [15]

1
20160616 USB3P4_RXN_CON 6 4 USB3P4_RXP_CON
NC_1 CH3
Change C91 for 0.1U_0402_10V6-K to 1U_0402_10V6-K EMC@
5 USB3P4_RXN_CON
CH4

EXC24CH900U_4P
USB3P4_TXP USB3P4_TXP_C USB3P4_TXP_CON AOZ8808DI-05_DFN-10-10-9_2P5X1
C95 1 2 0.1U_0402_10V7-K 4 3
[15] USB3P4_TXP 4 3 EMC@
+USB_VCCA
USB3P4_TXN C96 1 2 0.1U_0402_10V7-K USB3P4_TXN_C 1 2 USB3P4_TXN_CON
[15] USB3P4_TXN 1 2
L10 EMC@ JUSB4 ME@
USB3P4_TXP_CON 9
D7 EMC@ 1 StdA_SSTX+
USB20_N4_CON 1 6 USB20_P4_CON USB3P4_TXN_CON 8 VBUS
EXC24CH900U_4P USB20_P4_CON 3 StdA_SSTX-
USB3P4_RXP 4 3 USB3P4_RXP_CON +USB_VCCA 7 D+
[15] USB3P4_RXP 4 3 USB20_N4_CON GND_DRAIN
2 10
2 5 USB3P4_RXP_CON 6 D- GND_1 11
USB3P4_RXN 1 2 USB3P4_RXN_CON 4 StdA_SSRX+ GND_2 12
[15] USB3P4_RXN 1 2 USB3P4_RXN_CON GND_5 GND_3
5 13
L11 EMC@ StdA_SSRX- GND_4
3 4 ALLTO_C190L1-109H9-L

CM1293A-04SO_SC-74-6
EXC24CH900U_4P
USB20_P4 4 3 USB20_P4_CON
[15] USB20_P4 4 3

USB20_N4 1 2 USB20_N4_CON
[15] USB20_N4 1 2
C L12 EMC@ C

PORT2(AOU)
EXC24CH900U_4P
USB3P2_TXN C97 1 2 0.1U_0402_10V7-K USB3P2_TXN_C 4 3 USB3P2_TXN_CON
[15] USB3P2_TXN 4 3
+5VALW +5VALW_CHGUSB
USB3P2_TXP C98 1 2 0.1U_0402_10V7-K USB3P2_TXP_C 1 2 USB3P2_TXP_CON
[15] USB3P2_TXP 1 2
L13 EMC@
AOU1
1 12
IN OUT 10 USB20P2
USB20_P2 3 DP_IN 11 USB20N2
[15] USB20_P2 USB20_N2 DP_OUT DM_IN
2 14
[15] USB20_N2 DM_OUT GND
EXC24CH900U_4P EXC24CH900U_4P
9 AOU_IFG# AOU_IFG# [57] USB3P2_RXN 4 3 USB3P2_RXN_CON USB20P2 4 3 USB20_P2_CON
STATUS# [15] USB3P2_RXN 4 3 4 3
4
USB_OC1# 13 ILIM_SEL USB3P2_RXP 1 2 USB3P2_RXP_CON USB20N2 1 2 USB20_N2_CON
[15] USB_OC1# AOU_EN FAULT# [15] USB3P2_RXP 1 2 1 2
[57] AOU_EN 5
EN 15 ILIM_LO R84 1 @ 2 20K_0402_1% L14 EMC@ L15 EMC@
AOU_CTL1 6 ILIM_LO 16 ILIM_HI R85 1 2 20K_0402_1%
[57] AOU_CTL1 CLT1 ILIM_HI
7
AOU_CTL3 8 CLT2 17
[57] AOU_CTL3 CLT3 GND_Pad
B 1 TPS2546RTER_QFN16_4X4 D8 B
@ +5VALW_CHGUSB
C99
0.1U_0402_10V7-K
TI TPS2546 1 USB3P2_TXP_CON
2 CH1
USB3P2_TXP_CON 9 2 USB3P2_TXN_CON
NC_4 CH2 1
1
USB3P2_TXN_CON 8 + C100 C101
NC_3
3 150U_B2_6.3VM_R35M 470P_0402_50V7-K
CLT1 CLT2 CLT3 ILIM_SEL MOD VN 2 2
USB3P2_RXP_CON 7
NC_2
0 0 0 X DCH OUT held low USB3P2_RXN_CON 6 4 USB3P2_RXP_CON
NC_1 CH3

1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active 5 USB3P2_RXN_CON
* CH4

* 1 1 1 0 SDP2 Data Connected AOZ8808DI-05_DFN-10-10-9_2P5X1

EMC@ +5VALW_CHGUSB
* 1 1 0 X SDP1 Data Connected

JUSB2 ME@
* 0 1 0 X SDP1 Data Connected
D9 EMC@
USB3P2_TXP_CON 9
1 StdA_SSTX+
USB20_N2_CON 1 6 USB20_P2_CON USB3P2_TXN_CON 8 VBUS
1 0 0 X Device Forced to stay in DCP BC 1.2 charging mode USB20_P2_CON 3 StdA_SSTX-
DCP_Short D+
+5VALW_CHGUSB 7
USB20_N2_CON 2 GND_DRAIN 10
1 0 1 X Device Forced to stay in DCP Divider 1 Charging Mode 2 5 USB3P2_RXP_CON 6 D- GND_1 11
DCP_Divider StdA_SSRX+ GND_2
4 12
USB3P2_RXN_CON 5 GND_5 GND_3 13
0 1 1 X Data Disconnected and Port Power Mgt. Function Active StdA_SSRX- GND_4
DCP_Auto
A
* 3 4 ALLTO_C190L1-109H9-L A

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active CM1293A-04SO_SC-74-6

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 USB3 PORT1/PORT2(AOU)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 44 of 82
5 4 3 2 1
 5 4 3 2 1

D D

USB3 PORT3
+USB_VCCA

1
1
+ C802 C803

150U_B2_6.3VM_R35M 470P_0402_50V7-K
2 2

C C

+USB_VCCA

JUSB3
D62 EMC@ 1
L25 EMC@ USB20_P3_CON 1 6 USB20_N3_CON VBUS
USB20_P3 1 2 USB20_P3_CON USB20_N3_CON 2
[15] USB20_P3 1 2 +USB_VCCA USB20_P3_CON D-
3
D+
USB20_N3 4 3 USB20_N3_CON 2 5 4
[15] USB20_N3 4 3 GND_1
5
EXC24CH900U_4P 6 GND_2
7 GND_3
3 4 8 GND_4
GND_5
CM1293A-04SO_SC-74-6 DEREN_43-42157-00401RHF
ME@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 USB PORT3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 45 of 82
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
0.5ms＜spec＜ 100m s
+3VALW +3VALW_LAN +3VALW_LAN +LAN_VDDREG +3VALW_LAN +3VS

RL1 0_0603_5%
RL18 1 2 0_0805_5% width : 40 mils 1 2

2
4.7U_0603_6.3V6-K

4.7U_0603_6.3V6-K
RL2

G
D D
CL4 CL5 10K_0402_5% @ QL1

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K
LP2301ALT1G_SOT23-3 1 1

0.1U_0402_10V7-K

0.1U_0402_10V7-K
CL2 1 CL3 1 1 1 CL6

2
CL7 QL2 3 1 @ CL8 CL1 LAN_CLKREQ#_R 1 3 @

D
CLKREQ_PCIE3_LAN# [10]
@ @

S
2 2

0.1U_0402_10V7-K

0.1U_0402_10V7-K
1 1 2N7002KW_SOT323-3
2 2 2 2

G
2
@ @
RL4 1 2 0_0402_5%
2 2
RL5 1 @ 2
[12] PCH_SLP_LAN#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN

1
RL6
@ 10K_0402_5% UL1
CL10 close to Pin18 +3VALW_LAN 11 3 +LAN_VDD10
CL9 close to Pin17 AVDD33_1 AVDD10_1
2

+3VALW_LAN 32 8 +LAN_VDD10
RL7 1 2 0_0402_5% LAN_WAKE#_R AVDD33_2 AVDD10_2 30 +LAN_VDD10
[57] LAN_WAKE# PCIE_PRX_DTX_P10CL9 1 AVDD10_3
2 0.1U_0402_10V7-K PCIE_PRX_DTX_C_P10 17 22 +LAN_VDD10
[15] PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10CL10 1 2 0.1U_0402_10V7-K PCIE_PRX_DTX_C_N10 18 HSOP DVDD10
[15] PCIE_PRX_DTX_N10 HSON 1 MDI_0+
C C
PLT_RST# 19 MDIP0 2 MDI_0- MDI_0+ [47]
[12,28,42,48,49,57,58] PLT_RST# PERSTB MDIN0 MDI_0- [47]
4 MDI_1+
ISOLATE# 20 MDIP1 5 MDI_1- MDI_1+ [47]
LAN_WAKE#_R 21 ISOLATEB MDIN1 MDI_1- [47]
+3VS +3VALW_LAN LANWAKEB 6 MDI_2+
+LAN_VDDREG 23 MDIP2 7 MDI_2- MDI_2+ [47]
+LAN_REGOUT 24 VDDREG MDIN2 MDI_2- [47]
REGOUT MDI_3+
1

9
RJ45_LINKUP# 25 MDIP3 10 MDI_3- MDI_3+ [47]
RL19
[47] RJ45_LINKUP# LED1 26 LED2 MDIN3 MDI_3- [47]
RL8 @ 10K_0402_5%
1K_0402_5% RJ45_ACTIVITY# 27 LED1/GPO 13 PCIE_PTX_C_DRX_P10
[47] RJ45_ACTIVITY# LED0 HSIP 14 PCIE_PTX_C_DRX_N10 PCIE_PTX_C_DRX_P10 [15]
HSIN PCIE_PTX_C_DRX_N10 [15]
2

LAN_XTALO 28 12 LAN_CLKREQ#_R
ISOLATE# LED1 CKXTAL1 CLKREQB
LAN_XTALI 29 15 CLK_PCIE_LAN
CKXTAL2 REFCLK_P 16 CLK_PCIE_LAN# CLK_PCIE_LAN [10]
REFCLK_N CLK_PCIE_LAN# [10]
1

RL9 TL2 1 RJ45_LINKUP# 33 31 RSET

15K_0402_5% GND RSET

1
TL3 1 LED1
RTL8111GUS-CG_QFN32_4X4 RL10
2

TL4 1 RJ45_ACTIVITY# 2.49K_0402_1%

2
B B

LAN_XTALI
+LAN_VDD10
YL1 LAN_XTALO

1 4 LL1
OSC1 GND2 +LAN_REGOUT 1 2
2 3
GND1 OSC2

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1U_0402_10V6-K
2.2UH_EP-22AM05B02_2A_20% 1 1 1 1 1 1 1
1 1
Layout Note: LL1 must be CL14 CL15 CL16 CL17 CL18 CL19 CL20 @
CL11 25MHZ_10PF_7V25000014 CL12
12P_0402_50V8-J 12P_0402_50V8-J within 200mil to Pin24, 2 2 2 2 2 2 2
2 2 CL14,CL15 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil Close to Pin3, 8, 22, 30 LAYOUT NEED CHECK Close to Pin22(Reserved)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 GBE LAN PHY

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 46 of 82
5 4 3 2 1
 5 4 3 2 1

TL1 EMC@

MDI_0+ 1 1:1
[46] MDI_0+ TD1+ T1/B RJ45_TXD0P
24
TX1+

MDI_0- 2
[46] MDI_0- TD1-
D D
23 RJ45_TXD0N
TX1-
TDCT 3 22 MCT1 RL12 2 1 75_0805_5% RJ45_GND DL1 @
TDCT1 T1/A TXCT1 MCT1 2 1
EMC@
4 21 MCT2 RL13 2 1 75_0805_5%
MDI_1+ 5 TDCT2 1:1 TXCT2 LSE-200NX3216TRLF_1206-2
[46] MDI_1+ TD2+ T1/B
RJ45_TXD1P
20 EMC@
TX2+ @
DL2
MCT2 2 1

MDI_1- 6
[46] MDI_1- TD2- RJ45_TXD1N
19 LSE-200NX3216TRLF_1206-2
TX2-
DL3 @
T1/A MCT3 2 1
20160218
MDI_2+ 7 1:1 RL12,RL13,RL14,RL15 change to SD00001V80T
[46] MDI_2+ TD3+ T1/B RJ45_TXD2P
TX3+
18 By EMC request LSE-200NX3216TRLF_1206-2

DL4 @
MDI_2- 8 MCT4 2 1
[46] MDI_2- TD3-
17 RJ45_TXD2N
TX3- LSE-200NX3216TRLF_1206-2
9 16 MCT3 RL14 2 1 75_0805_5%
TDCT3 T1/A TXCT3
EMC@
10 15 MCT4 RL15 2 1 75_0805_5%
MDI_3+ 11 TDCT4 1:1 TXCT4
[46] MDI_3+ TD4+ T1/B
RJ45_TXD3P
14 EMC@
TX4+
1U_0402_10V6K

1 1
PATTERN MUST BE
EMC@ CL21 CL22 EMC@
C
0.1U_0402_25V6-K MDI_3- 12
SHORT AND WIDE. C
2 2 [46] MDI_3- TD4- RJ45_TXD3N
13
TX4-

T1/A

CL21 CL22 close to LAN Chip BOTHHAND_NA69LF

RJ-45 Conn.
DL5 RCLAMP0524PATCT_SLP2510P8-10-9

RL16 JRJ1 ME@

MDI_0+ 9 1 MDI_0+ 1 2 RJ45_ACTIVITY#_R 12
MDI_0- MDI_0- [46] RJ45_ACTIVITY# Yellow_LED-
8 2
MDI_1+ 7 4 MDI_1+ 510_0402_1% 11
MDI_1- MDI_1- +3VALW_LAN Yellow_LED+
6 5
RJ45_TXD3N 8 16
PR4- G4 15
RJ45_TXD3P 7 G3 14
B B
PR4+ G2 13
EMC@ RJ45_TXD1N 6 G1
PR2-
3

RJ45_TXD2N 5
PR3-
RJ45_TXD2P 4
PR3+
RJ45_TXD1P 3
PR2+
RJ45_TXD0N 2
PR1-
RJ45_TXD0P 1
RL17 PR1+
DL6 RCLAMP0524PATCT_SLP2510P8-10-9 1 2 RJ45_LINKUP#_R 10
[46] RJ45_LINKUP# Green_LED-
+3VALW_LAN 510_0402_1% 9
Green_LED+
MDI_2+ 9 1 MDI_2+ SINGA_2RJ3089-108211F
MDI_2- 8 2 MDI_2-
MDI_3+ 7 4 MDI_3+ EMC@
MDI_3- 6 5 MDI_3-
RJ45_GND CL23 1 2 1000P_1808_3KV7k~D LANGND
1 1
CL24 CL25
EMC_NS@ EMC@
EMC@ 0.1U_0402_10V6-K .01U_0402_16V7-K
3

2 2

LANGND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 RJ45 CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 47 of 82
5 4 3 2 1
 +3VS +3VALW +3V_WLAN

TYPE-A NGFF SLOT FOR WLAN R86 1

@
2 0_0805_5%

3.2H CONNECTOR R87 1 2 0_0805_5%

@
+3VALW

@
R390 1 2 10K_0402_5% EC_WLAN_WAKE# +3VS
+3V_WLAN

JWLBT1
+3VS EMC@ 1 2
USB20_P6 R425 1 2 0_0402_5% USB20_P6_CON 3 GND1 3.3VAUX1 4
USB20_N6 R426 1 2 0_0402_5% USB20_N6_CON 5 USB_D+ 3.3VAUX2 6
USB_D- KEY A LED1#

1
EMC@ 7 8
1 2 BT_ON GND2 NC
R421
9 NC NC 10
R312 11 NC NC 12 R420 @ @ 49.9K_0402_1%
10K_0402_5% For EMI choke co-lay 13 14 49.9K_0402_1%
NC NC
1 2 RF_OFF# 15 16
NC LED2#

2
17 18
R313 19 MLDIR_SENSE GND16 20
10K_0402_5% 21 DP_ML3N DP_AUXN 22
23 DP_ML3P DP_AUXP 24
25 GND3 GND13 26 R330 1 2 0_0402_5%
DP_ML2N DP_ML1N UART2_RX [14]
27 28
29 DP_ML2P DP_ML1P 30 R331 1 2 0_0402_5%
GND4 GND14 UART2_TX [14]
31 32
33 DP_HPD DP_ML0N 34
PCIE_PTX_C_DRX_P9 35 GND5 DP_ML0P 36
[15] PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_N9 PETP0 GND15 CL_RST_WLAN#
L34 EMC_NS@ 37 38
USB20_P6 USB20_P6_CON [15] PCIE_PTX_C_DRX_N9 PETN0 VENDOR_DEFINED_1 CL_DATA_WLAN CL_RST_WLAN# [11]
1 2 39 40
[15] USB20_P6 1 2 PCIE_PRX_DTX_P9 GND6 VENDOR_DEFINED_2 CL_CLK_WLAN CL_DATA_WLAN [11]
41 42
[15] PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 PERP0 VENDOR_DEFINED_3 CL_CLK_WLAN [11]
43 44
USB20_N6 USB20_N6_CON [15] PCIE_PRX_DTX_N9 PERN0 COEX3
4 3 45 46
[15] USB20_N6 4 3 CLK_PCIE_WLAN GND7 COEX2
47 48
[10] CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX1 SUSCLK_32K
EXC24CH900U_4P 49 50
[10] CLK_PCIE_WLAN# REFCLKN0 SUSCLK PLT_RST# SUSCLK_32K [10]
51 52
CLKREQ_PCIE2_WLAN# GND8 PERST0# BT_ON_R PLT_RST# [12,28,42,46,49,57,58]
53 54
[10] CLKREQ_PCIE2_WLAN# EC_WLAN_WAKE# CLKREQ0# W_DISABLE2# RF_OFF#
55 56
PEWAKE0# W_DISABLE1# RF_OFF# [14]
57 58
59 GND9 I2C_DATA 60
61 PETP1 I2C_CLK 62 R90 1 2 100_0402_1% EC_RX
PETN1 ALERT# EC_TX_R EC_TX EC_RX [57]
63 64 R91 1 2 100_0402_1%
GND10 RESERVED4 EC_TX [57]
65 66
67 PERP1 PERST1# 68
69 PERN1 CLKREQ1# 70
GND11 PEWAKE1#

1
71 72
73 REFCLKP1 3.3VAUX4 74
75 REFCLKN1 3.3VAUX5 R92
GND12 100K_0402_5%
76 77
PEG1 PEG2

2
ARGOS_NASA0-S6701-TS40 BT_ON_R R93 1 2 1K_0402_5%
BT_ON [14]
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 WWAN/WLAN NGFF CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 48 of 82
 5 4 3 2 1

+3VS

4.7U_0603_6.3V6-K
@ 1
CW9 CW8, CW7 should be closed to Power pin 1,18 respectively.
2
CW1 should be closed to Power pin10 and Pin12
+3VS

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
D 1 D
CW3
1 1 1 1 1 1U_0402_10V6-K

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K
CW1 CW8 CW7 CW14 CW4 2

All of cap. close to chip 2 2 2 2 2

CW2

1 1
UW1

4.7U_0603_6.3V6-K

0.1U_0402_10V7-K
18

10

12

26

32

31

11

19
1

9
CW15
RW8 need to apply new P/N

CORE_12VCCD
PE_33VCCAIN

PE_12VCCAIN
AUX _33VIN

MAIN_LDO_12VOUT
MAIN_LDO_VIN
SD_IO_SKT_33VIN

AUX_LDO_CAP
PLL_DLL_12VCCAIN

SD_IO_LDO_CAP
2 2
RW8 1 2 191_0402_1% SD_RREF 4
PE_REXT
Close to chip
PCIE_PTX_C_DRX_N5 5
[15] PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5 PE_RXM
6
[15] PCIE_PTX_C_DRX_P5 PE_RXP
+CRD_POWER
CW11 1 2 0.1U_0402_10V7-K PCIE_PRX_C_DTX_P5 7
[15] PCIE_PRX_DTX_P5 PE_TXP
CW13 1 2 0.1U_0402_10V7-K PCIE_PRX_C_DTX_N5 8 17
[15] PCIE_PRX_DTX_N5 PE_TXM SD_SKT_33VOUT
1
CLK_PCIE_CR# 2 CW16
[10] CLK_PCIE_CR# CLK_PCIE_CR PE_REFCLKM SD_WP
3 21 1U_0402_10V6-K
[10] CLK_PCIE_CR PE_REFCLKP SD_WPI
20 SD_CD# 2
SD_CD#
27 SD_CLK_MS_DATA0 1 @ 2 SD_CLK_MS_DATA0_R
PLT_RST# 14 SD_CLK RW10 0_0402_5%
[12,28,42,46,48,57,58] PLT_RST# PE_RST#_GATE# SD_CMD_MS_DATA2 SD_CMD_MS_DATA2_R
28 1 @ 2
SD_CMD RW13 0_0402_5%
C SD_MS_DATA3 SD_MS_DATA3_R C
+3VS 13 29 1 @ 2
MAIN_LDO_EN SD_D3 RW14 0_0402_5% 1
RW5 @ 30 SD_DATA2_MS_CLK 1 @ 2 SD_DATA2_MS_CLK_R CW5
10K_0402_5%1 2 SD_WAKE# 15 SD_D2 RW15 0_0402_5%
+3VS DEV_WAKE# 5P_0402_50V9-C
24 SD_DATA1 1 @ 2 SD_DATA1_R EMC_NS@
SD_D1 RW12 0_0402_5% 2
25 SD_DATA0_MS_DATA1 1 @ 2 SD_DATA0_MS_DATA1_R
CLKREQ_PCIE5_CR# 23 SD_D0 RW11 0_0402_5%
[10] CLKREQ_PCIE5_CR# CLKREQ#
20160621
22 Change RW10,RW11,RW12,RW13,
LED#_IO1
16
RW14,RW15 to short pad for EMI
+3VS IO0_MAIN_LDOSEL

GND
OZ621FJ1LN_QFN32_4X4

33
+3VS +3VS +3VS

JREAD1

1
+CRD_POWER
RW19
SD_DATA2_MS_CLK_R 1 100K_0402_5% 100K_0402_5% 10K_0402_5%
40 mils DAT2
SD_MS_DATA3_R 2 RW16 RW20
SD_CMD_MS_DATA2_R 3 CD/DAT3
CMD

2
B 4 B
5 VSS1
VDD 2 @ 1 SD_CD# 2 @ 1 SD_WP
SD_CLK_MS_DATA0_R 6 RW3 0_0402_5% RW4 0_0402_5%
7 CLK
10U_0603_6.3V6-M
0.1U_0402_10V7-K

SD_DATA0_MS_DATA1_R 8 VSS2
1 1 DAT0
SD_DATA1_R

1
9 QW1 D QW2 D
CW18

@ DAT1 SD_CD#_R 2 SD_WP_R 2

CW17

G G
2 2 SD_WP_R 10
SD_CD#_R 11 W/P S 2N7002WT1G_SC-70-3 S 2N7002WT1G_SC-70-3
C/D

3
12
13 GND1
GND2

Close to JREAD1. T-SOL_156-2000302604_RV

ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 49 of 82
5 4 3 2 1
 +5VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +5VS
U11 J5 @
1 14 +5VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X118
1 1
SUSP# 3 12 C356 1 2 1000P_0402_25V7-K
Load Switch C352
1U_0402_6.3V6-K 4
ON1 CT1
11
C354
0.1U_0402_10V7-K
+5VALW
+5VALW To +5VS 2
SUSP# 5
VBIAS GND
10 C357 1 2 100P_0402_50V8-J
2

+3VALW To +3VS +3VALW

6
ON2 CT2
9 J6 @
+3VS

7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2

VIN2_2 VOUT2_1 1 2
1 15 1 JUMP_43X118
GPAD
C353 TPS22966DPUR_WSON14_2X3 C355
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2

+5VS, C356 --> 1.5ms

+3VS, C357 --> 2.5ms

+1VALW to +VCC_IO_AP & +VCC_ST

+1VALW
Unstaff C402 and C403 for the fastest sequence. +VCC_IO

3 A
U14 R416 0_0805_5%
1 14 +VCC_IO_AP 1 @ 2
2 IN1_1 OUT1_2 13 R417 0_0805_5%
IN1_2 OUT1_1 @ 1 @ 2
1 1
[57,69] SUSP# SUSP# 3 12 C402 1 2 1000P_0402_25V7-K
C400 EN1 CT1 C404
1U_0402_6.3V6-K +5VALW 4 11 0.1U_0402_10V7-K
2 VBIAS GND @ 2 +VCC_ST
+1VALW 5 10 C403 1 2 100P_0402_50V8-J
[57,69,78] SYSON EN2 CT2
6
IN2_1 OUT2_2
9 60mA
7 8 +VCC_ST_OUT R381 1 @ 2
IN2_2 OUT2_1 0_0603_5%
1 15 1
GPAD
C401 G5016KD1U_TDFN14_2X3 C405
1U_0402_6.3V6-K 0.1U_0402_10V7-K
2 2

+VCC_IO +VCC_STG

R272 0_0805_5%
1 @ 2

Slew Rate=10uS<TR<65us

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 DC V TO VS/ V-PCH/VM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 50 of 82
 A B C D E

+5VS +1.8V_LDO +1.65V_LDO +3V_LDO

LDO 1V8 VREF 1V65 LDO 3V3
1 RA1 0_0805_5% +3VS 1
1 @ 2 CA1 CA2 CA3 CA4 +5VS_CLASSD

4.7U_0603_10V6-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

CA6

CA7

CA8

CA9
CA10
1 1 1 1
0.1U_0402_10V7-K
CA10 close Pin7
1 1 1 1 1
CA11
2
2 2 2 2

4.7U_0603_10V6-K

0.1U_0402_10V7-K

1U_0402_6.3VA-K

0.1U_0402_10V7-K
2.2U_0402_6.3V6-M
2 2 2 2 2
X5R CAP

+3VS_VDDO +3VS
X5R CAP

Close to Pin13,16 RA2 2 1 0_0402_5%

1 @
CA12
0.1U_0402_10V7-K CA12 close Pin2
UA1 2

PCH_HDA_RST# 9 3
[9] PCH_HDA_RST# RESET# FILT_1.8V +1.8V_LDO
7 +3VS_VDDIO
VDD_IO 2 +3V_AVDD_HP +3VL
PCH_HDA_BCLK VDDO_3.3 +3VS_VDDO
5 18 +3VS_DVDD
[9] PCH_HDA_BCLK BIT_CLK DVDD_3.3
PCH_HDA_SYNC 8 27 RA4 0_0805_5%
[9] PCH_HDA_SYNC SYNC AVDD_3.3 +3V_LDO
29 1 @ 2
[9] PCH_HDA_SDIN0
PCH_HDA_SDIN0 RA3 1 2 33_0402_5% PCH_HDA_SDIN0_R 6 CX11852 VREF_1.65V 28
+1.65V_LDO
+5VS_AVDD
PCH_HDA_SDOUT 4 SDATA_IN AVDD_5V
[9] PCH_HDA_SDOUT SDATA_OUT 1
PC_BEEP 10 12 SPK_L+ CA13
2 [52] PC_BEEP SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L- SPK_L2+ [52]
1U_0402_6.3VA-K
CA13 close Pin24 2
SPKR_MUTE# LEFT- SPK_L1- [52] 2
JSENSE 38 17 SPK_R+
[52] JSENSE JSENSE RIGHT+ SPK_R- SPK_R2+ [52]
37 15
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- [52]
36 35
DMIC_CLK RA7 1 2 33_0402_5% MIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34 +3VS
[37] DMIC_CLK DMIC_DATA DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB +3VS_DVDD
1
[37] DMIC_DATA DMIC_DAT/GPIO1 PORTB_R
33
PORTB_R_LINE PORTB_L PORTB_R [52]
32 RA8 0_0805_5%
CLASSD_REF PORTB_L_LINE PORTB_L [52]
1 +5VS_CLASSD CA14 1 2 11 1 @ 2
CA32 0.1U_0402_10V7-K CLASS-D_REF 30 EXT_MIC_A
PORTD_A_MIC EXT_MIC_B EXT_MIC_A [52]
150P_0402_50V8-J 13 31
EMC@ 16 LPWR_5.0 PORTD_B_MIC EXT_MIC_B [52] X5R CAP, Please Close Pin18
2 W= 80mils RPWR_5.0 25 HGNDA
FLY_P HGNDA HGNDA [52,53]
CA15 1 2 19 26 HGNDB 1
FLY_N FLY_P HGNDB HGNDB [52,53]
1U_0402_6.3V6-K 20
FLY_N 24 CA16
20160121 AVDD_HP +3V_AVDD_HP
+AVEE 21 1U_0402_6.3VA-K
Mount CA32 by EMC suggestion +AVEE
CA17 AVEE 23 HP_OUTR 2
PORTA_R HP_OUTL HP_OUTR [52]
41 22
2.2U_0402_6.3V6-M

HP indicate 1 GND PORTA_L HP_OUTL [52]

Should be Apple --> EXT_MIC_A, HGNDB

2 connect to CX11852-11Z_QFN40_5X5 Nokia --> EXT_MIC_B, HGNDA
GNDA
+5VS_AVDD +5VS
RA9 0_0805_5%
38 31 1 @ 2
1 AGND

1
CA18
3 DGND 0.1U_0402_10V7-K 3
21
11 2
W= 300mils
EMC_NS@
CA34 1 2 0.1U_0402_10V7-K
Please Close Pin28
EMC_NS@
CA33 1 2 0.1U_0402_10V7-K

EMC_NS@
CA19 1 2 0.1U_0402_10V7-K
+3VALW

+3VS_VDDIO
+3VS_VDDO
GND GNDA 0_0402_5% 1 2 RA12 +3VS_VDDIO
1

@ 1
RA10 CA20
47K_0402_5% 0.1U_0402_10V7-K
2
2

DA1
CA20 close Pin7
EC_MUTE# 1 2 SPKR_MUTE#
[57] EC_MUTE#
RB751V-40_SOD323-2
SCS00008K00

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 Audio Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 51 of 82
A B C D E
 5 4 3 2 1

Apple --> EXT_MIC_A, HGNDB

PC Beep 1
RA37
2 CA21 1 2 0.1U_0402_10V7-K
EXT. MIC/ LINE IN Nokia --> EXT_MIC_B, HGNDA

4.7K_0402_5%

D D
EXT_MIC_A RA13 1 2 100_0402_5% EXT_MIC_A_R CA22 1 2 2.2U_0402_6.3V6-K HGNDB
[51] EXT_MIC_A HGNDB [51,53]
EC Beep DA2 @
2 @ @
[57] BEEP# EXT_MIC_B
CA24 RA14 1 2 100_0402_5% EXT_MIC_B_R CA23 1 2 2.2U_0402_6.3V6-K HGNDA
BEEP_D RA15 PC_BEEP [51] EXT_MIC_B HGNDA [51,53]
1 1 2 1 2
PC_BEEP [51]
PCH Beep 3
33_0402_5%
0.1U_0402_10V7-K
[9] PCH_BEEP
BAT54CW_SOT323-3

1
@
RA16
10K_0402_5%

2
+3VS

1
RA17
RA36
5.11K_0402_1%
1 2 CA25 1 2 0.1U_0402_10V7-K

2
JSENSE RA18 2 1 20K_0402_1% JSENSE_CON
4.7K_0402_5% [51] JSENSE JSENSE_CON [53]
RA19 2 1 39.2K_0402_1%

C C

HeadPhone/ LINE OUT Speaker OUT SPK CONN.

Need Lenght Match
RA20 1 2 3K_0402_5% +MICBIASB
JSPK2
HP_OUTL RA21 1 2 75_0402_5% HP_OUTL_CON 20160601 SPK_L+_CON 1
[51] HP_OUTL HP_OUTL_CON [53] SPK_L-_CON 1
2
CA26
Change RA41 to R-short EMC@ 2
PORTB_L RA24 SPK_L-_CON
[51] PORTB_L 1 2 1 2 RA22 1 2 BLM18PG221SN1D_2P 3
[51] SPK_L1- GND1
EMC@ 4
100_0402_5% SPK_L+_CON GND2
B 4.7U_0603_6.3V6-K RA23 1 2 BLM18PG221SN1D_2P B
[51] SPK_L2+
EMC@ TE_2041180-2
1 2 SPK_R-_R RA25 1 2 BLM18PG221SN1D_2P SPK_R-_CON
[51] SPK_R1- ME@
RA41 0_0805_5% EMC@
RA27 1 2 3K_0402_5% +MICBIASB 1 2 SPK_R+_R RA26 1 2 BLM18PG221SN1D_2P SPK_R+_CON
[51] SPK_R2+
RA40 1_0805_5%
20160418 JSPK1
HP_OUTR RA28 1 2 75_0402_5% HP_OUTR_CON SPK_R+_CON 1
[51] HP_OUTR HP_OUTR_CON [53] Change RA41 to 0ohm/RA40 to 1ohm SPK_R-_CON 2 1
CA27 for speaker volume balance 2
PORTB_R RA29
[51] PORTB_R 1 2 1 2 3
4 GND1
100_0402_5% GND2
4.7U_0603_6.3V6-K
TE_2041180-2
EMC@ ME@
CA28 1 2 1000P_0402_50V7-K SPK_L-_CON
EMC@
CA29 1 2 1000P_0402_50V7-K SPK_L+_CON
EMC@
CA30 1 2 1000P_0402_50V7-K SPK_R-_CON
EMC@
CA31 1 2 1000P_0402_50V7-K SPK_R+_CON

EMI parts Close to connector

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 HP/MIC JACK/Speaker
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 52 of 82
5 4 3 2 1
 5 4 3 2 1

D D

JAUHP1
HGNDB 3
[51,52] HGNDB
HGNDA 6
[51,52] HGNDA ESD request
HP_OUTL_CON 1

HGNDA

HGNDB

HP_OUTL_CON

HP_OUTR_CON

JSENSE_CON

GNDA
[52] HP_OUTL_CON

HP_OUTR_CON 2
[52] HP_OUTR_CON JSENSE_CON 4
[52] JSENSE_CON
5

2
C
SINGA_2SJ-E960-001F C
ME@ D32 D33 D65
GNDA PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3
EMC@ EMC@ EMC@

1
EMC@ C8620
100P_0402_50V8-J

EMC@ C8621
100P_0402_50V8-J
1 1

2 2

Vendor suggestion. Reserve for EMI.

GNDA Close to JAUHP.

EMC_NS@
CA35 1 2 0.1U_0402_10V7-K
B B
EMC_NS@
CA36 1 2 0.1U_0402_10V7-K

GND GNDA

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 AUDIO JACK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 53 of 82
5 4 3 2 1
 5 4 3 2 1

+3VPD +3VPD_VDD +3VPD_VDDIO 20160426

USBC1_CC1_CONN
1.Change C108,C109 to 150P
by vender suggestion
TYPEC@ TYPEC@
R98 1 2 0_0402_5% R99 1 2 0_0402_5% USBC1_CC2_CONN
20160505
20160624 Change C108,109 to 390P
Change R99 Pin1 to +3VPD_VDD 1 1 due to U20 material shortage

390P_0402_50V8-J

390P_0402_50V8-J
+3VPD_VDD TYPEC@ C108 C109 TYPEC@

+3VPD_VDD +3VPD_VDDIO 2 2
+3VALW +3VPD_VDDIO
D VCCPD_VBUS +5VALW D
1

R110 @
4.7K_0402_5% 1
0.1U_0402_16V7-K

0.1U_0402_16V7-K

1U_0402_10V6-K

0.1U_0402_16V7-K

1U_0402_10V6-K
1 1 1 1 1 TC32
TYPEC@ TYPEC@ TYPEC@ TYPEC@ TYPEC@
C103 C104 C105 C902 C903
2

PD_XRES 2 2 2 2 2
U5

31

20
18

40
1

VBUS

VBUS_P
VSYS
VDDIO
C110 TYPEC@
0.1U_0402_16V7-K
2 R215 1 TYPEC@2 0_0402_5% CCG2_I2C_CLK_PD_R 9 19 VCCD
[55] CCG2_I2C_CLK_PD CCG2_I2C_DATA_PD_R GPIO/UART_0_RX/UART_3_CTS/SPI_3_MOSI/I2C_3_SCL/HPD VCCD
R216 1 TYPEC@2 0_0402_5% 10 +3VALW
[55] CCG2_I2C_DATA_PD GPIO/UART_0_TX/UART_3_RTS/SPI_3_CLK/I2C_3_SDA USB_P_PWR_SENSE +5VALW +3V_MUX
39

0.1U_0402_16V7-K

1U_0402_10V6-K
1 1 TYPEC@
R108 1 TYPEC@2 0_0402_5% USBC1_CC1 5 OC TYPEC@ TYPEC@ R521
[55] USBC1_CC1_CONN USBC1_CC2 CC1
[55] USBC1_CC2_CONN R109 1 TYPEC@2 0_0402_5% 3 C900 C901 0_0805_5%
4 CC2 +3VPD_VDD 1 2
+5VALW V5V 2 2
20160615
+3VPD_VDDIO Add VBUS_C_CTRL0 due to Type-C 17
PD_VBUS_DISCHG VDDD

1
32 3 1

D
Add R961 0_0402_5% VBUS_C_CTRL0_R VBUS_DISCHARGE
[65] VBUS_C_CTRL0 R965 1 TYPEC@ 2 0_0402_5% 30 20160414 @
29 VBUS_C_CTRL0 R969 Q31
CCG2_I2C_CLK_PD R400 1 TYPEC@2 10K_0402_5% VBUS_C_CTRL1 1.Change net name from +3VPD_VDDIO
to +3VPD_VDD 47K_0402_5% AO3413_SOT23-3

G
2
6 @
CCG2_I2C_DATA_PD R399 1 TYPEC@2 10K_0402_5% PCH_MUX_HPD_PD VCONN

2
[5,55] PCH_MUX_HPD R105 1 TYPEC@ 2 0_0402_5% 35
TP17 1 VSEL1 28 GPIO/P3.3 1 PD_VBUS_P_CTRL1
PD_VBUS_C_CTRL1 I2C_0_SCL/GPIO_OVT/UART_0_RTS/SPI_0_MISO VBUS_P_CTRL1 PD_VBUS_P_CTRL0

2
20160624 [65] PD_VBUS_C_CTRL1 27 2
I2C_0_SDA/GPIO_OVT/UART_0_CTS/SPI_0_SEL VBUS_P_CTRL0 @
Change pull up from +3VPD to +3VALW EC_SMB_DA2_R
R214 1 TYPEC@2 0_0402_5% 36 R971
[57] EC_SMB_DA2 EC_SMB_CK2_R GPIO/UART_2_CTS/SPI_2_MOSI/I2C_2_SDA
R213 1 TYPEC@2 0_0402_5% 37 10K_0402_5%
20160627 [57] EC_SMB_CK2
R101 1 TYPEC@2 0_0402_5% INT#_TYPEC_R 34 GPIO/UART_2_RTS/SPI_2_CLK/I2C_2_SCL
Change pull up from +3VALW to +3VPD_VDDIO [57] INT#_TYPEC GPIO/P3.2

1
C
R972 1 TYPEC@ 2 0_0402_5% U5_SENSE# 38 PD_MUX_EN# C
[55] 3V_TPD8S300_FLT# GPIO/P3.6
VBUS_OVP_ACOK# R973 1 TYPEC@ 2 0_0402_5%
D

1
@ 1
23 PD_MUX_EN 2 Q30 @
GPIO/P2.4 15 PD_SWD_IO 1 G 2N7002KW_SOT323-3 C961
+3VALW GPIO/UART_1_CTS/SPI_1_CLK/I2C_1_SCL/SWD_0_DAT/P2.0 PD_SWD_CLK TC23

1
22 16 1 S 0.1U_0402_16V7-K
DMINUS GPIO/UART_1_RTS/SPI_1_MOSI/I2C_1_SDA/SWD_0_CLK/P2.1 TC24 2

3
21 7 @
DPLUS GPIO/UART_2_TX/SPI_2_MISO 8 R970
GPIO/UART_2_RX/SPI_2_SEL 100K_0402_5%
2.2K_0402_5% 1 2 R393 EC_SMB_CK2 USB_OE# 25
[55] USB_OE# GPIO/UART_0_RX/SPI_0_CLK

2
2.2K_0402_5% 1 2 R394 EC_SMB_DA2 USB_SEL 24
[55] USB_SEL USBC_DPAUX1_PD GPIO/UART_0_TX/SPI_0_MOSI
[55] USBC_DPAUX1_MUX R889 1 @ 2 0_0402_5% 11
R890 1 @ 2 0_0402_5% USBC_DPAUX2_PD 14 AUX_P_signal/GPIO/UART_1_TX/SPI_1_MISO 20160616
[55] USBC_DPAUX2_MUX USBC_SBU1 AUX_N_signal/GPIO/UART_1_RX/SPI_1_SEL
[55] USBC_DPAUX1 R891 1 @ 2 0_0402_5% 12 Add soft stop
+3VALW R892 1 @ 2 0_0402_5% USBC_SBU2 13 SBU1_signal/GPIO/UART_3_TX/SPI_3_MISO/SWD_1_CLK
[55] USBC_DPAUX2 SBU2_signal/GPIO/UART_3_RX/SPI_3_SEL/SWD_1_DAT
33 1
GND TC33
41
2.2K_0402_5% 1 2 R370 INT#_TYPEC 1 PD_XRES 26 EPAD
10K_0402_1% 1 @ 2 R371 PCH_MUX_HPD XRES
TC34
CYPD3125-40LQXIT_QFN40_6X6
20160414 TYPEC@
1.Change pull up from +3VPD to +3VALW
by vender suggestion.

B B

VBUS_P_CTRL = 1 (Consumer Path ON) FROM SYSTEM

VBUS_P_CTRL = 0/Z (Consumer Path OFF)

TYPEC@ TYPEC@
VCCPD_VBUS Q27 Q28 TYPEC@ +5VALW VCCPD_VBUS_CONN 20160824
AON7380 3 3 AON7380 0.01_1206_1% Due to EMI fail with Acbel typeC adapter
2 2 EMI suggest add -filter
5 1 VCC5M_Q_VBUS 1 5USB_P_PWR_SENSE 1 2 20160616
PL5 EMC_NS@
BLM18KG300TN1D_2P
Change +3VAWL to +3V_MUX
1U_0402_25V6-K

R533
1 2 20160624

1U_0402_25V6-K
1 1
4

C180 Change F10 connect to VCCPD_VBUS +3V_MUX

TYPEC@

1 1 VCCPD_VBUS
C181 + C460 C461 PL6 EMC_NS@ U30

TYPEC@
1

BLM18KG300TN1D_2P F10
2 R156 R896 470P_0402_50V7-K 1 2 B3 A2 VCCPD_VBUS_F 1 2
2 2 2 IN1 OUT1

1000P_0402_50V7-K

1000P_0402_50V7-K
C2 A3

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
100_0805_5% 100_0805_5% R974 10K_0402_5% R975 10K_0402_5%
PD_VBUS_P_CTRL1 PD_VBUS_P_CTRL0 @ @ C3 IN2 OUT2 B2

100P_0402_50V8J

100P_0402_50V8J
TYPEC@ @ 1 2 1 2 5A_35V_T0603FF5000TM

2
IN3 OUT3 1 TYPEC@ TYPEC@
1 1 1 1 TYPEC@ C960 R960
2

TYPEC@ TYPEC@ 150U_B2_6.3VM_R35M A1 B1 1U_0603_25V6-K 10K_0201_5%

TYPEC@ EN# ACOK#
1

C200 C201 C202 C203 R508 1 2 1M_0201_5% C1 2

GND_1
GND_2
GND_3
PD_VBUS_DISCHG 2 2 2 2 OVLO
1

1
R537 R536
2

0.1U_0603_50V7-K
C8622 TYPEC@ 10M_0402_5% 10M_0402_5% C8623 TYPEC@

TYPEC@

1
0.1U_0402_25V6-K TYPEC@ TYPEC@ 0.1U_0402_25V6-K TYPEC@

C505
2

Discharge Circuit R902 FPF2281BUCX-F130_WLCSP12

C4
A4
B4
2

1 51.1K_0201_1% TYPEC@ VBUS_OVP_ACOK#

2
20160309
1. Reserve R896 for discharge circuit.
A A

20160624
Type-C solution for inrush current

20160627
Change R974/R975 to 10K_0201_5% TYPEC@
Security Classification LC Future Center Secret Data Title
VBUS_DISCHARGE = 1 (Consumer Path ON)
VBUS_DISCHARGE = 0/Z (Consumer Path OFF)
Issued Date 2015/09/01 Deciphered Date 2016/12/31 TYPE-C_Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 54 of 82
5 4 3 2 1
 5 4 3 2 1

+3V_MUX

ESD request +3V_MUX

D35

2
R401 TYPEC@ 1 TYPEC_CON_TXN1
CH1

0.1U_0402_16V7-K

0.1U_0402_16V7-K

0.1U_0402_16V7-K

0.1U_0402_16V7-K

0.1U_0402_16V7-K
0_0402_5% 1 1 1 1 1
TYPEC_CON_TXN1 9 2 TYPEC_CON_TXP1
NC_4 CH2 C111 C112 C113 C114 C115

1
VDD_DCI TYPEC_CON_TXP1 8
NC_3 2 2 2 2 2
U7 3

20
28

17
VN

6
DDI2_MUX_TX0+ C119 1
TYPEC@2 0.1U_0402_16V7-K DDI2_MUX_TX0+_TYPEC 9 TYPEC_CON_RXN1 7

VDD_DCI
VDD33_1
VDD33_2
VDD33_3
[5] DDI2_MUX_TX0+ DDI2_MUX_TX0- DDI2_MUX_TX0-_TYPEC ML0P NC_2
D C117 1
TYPEC@2 0.1U_0402_16V7-K 10 TYPEC@ TYPEC@ TYPEC@ TYPEC@ TYPEC@ D
[5] DDI2_MUX_TX0- DDI2_MUX_TX3+ 1 2 DDI2_MUX_TX3+_TYPEC 18 ML0N TYPEC_CON_RXP1 6 4 TYPEC_CON_RXN1
C123 TYPEC@ 0.1U_0402_16V7-K
[5] DDI2_MUX_TX3+ DDI2_MUX_TX3- 1 2 DDI2_MUX_TX3-_TYPEC 19 ML3P NC_1 CH3
C124 TYPEC@ 0.1U_0402_16V7-K
[5] DDI2_MUX_TX3- ML3N
R418 1DCI@ 2 0_0402_5% DCI_DATA_R 11 30 MUX_TYPEC_RXP1 5 TYPEC_CON_RXP1
[14] DCI_DATA DCI_CLK_R SSDE/DCI_DATA RX1P MUX_TYPEC_RXN1 CH4
R419 1DCI@ 2 0_0402_5% 14 31
[14] DCI_CLK CDE/DCI_CLK RX1N MUX_TYPEC_RXP2
40
C127 1
TYPEC@2 0.1U_0402_16V7-K USB3P1_RXP_TYPEC 5 RX2P 39 MUX_TYPEC_RXN2
[15] USB3P1_RXP USB3P1_RXN_TYPEC SSRXP RX2N AOZ8808DI-05_DFN-10-10-9_2P5X1
C128 1
TYPEC@2 0.1U_0402_16V7-K 4
[15] USB3P1_RXN 1 2 USB3P1_TXP_TYPEC 8 SSRXN EMC_TC@
C125 TYPEC@ 0.1U_0402_16V7-K
[15] USB3P1_TXP 1 2 USB3P1_TXN_TYPEC 7 SSTXP
C126 TYPEC@ 0.1U_0402_16V7-K D36
[15] USB3P1_TXN SSTXN 33 MUX_TYPEC_TXP1 +3V_MUX
TX1P 34 MUX_TYPEC_TXN1 1 TYPEC_CON_TXN2
DDI2_MUX_TX2+ C121 1
TYPEC@2 0.1U_0402_16V7-K DDI2_MUX_TX2+_TYPEC 15 TX1N 37 MUX_TYPEC_TXP2 CH1
[5] DDI2_MUX_TX2+ DDI2_MUX_TX2- 1 2 DDI2_MUX_TX2-_TYPEC 16 ML2P TX2P 36 MUX_TYPEC_TXN2 TYPEC_CON_TXN2 9 2 TYPEC_CON_TXP2
C122 TYPEC@ 0.1U_0402_16V7-K TYPEC@
[5] DDI2_MUX_TX2- DDI2_MUX_TX1+ 1 2 DDI2_MUX_TX1+_TYPEC 12 ML2N TX2N NC_4 CH2 MUX_I2C_EN
C118 TYPEC@ 0.1U_0402_16V7-K R115 1 2 4.7K_0402_5%
[5] DDI2_MUX_TX1+ DDI2_MUX_TX1- DDI2_MUX_TX1-_TYPEC ML1P TYPEC_CON_TXP2
C120 1
TYPEC@2 0.1U_0402_16V7-K 13 8
[5] DDI2_MUX_TX1- ML1N NC_3 CE_USB R116 1 @ 2 10K_0402_5%
1
C129 TYPEC@2 0.1U_0402_16V7-K DOCK_AUX_TYPEC 24 3
[5] DDI2_MUX_AUX 1 2 0.1U_0402_16V7-K DOCK_AUX#_TYPEC 25 AUXP 1 MUX_CEXT 1 2 2.2U_0402_10V6-K VN
C130 TYPEC@ C116 FLIP R117 1 @ 2 10K_0402_5%
[5] DDI2_MUX_AUX# AUXN CEXT 23 CE_DP TYPEC_CON_RXN2 7
MUX_I2C_EN 29 CE_DP 35 CE_USB NC_2 CE_DP R120 1 @ 2 10K_0402_5%
ADDR 3 I2C_EN CE_USB 38 FLIP TYPEC@ TYPEC_CON_RXP2 6 4 TYPEC_CON_RXN2
DCICFG/ADDR FLIP 27 USBC_DPAUX1_MUX 0_0402_5% R8941 2 NC_1 CH3
CCG2_I2C_CLK_PD 21 SBU1 26 USBC_DPAUX2_MUX 0_0402_5% R8951 TYPEC@2 USBC_DPAUX1 [54]
[54] CCG2_I2C_CLK_PD CCG2_I2C_DATA_PD DPEQ/CSCL SBU2 MUX_HPD_PD USBC_DPAUX2 [54] TYPEC_CON_RXP2
[54] CCG2_I2C_DATA_PD 22 32 0_0402_5% R1271 TYPEC@2 5
CEQ/CSDA IN_HPD PCH_MUX_HPD [5,54] CH4 CE_USB R397 1 @ 2 10K_0402_5%

EPAD
4.99K_0402_1% 2 1 R119 MUX_REXT 2
REXT USBC_DPAUX1_MUX FLIP R398 1 @ 2 10K_0402_5%
USBC_DPAUX2_MUX USBC_DPAUX1_MUX [54] AOZ8808DI-05_DFN-10-10-9_2P5X1
TYPEC@ USBC_DPAUX2_MUX [54]

41
PS8743BQFN40GTR-B0_QFN40_4X6 TYPEC@ EMC_TC@ CE_DP R396 1 @ 2 10K_0402_5%
MUX_I2C_EN R118 1 @ 2 4.7K_0402_5%

C R132 1 @ 2 0_0402_5% C

D72 EMC_TC@ EMC_TC@

D73 20160505
TYPEC@ EXC24CH900U_4P +3V_MUX
1. Due to C502 martirail shortage.
MUX_TYPEC_TXP1 1 2 MUX_TYPEC_C_TXP1 4 3 TYPEC_CON_TXP1 USB20_P1_A_CON 1 2 2 1USB20_N1_A_CON
4 3 1 2 2 1 Release memo and use
C132 0.1U_0402_10V7-K
0.1u 25V sample to +3V_MUX
MUX_TYPEC_TXN1 1 2 MUX_TYPEC_C_TXN1 1 2 TYPEC_CON_TXN1 PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 replace 0.1u 50V for SIT.
1 2 2
C131 0.1U_0402_10V7-K D74 EMC_TC@ EMC_TC@
D75
TYPEC@ L16 EMC_TC@ C889 TYPEC@
USB20_P1_B_CON 1 2 2 1USB20_N1_B_CON R121 1 TYPEC@2 100K_0402_5% DOCK_AUX#_TYPEC
1 2 2 1 0.1U_0402_25V6-K
R134 1 @ 2 0_0402_5% 1
R122 1 2 100K_0402_5% DOCK_AUX_TYPEC
PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 U19 TYPEC@

9
D77 EMC_TC@ EMC_TC@
D76
R136 1 @ 2 0_0402_5% 2 4 USB20_N1_A

VDD
USBC1_CC2_CONN_R
1 2 2 1USBC1_CC1_CONN_R [15] USB20_N1 Y- M-
1 2 2 1 1 5 USB20_P1_A
[15] USB20_P1 Y+ M+ +3V_MUX
TYPEC@ L18 EMC_TC@
MUX_TYPEC_TXP2 1 2 MUX_TYPEC_C_TXP2 1 2 TYPEC_CON_TXP2 PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 USB_SEL 10 6 USB20_N1_B
1 2 [54] USB_SEL SEL D-
C133 0.1U_0402_10V7-K D79 EMC_TC@ EMC_TC@
D78
USB_OE# 8 7 USB20_P1_B
[54] USB_OE#

GND
MUX_TYPEC_TXN2 1 2 MUX_TYPEC_C_TXN2 4 3 TYPEC_CON_TXN2 USBC_DPAUX1_R 1 2 2 1USBC_DPAUX2_R OE D+ R128 1 @ 2 4.7K_0402_5% ADDR
4 3 1 2 2 1

2
C134 0.1U_0402_10V7-K
TYPEC@ EXC24CH900U_4P R888 R129 1 @ 2 4.7K_0402_5%

3
PESD5V0H1BSF SOD962 PESD5V0H1BSF SOD962 100K_0402_5% PI3USB102ZMEX_UQFN10_1P4X1P8
R139 1 @ 2 0_0402_5%
TYPEC@ TYPEC@

1
R148 1 2 2M_0402_1% USBC_DPAUX2
TYPEC@

R887 1 @ 2 0_0201_5%
20160414 R149 2 1 2M_0402_1% USBC_DPAUX1
1. Swap L35 by layout request TYPEC@
EXC24CH900U_4P 20160414
USB20_N1_A 4 3 USB20_N1_A_CON VCCPD_VBUS_CONN
4 3 1. Delete D30,D37 and add D72~D80
B for layout placement B
USB20_P1_A 1 2 USB20_P1_A_CON 2. Add U20 (OVP protection circuit)
1 2 EMC_TC@
UCLAMP2271P.TNT SGP1610N2

20160419
1

L35 EMC_TC@ D80

1. Co-lay F11 20160330
1

R886 1 @ 2 0_0201_5% 1.Add CC/SBU

20160621 protection solution USBC_DPAUX1 R897 1 @ 2 USBC_DPAUX1_R
Mark D80 as EMC_TC@ for EMI
0_0201_5% +3V_MUX
R850 1 2 0_0201_5% 20160505 USBC_DPAUX2 R898 1 @ 2 USBC_DPAUX2_R
2

@
1. Unstaff U20 and staff 0_0201_5%

25
26
27
28
29
2

JUSB1 R897,R898,R899,R900 USBC1_CC1_CONN R899 1 @ 2 USBC1_CC1_CONN_R

EXC24CH900U_4P due to U20 martirail shortage. 0_0201_5% 1

GND25
GND26
GND27
GND28
GND29
USB20_N1_B 4 3 USB20_N1_B_CON USBC1_CC2_CONN R900 1 @ 2 USBC1_CC2_CONN_R TYPEC@
4 3 0_0201_5% C950
201616 1U_0201_6.3V6-M
USB20_P1_B 1 2 USB20_P1_B_CON 24 1 FLT pin into U5 pin30 U20 2
1 2 GND_B12 GND_A1
L17 EMC_TC@ TYPEC_CON_RXP1 23 2 TYPEC_CON_TXP1 20160624 10
RX1+_B11 TX1+_A2 1. Change VPER to +3V_MUX VPWR
R851 1 @ 2 0_0201_5% TYPEC_CON_RXN1 22 3 TYPEC_CON_TXN1 USBC_DPAUX1 15 1 USBC_DPAUX1_R
RX1-_B10 TX1-_A3 USBC_DPAUX2 14 SBU1 C_SBU1 2 USBC_DPAUX2_R
20160719 SBU2 C_SBU2
21 4
VBUS_B9 VBUS_A4 1. U20 martirail prepare ready. USBC1_CC1_CONN 12 4 USBC1_CC1_CONN_R
USBC_DPAUX2_R USBC1_CC1_CONN_R [54] USBC1_CC1_CONN USBC1_CC2_CONN CC1 C_CC1 USBC1_CC2_CONN_R
R140 1 @ 2 0_0402_5% 20 5 11 5
SBU2_B8 CC1_A5 [54] USBC1_CC2_CONN CC2 C_CC2
USB20_N1_B_CON 19 6 USB20_P1_A_CON USB20_N1_A_CON 20 7
EXC24CH900U_4P D-_B7 D+_A6 USB20_P1_A_CON 19 D1 RPD_G1
MUX_TYPEC_RXP1 4 3 TYPEC_CON_RXP1 USB20_P1_B_CON 18 7 USB20_N1_A_CON USB20_N1_B_CON 17 D2 6
4 3 D+_B6 D-_A7 USB20_P1_B_CON 16 D3 RPD_G2
USBC1_CC2_CONN_R 17 8 USBC_DPAUX1_R D4 9 3V_TPD8S300_FLT# [54]
MUX_TYPEC_RXN1 1 2 TYPEC_CON_RXN1 CC2_B5 SBU1_A8 3 FLT
1 2 16 9 VBIAS 8
VBUS_B4 VBUS_A9 1 GND1
L19 EMC_TC@ TYPEC@ 13
TYPEC_CON_TXN2 15 10 TYPEC_CON_RXN2 C951 GND2 18
R143 1 @ 2 0_0402_5% TX2-_B3 RX2-_A10 1U_0402_25V6-K GND3 21
TYPEC_CON_TXP2 14 11 TYPEC_CON_RXP2 2 THERMAL_PAD
A TX2+_B2 RX2+_A11 A
TPD8S300_QFN20_3X3
13 12 TYPEC@
R144 1 @ 2 0_0402_5% GND_B1 GND_A12
GND34
GND33
GND32
GND31
GND30

L20 EMC_TC@
MUX_TYPEC_RXP2 1 2 TYPEC_CON_RXP2
1 2
HIGHS_UB11126-A5A0B-1H
34
33
32
31
30

ME@
MUX_TYPEC_RXN2 4 3 TYPEC_CON_RXN2
4 3 Security Classification LC Future Center Secret Data Title
EXC24CH900U_4P
Issued Date 2015/09/01 Deciphered Date 2016/12/31 TYPE-C_MUX
R147 1 @ 2 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 55 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/10/5 Deciphered Date 2016/12/31 DOCKING/ DCIN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 56 of 82
5 4 3 2 1
 5 4 3 2 1

+3VALW

RE41 +3VL_EC
Vcc 3.3V +/- 5%
1 1 2
HDD_DETECT# [42] PM_SLP_S3# 1 TP8 100K +/- 1%
10K_0402_1% RE1
15K_0402_1% PM_SLP_S4#

2
RE38 1 TP9 Board ID min typ
RE1
RE2 VAD_BID V AD_BID VAD_BID max Phase
2

PM_SLP_S5# 1 TP10 100K_0402_1%

TEMBER_DETECT# 0 0K +/- 5% 0 V 0 V 0 V SDV
PBTN_OUT# 1 TP12
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V FVT

1
Board_ID
2 18K +/- 5% 0.436 V 0.503 V 0.538 V SIT
RE42
3 33K +/- 5% 0.712 V 0.819 V 0.875 V SVT

1
1 2
SSD_DET_EC# [42]
20160419 RE2 4.7K +/- 5% 0.141
D
18K_0402_1%
4 V 0.148 V 0.155 V D
33K_0402_1% Change RE2 to 18K
for SIT board ID 5 24K +/- 5% 0.612 V 0.638 V 0.664 V
20160127

2
1. Add TEMBER_DETECT# circuit +3VL +3VL_EC +3VL_AVCC
2. Change Resistor value All capacitors close to EC
LE1
CE1 CE2 CE3 CE4 CE5 CE6 RE3 1 2 1 2

+3VALW

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K
0_0603_5% BLM18PG121SN1D_2P
+3VL_EC
1 1 1 1 1 1 1 1
@ @
1 2 HDD_DETECT# CE7 CE8 ACIN RE5 1 2 10K_0402_5%
RE4 100K_0402_5% 1000P_0402_50V7-K 0.1U_0402_25V6-K
2 2 2 2 2 2 2 2
@ EC_AGND RE6 1 2 0_0402_5%
ACPRN [67]
+3VALW
DEV1 @ 2 1 RB751V-40_SOD323-2

RE22 1 2 10K_0402_5% AOU_IFG# CE9 1 2 100P_0402_50V8-J

RE23 1 2 10K_0402_5% KB_FN Close to EC +3VS
CE10
1 2 +VCOREVCC

0.1U_0402_25V6-K

114
121
127
RE25 1 2 10K_0402_5% KSO1
minimum trace width 12 mil

12

11

26
50
92

74
3
RE26 1 2 10K_0402_5% KSO2 UE1
RE27 1 2 10K_0402_5% FAN_ID

VBAT

VCORE

VCC

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)

AVCC
RE28 1 2 10K_0402_5% LAN_WAKE#

KBRST# 4 24 LOGO_LED#
1 2 10K_0402_5% EC_WAKE# [11] KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 AOU_IFG# LOGO_LED# [37]
RE7 SERIRQ AOU_IFG# [44]
[11,58] SERIRQ LPC_FRAME# SERIRQ/GPM6 PWM1/GPA1
1 6 28
[11] LPC_FRAME# LPC_AD3 7 LFRAME#/GPM5 PWM2/GPA2 29 PWRBTN_LED# EC_ON2 [76,77]
C CE13 C
[11] LPC_AD3 LPC_AD2 LAD3/GPM3 PWM3/GPA3 PWRBTN_LED# [61]
10P_0402_50V8-J EMC_NS@
[11] LPC_AD2
8
LAD2/GPM2
PWM PWM4/GPA4
30
VR_ON [70]
+5VALW
LPC_AD1 9 31 EC_FAN_PWM
2 [11] LPC_AD1 LPC_AD0 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM [61]
BEEP#
[11] LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 VCCST_PG_EC BEEP# [52] USB_ON# 1 2
LPC RE10 10K_0402_5%
[11] CLK_PCI_EC 14 LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 OTP_RESET VCCST_PG_EC [12]
[28] WRST# WRST#
+3VS PD_VBUS_C_CTRL1_EC 15 WRST# TMRI0/GPC4 OTP_RESET [65]
124 SUSP#
[65]
PD_VBUS_C_CTRL1_EC EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# [50,69]
[48] EC_RX PWUREQ#/BBO/SMCLK2ALT/GPC7 +3VS
RE29 1 2 10K_0402_5% LPC_FRAME# 1
EC_TX 17 66 TEMBER_DETECT#
[48] EC_TX LPCPD#/GPE6 ADC0/GPI0
+3VL_EC RE30 1 2 10K_0402_5% EC_FAN_SPEED PLT_RST# 22 67 CP_BYPASS
[12,28,42,46,48,49,58] PLT_RST# EC_SCI# LPCRST#/GPD2 ADC1/GPI1 BATT_TEMP CP_BYPASS [63]
CE11 23 68 BATT_TEMP [66,67]
[11] EC_SCI# ECSCI#/GPD3 ADC2/GPI2
RE31 1 2 10K_0402_5% LID_SW# 1U_0402_10V6-K OTG 126 ADC 69 Board_ID CP_CLK RE13 1 2 4.7K_0402_5%
2 [67] OTG GA20/GPB5 ADC3/GPI3 FAN_ID
70

+3VL_EC
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
TP_RESET
FAN_ID
ADP_I
[61]
[67]
CP_DATA RE14 1 2 4.7K_0402_5%
TP_RESET [63]
20160307 [60] KSI[0..7]
KSI[0..7] KSI0 58
KSI0/STB#
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADP_ID
ADP_ID [65]
KSI1 59 78 VGATE
RE11 1 2 100K_0402_5%WRST#
Stuff CE11 for WRST singal KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON_EC VGATE [70]
[60] KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 MAINPWON_EC [65,66,68]
RE32 1 2 2.2K_0402_5% EC_SMB_CK1 KSI3 61 DAC 80 H_PROCHOT_EC
Un-stuff if not necessary.
+3VS RE33 1 2 2.2K_0402_5% EC_SMB_DA1 KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 ENBKL
KSI4 DAC5/RIG0#/GPJ5 ENBKL [5]
RE34 1 2 2.2K_0402_5% EC_SMB_DA3 KSI5 63
RE35 1 2 2.2K_0402_5% EC_SMB_CK3 KSI6 64 KSI5 85 AOU_EN
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 PBTN_OUT# AOU_EN [44]
KSI7
36 KSI7 PS2DAT0/TMB1/GPF1 87 EC_SMB_CK2 PBTN_OUT# [12]
KSO0
37 KSO0/PD0 GPF2 88 EC_SMB_DA2 EC_SMB_CK2 [54] VR_HOT#
KSO1
KSO1/PD1 Int. K/B PS2 GPF3 EC_SMB_DA2 [54] [6,67,70] VR_HOT#
KSO2 38 89 CP_CLK
KSO2/PD2 Matrix PS2CLK2/GPF4 CP_DATA CP_CLK [63]
KSO3 39 90 1
KSO3/PD3 PS2DAT2/GPF5 CP_DATA [63] D

1
KSO4 40 CE12
KSO5 41 KSO4/PD4 96 BATT_CHG_LED# H_PROCHOT_EC 2
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 PWR_STATUS_LED# BATT_CHG_LED# [61]
RE36 1 2 100K_0402_5%SUSP# KSO6 42 97 G 47P_0402_50V8-J
KSO6/PD6 GPH4/ID4 PWR_STATUS_LED# [61] 2
KSO7 43 98 ACOFF QE1 S
KSO7/PD7 GPH5/ID5 ACOFF [67]

3
KSO8 44 99 PCH_PWROK 2N7002WT1G_1N_SC-70-3
KSO8/ACK# GPH6/ID6 PCH_PWROK [12]
RE37 1 2 100K_0402_5%SYSON KSO9 45
KSO10 46 KSO9/BUSY 101 FSCE#
51 KSO10/PE NC1 102 SPI_FMOSI# FSCE# [21]
KSO11
KSO11/ERR# NC2 SPI_FMISO SPI_FMOSI# [21]
KSO12 52 SPI Flash ROM 103
53 KSO12/SLCT NC3 105 SPI_FSCK SPI_FMISO [21]
KSO13
54 KSO13 NC4 SPI_FSCK [21]
KSO14
KSO15 55 KSO14
KSO16 56 KSO15 108 ACIN
KSO17 57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW#
B
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# [61]
B

ON/OFF# 110 82 PCH_SYSPWROK

[61] ON/OFF# PWRSW# EGAD/GPE1 EC_ON PCH_SYSPWROK [12]
111 SM Bus 83 EC_ON [68]
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 AOU_CTL1
[66,67] EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 [44]
RE17 [66,67] EC_SMB_DA1 SMDAT1/GPC2 PM_SLP_S5#
1 2 PECI 117 GPIO 77 PM_SLP_S5# [12]
[6] H_PECI ADAPTER_ID_ON# 118 SMCLK2/PECI/GPF6 GPJ1 100 EC_MUTE#
43_0402_5%[65] ADAPTER_ID_ON# EC_SMB_CK3 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106 VGA_PWR_LIM EC_MUTE# [51]
[11,28,59,62] EC_SMB_CK3 EC_SMB_DA3 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 ME_FLASH VGA_PWR_LIM [28]
95 104
[11,28,59,62] EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 ME_FLASH [9]
+3VL_EC DTR1#/SBUSY/GPG1/ID7 119 SYSON [50,69,78]
BKOFF#
CRX0/GPC0 123 DCIN_ATTACHED2 BKOFF# [37]
CTX0/TMA0/GPB2 PM_SLP_S3# DCIN_ATTACHED2 [65]
112 18 PM_SLP_S3# [12]
LAN_WAKE# 125 VSTBY0 RI1#/GPD0 21 PM_SLP_S4#
[46] LAN_WAKE# GPE4 RI2#/GPD1 INT#_TYPEC PM_SLP_S4# [12]
WAKE UP 76 INT#_TYPEC [54]
TACH2/GPJ0 48 AOU_CTL3
TACH1A/TMA1/GPD7 EC_FAN_SPEED AOU_CTL3 [44] +3VL_EC
47 EC_FAN_SPEED [61]
USB_ON# 33 TACH0A/GPD6 19 CAP_LED#
[44] USB_ON# CP_RESET# CP_RESET#_EC 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 KB_FN CAP_LED# [60]
1 2 GPIO 20 KB_FN [60] MIRROR@
[63] CP_RESET# EC_RSMRST# 93 RTS1#/GPE5 L80LLAT/GPE7 EC_ON 1 2
RE18 0_0402_5% RE19 10K_0402_5%
[12] EC_RSMRST# CLKRUN#/GPH0/ID0

EC_WAKE# 2
Please don't place any PU Resistor on GPG[7:2] +3VL_EC
[6] EC_WAKE# AC_PRESENT CK32KE/GPJ7 (Reserve hardware strapping)
128 Clock
[12] AC_PRESENT CK32K/GPJ6 MIRROR@
EC_MUTE# RE20 1 2 10K_0402_5%

RE21 1 @ 2 10K_0402_5%
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

IT8586E-AX_LQFP128_14X14 IT8586E/ FX LQFP

1. Version CX : Don't Support Mirror Code
1

27
49
91
113
122

75

SA00005W940 Version DX/ EX/ FX : Support Mirror Code

2. For Mirror Code
EC_AGND
"H" --> Enable
A
"L" --> Disable (Default) A
LE2 1 2 *
BLM18PG121SN1D_2P

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 EC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A2 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 57 of 82
5 4 3 2 1
 A B C D E

TPM IC

1 1

+3V_SPI

1 1
C137
TPM@ C138 TPM@
0.1U_0402_10V6-K 10U_0603_6.3V6-M
2 2

+3V_SPI NOTE:
Place 0.1 uF capacitors as close as
possible to the device power pins.

1 1 1 1
C139 C140 C141 C142 +3V_SPI +3VS
TPM@ TPM@ TPM@ TPM@
2 2

2
10U_0603_6.3V6-M

0.1U_0402_10V6-K

0.1U_0402_10V6-K

0.1U_0402_10V6-K
2 2 2 2 R168
10K_0402_5%

2
TPM@
R173

22

14
1

1
UTPM1 TPM@ @ 10K_0402_5%

VDD
VHIO2

VHIO1

VSB

1
15 4 PP 1 TP13
SERIRQ R169 1 @ 2 0_0402_5% SERIRQ_R 18 LAD3 PP 3 GPIO2
[11,57] SERIRQ SPI_SI SPI_SI_R LAD2/SPI_IRQ GPX/GPIO2
R170 1 TPM@ 2 33_0402_5% 21 30 GPIO01 1
[11,21] SPI_SI SPI_SO SPI_SO_R LAD1/MOSI SCL/GPIO1
R171 1 TPM@ 2 33_0402_5% 24 TP14
[11,21] SPI_SO SPI_CS2#_TPM SPI_CS2_R LAD0/MISO
R172 1 TPM@ 2 33_0402_5% 20
[11] SPI_CS2#_TPM LFRAME/SCS
27
SPI_CLK R174 1 TPM@ 2 33_0402_5% SPI_CLK_L 19 SERIRQ SDA/GPIO0 29
[11,21] SPI_CLK LCLK/SCLK 6 GPIO03 1 TP15
TP16 1 GPIO04 13 GPIO3/BADD 5
PLT_RST# 17 CLKRUN/GPIO04/SINT TEST
Follow THP1_SWG_SIT_EC005, update TPM table [12,28,42,46,48,49,57] PLT_RST# LRESET/SPI_RST/SRESET
NOTE:
Follow the SPI topology layout guidelines 28 2
in the relevant Intel Platform Design Guide. LPCPD NC1 7
NC2 10
NOTE: NC3 11
NC4
Check timing sequence in SDV phase. 12
Reserved NC5
25
26
NC6

2
31
R175 NC7

GND1

GND2

GND3

GND4
5 ms < t 10K_0402_5% 33
NOTE: TPM@ EX-PAD
1) It is recommended to connect the TPM to the system's
standby voltage to improve performance.

1
2) SPI_RST# must be asserted for at least 5 msec after SLB9670VQ1P2_VQFN32_5X5

16

23

32
0 < t
VSB
VSB power-up.
3) VSB may come up anytime before VDD power-up,
SA000075L10
3 3
but not after VDD power-up.
4) SPI_RST# may be asserted together with VDD power
negation, but should not at any point exceed 0.5V
VDD above the VDD power level.
1 ms < t

SPI_RST#

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 58 of 82
A B C D E
 A B C D E

1 1

+3VS +3VALW +3VS_GS

@
1 2
RG1 0_0402_5%

1 2
RG6 0_0402_5%
@
TABLE

P/N Mode Selection

+3VS_GS
H I2C Mode

2 L SPI Mode 2

APS G-Sensor
+3VS_GS +3VS_GS
TABLE

1U_0402_10V6K

10U_0603_6.3V6-M
1 1
P/N ADDR_SEL Address

CG1

CG2
RG2 RG3 +3VS_GS
2 2
10K_0402_5% 10K_0402_5%
H 32h (W) & 33h (R)
LIS3DSHTR

14
1

2
L 30h (W) & 31h (R) UGSEN1
RG5

Vdd
Vdd_IO
8 10K_0402_5%
4 CS
[11,28,57,62] EC_SMB_CK3 SCL/SPC
H 3Eh (W) & 3Fh (R) 6 @
[11,28,57,62] EC_SMB_DA3 SDA/SDI/SDO

1
ADDR_SEL 7
KX023-1025 SEL/SDO 11 GSENSE_INT
L 3Ch (W) & 3Dh (R) 16 INT1/DRDY 9 GSENSE_INT2 1
EC_SMB_CK3/DAT3 GND_4 INT2 TG1
PU AT EC SIDE, 15
13 RES_2 10
+3VS AND 4.7K GND_3 RES_1

2
2

GND_1

GND_2
RG4 3 NC_1
NC_2
10K_0402_5%

12
LIS3DSHTR_LGA16_3X3
3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 G SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 59 of 82
A B C D E
 5 4 3 2 1

D D

C C

RTC CONN. KB CONN

JKB1 ME@
KSI[0..7] KSI1 1
[57] KSI[0..7] 1
KSI7 2
KSO[0..17] KSI6 3 2
[57] KSO[0..17] 3
B KSO9 4 B
KSI4 5 4
R179 5
D12 JRTC1 KSI5 6
1 2 1 2 +RTCBATT_R 1 KSO0 7 6
+RTCBATT 1 7
2 KSI2 8
RB751V-40_SOD323-2 1K_0603_5% 2 KSI3 9 8
SCS00008K00 3 KSO5 10 9
4 GND1 KSO1 11 10
GND2 KSI0 12 11
TE_2041180-2 KSO2 13 12
KSO4 14 13
ME@ 14
+3VS KSO7 15
KSO8 16 15
KSO6 17 16
17

1
KSO3 18
R180 KSO12 19 18
300_0402_5% KSO13 20 19
KSO14 21 20
KSO11 22 21
22

2
KSO10 23

+3VS_KBLED
KSO15 24 23

CAP_LED#
+3VS_KBLED 25 24
CAP_LED# 26 25
[57] CAP_LED# F1_LED# 26
27
[14] F1_LED# F4_LED# 27
28
[14] F4_LED# KB_FN 28
29
[57] KB_FN 29

3
30
D81 KSO16 31 30 33
PESD5V0U2BT_SOT23-3 KSO17 32 31 GND1 34
EMC@ 32 GND2

JAE_FL10F032HA2R3000
1

20160419
A 1. Add D81 by EMC request A
20160420
1. Swap pin2 and pin3

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 KB/RTC/TOUCH PAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 60 of 82
5 4 3 2 1
 5 4 3 2 1

FAN CONN. PWR BTN

+3VALW
LED2 PWRBTN_LED#
[57] PWRBTN_LED#
R424 300_0402_5%
3BATT_CHG_LED#_R 1 2BATT_CHG_LED#
BATT_CHG_LED#
[57] BATT_CHG_LED#
1
R430 300_0402_5%
D 2PWR_STATUS_LED#_R 1 2PWR_STATUS_LED# PWR_STATUS_LED# D
[57] PWR_STATUS_LED#
20160424
1. Change R430/R423 from 100 to 300 12-22/S2G6C-C30/2C 3X1 ORG/YELGRN
ohm for LED brightness +3VL
2. Change R422 from 100 to 75 ohm
for LED brightness

1
ON/OFF#
+5VS +VCC_FAN +3VL
ME@
R181
@ HIGHS_WS33050-S0351-HF 100K_0402_5%
R182 1 2
40mil 7
GND2 R422 LED1

2
0_0603_5% 6
GND1 1 2 2 1PWRBTN_LED# SW1

2
5 1 3 ON/OFF#
[57] EC_FAN_PWM 5 ON/OFF# [57]
4 D34
3 4 75_0402_5% LTST-C193KGKT-5A_GREEN 2 4
[57] EC_FAN_SPEED 3 PESD5V0U2BT_SOT23-3
2
1 2 NTC010-AK1G-B160T_4P
[57] FAN_ID 1

1
JFAN1

20160621
Mount D34 for ESD issue

C C

FingerPrint CONN. Lid Switch

+3VS R183 FPR@ +3VS_FRP +3VL +3VL

0_0603_5%
1 2

JFRP1
EMC@ 1
USB20_P9 R410 1 2 0_0402_5% USB20_P9_CON 2 1 U8 U16
B B
[15] USB20_P9 USB20_N9 USB20_N9_CON 2 LID_SW# LID_SW#
R411 1 2 0_0402_5% 3 5 1 LID_SW# [57] 5 1
[15] USB20_N9 3 VCC OUT VCC OUT
EMC@ 4 2 2
5 4 GND1 GND1
5 1
6 C144 1 4 3 1 4 3
6 FPR@ C53 GND2 NC C390 GND2 NC
For EMI choke co-lay
7 0.1U_0402_10V6-K @ TCS10DLU_UFV5 @ TCS10DLU_UFV5
8 GND1 2 0.1U_0402_10V7-K 0.1U_0402_10V7-K
EXC24CH900U_4P GND2 2 2
USB20_P9 4 3 USB20_P9_CON HIGHS_FC1AF061-2201H
4 3
ME@
USB20_N9 1 2 USB20_N9_CON
1 2
L33 EMC_NS@

ESD request
D31
USB20_P9_CON 6 1 USB20_N9_CON

5 2

4 3
A A
AOZ8904CIL_SOT23-6
EMC@

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 PBTN/LID/FP/FAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 61 of 82
5 4 3 2 1
 Thermal Sensor
placed near by VRAM
THU1
+3VS

1 10 EC_SMB_CK3
VCC SCL EC_SMB_CK3 [11,28,57,59]
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SDA EC_SMB_DA3 [11,28,57,59]
1
C145 REMOTE1- 3 8
DN1 ALERT#
0.1U_0402_10V6-K REMOTE2+ 4 7 F75303M_THERM# R184@ 1 2 10K_0402_5%
2 DP2 THERM# +3VS
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10

Address 1001_101xb
Internal pull up 1.2K to 1.5V
R for init i al t her mal shut do wnt e mp

REMOTE2+/ -:
Trace width/ space:10/ 10 mil
Trace length:<8"
Close to U1 Close to +VCC_CORE Close JDIMM1&JDIMM2
REMOTE1+ REMOTE2+ REMOTE1+ REMOTE2+ REMOTE2+

1 1 1 1 1

1
C C C
C146 C147 C148 @ 2 Q5 C149 @ 2 Q6 C380 @ 2 Q7
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3
2 2 2 E
3 SB000010U00 2 E SB000010U00 2 E SB000010U00

3
@
REMOTE1- REMOTE2- REMOTE1- REMOTE2- REMOTE2-

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 Thermal Sensor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 62 of 82
 5 4 3 2 1

D D

Track point
+5VS_TPCP

+5VS_TPCP JTP1
TP_DATA2 1
TP_RESET 2 1
3 2
R185 1 2 4.7K_0402_5% TP_CLK2 4 3
5 4
R186 1 2 4.7K_0402_5% TP_DATA2 TP_CLK2 6 5
7 6
R187 1 @ 2 10K_0402_5% CP_RESET# 8 7
9 8
R511 1 @ 2 10K_0402_5% TP_RESET 10 9
11 10 13
12 11 GND1 14
12 GND2
+3VS

C JAE_FL10F012HA1R3000 C
ME@
R512 1 2 10K_0402_5% TP_RESET

Click Pad
+5VS R310 +5VS_TPCP
0_0603_5%
+3VS 1 2
KYOCE_046811-612-000846

R311 1 2 10K_0402_5% CP_BYPASS 12 14

CP_SMB_CLK 11 12 GND2 13
[11,22,23] CP_SMB_CLK 11 GND1
10
TP_DATA2 9 10
TP_CLK2 8 9
B B
CP_SMB_DAT 7 8
[11,22,23] CP_SMB_DAT 7
6 20160414
CP_RESET# 5 6
[57] CP_RESET# CP_CLK 5 1. Change JCP1 foot print
4
TP_CLK2

TP_DATA2

CP_DATA

CP_CLK

[57] CP_CLK CP_DATA 4

3
[57] CP_DATA TP_RESET 3
2
[57] TP_RESET CP_BYPASS 2
1
[57] CP_BYPASS 1
JCP1
ME@
2

1 1
D82
C150 C151 PESD5V0U2BT_SOT23-3
100P_0402_50V8J 100P_0402_50V8J EMC@
EMC_NS@ 2 2 EMC_NS@
1

20160419
1. Add D81 by EMC request
2. Delete D66 and connect to C150/C151

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 CP/TPOINTCONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 63 of 82
5 4 3 2 1
 5 4 3 2 1

D D

Screw Hole

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10

@ @ @ @ @ @ @ @ @ @

1
PAD_CB6P0D3P3 PAD_CB6P0D3P3 PAD_CB6P0D3P3 PAD_CB6P0D3P3 PAD_C5P0D2P5 PAD_C6P0D2P5 PAD_CT5P0B6P0D2P5 PAD_C6P0D2P5 PAD_C5P5D2P5X3P0 PAD_C6P0D2P5X3P0

H11 H12 H13 H14 H15

@ @ @ @ @ 20160419

1
Change H9/ H10/ H11/ H12 footprint
PAD_CT5P0B6P0D2P5X3P0 PAD_C6P0D2P5X3P0 PAD_C6P0D2P5 PAD_CT8P0B6P0D2P5 PAD_CT8P0B5P0D2P5

H16

C C
@

1
PAD_O3P0X2P5D3P0X2P5N

H17 H18 H19

@ @ @
1

1
PAD_C6P0D3P3 PAD_CT6P0D3P2 PAD_CT6P0D3P2
H20 H21 H22 H23 H24

@ @ @ @ @
1

1
PAD_CT6P0D3P2 PAD_C6P0D2P5 PAD_CT5P0B6P0D2P5 PAD_SHAPET7P0X10P0CB6P0D2P5 PAD_SHAPET7P0X10P0CB6P0D2P5

H25
Center Zero
B B
@
1

H_2P5N

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 P64-PLM/SCREW HOLE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 64 of 82
5 4 3 2 1
 5 4 3 2 1

+3VALW

PD1
CUS357_SOD323-2

2
VSYSTEM
PR4 PD2 1 2
@ PR53 1SS355VMTE-17 PR1 PR2 VSYSTEM2
750_0402_1%
0_0402_5% 100K_0402_1% 10K_0402_1%
1 2 2 1 1 2 1 2 1 2
[57,66,68] MAINPWON_EC B+

1
PD4 @ PR5
CUS357_SOD323-2 1M_0402_5% PD3 UMA@

2
CUS357_SOD323-2 PR999

NTJD5121NT1G
0_0402_5%

3
PQ1 2 1
E

6
D 2 PR3
@ PR6
B
2 ADAPTER_ID_ON

PQ4A
0_0402_5% PMBT3906 750K_0402_5%

1
NTJD5121NT1G
C
G

1
S VGA DIS@ VCCGT

1
D 1.2VS D

3
D 540_0402NEW_30%
PR7 540_0402NEW_30% 540_0402NEW_30%

1
5 PRT1 PRT2 PRT3

PQ4B
10K_0402_1% PR8 ADAPTER_ID_ON# [57] C
1 2 G PQ2 2 2 1 2 1 2 1
ADP_ID [57]1M_0402_5% PMBT3904 B
S

4
E 2

1
D

1
PC1 2
1
A/D 1U_0603_25V7K G
OTP_RESET [57]

1
1
1

S PQ3 2N7002WT1G

3
680P_0402_50V7-K

PD5 2 1 2 1 2 1
0.1U_0402_6.3V
2

2 AZ5425-01F_DFN1006P2E2

2
PC2

PC3

PRT6 PRT5 PRT4

540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

1
PR50 Charger VCCSA VCORE
300K_0402_1%

@ PR51

2
0_0402_5%
1 2
DCIN_ATTACHED2 [57]

2
1
PR52

0.1U_0402_25V6
PC20 53.6K_0402_1%

1
RTC Battery
EMC@ PL1
BLM18KG300TN1D_2P
PQ5
EMC@ 1 2
VSYSTEM AON7409
PL2 1
JDCIN1
APDIN PF1 BLM18KG300TN1D_2P 2
3 7A_32V_0437007.WR 3
DETECT(ID) 2 APDIN2 1 1 2 5 VSYSTEM2 +3VL
POWER1 4
POWER2 1
GND1 EMC@ EMC@ EMC@ EMC@

2
5
1000P_0402_50V7-K

200K_0402_1%
GND2

1
6
1000P_0402_50V7-K
100P_0402_50V8-J

100P_0402_50V8J

PR18
GND3 7 PR21 @ PC18
GND4 3.01K_0402_1%
1

0.1U_0402_25V6

2
HIGHS_PJSS0056-PB01H-LC
+RTCBATT

1
ME@
2

<10,50> 1 2
PC4

PC5

PC6

PC7

PD6

2
CUS357_SOD323-2
1

PR20 PR19
PR24 100K_0402_5% 43K_0402_1%
402K_0402_1%

1
C C
2

PR38

1
D
82K_0402_5%
DCIN_ATTACHED1 1 2 2 PQ6
[67] DCIN_ATTACHED1 G 2N7002WT1G_SC-70-3
S
3
1

PC17 PR25

2PD_VBUS_C_CTRL1
0.1U_0402_25V6 100K_0402_5%
2

D
TYPEC@
2

PQ12 2
2N7002WT1G_SC-70-3 G
S
3

DCIN_ATTACHED# [65]
VSYSTEM

PR57
47K_0402_1%
TYPEC@ TYPEC@
6

1
D
1

PQ17A 2 TYPEC@
G PR59
NTJD5121NT1G S 1M_0402_5%
1

3
D
TYPEC@

2
5
PQ17B G

1
NTJD5121NT1G S
4

TYPEC@
PR58
2 100K_0402_5%

@ PJ2 @ PJ1
JUMP_43X79 JUMP_43X79

2 1 2 1
40V PROPECTION 2 1 2 1

@ PQ7 PQ19 TYPEC@

AON6248_DFN8-5 AON7466 TYPEC@ TYPEC@
B @ PR26 1 3 PQ9 PQ10 B
0.005_1206_1% 2 2 AON7409 AON7409
1 2 5 3 5 1 VCCPD_VBUS1 1 VBUS_Q_VINT20 1
VCCPD_VBUS 2 2 VSYSTEM2
TYPEC@ 3 3
1

1
5 TYPEC@ 5
4

@ PR31 PC16 TYPEC@

1 47_0402_5% 4.7U_0603_25V6-M TYPEC@ PC19 PR34
2

4
1 3

2PD_VBUS_C_CTRL1
@ PC15 0.1U_0402_25V6 200K_0402_1%
C
1

15U_B2_25V + 1 2
E

2
1

@ PR27 @ PC11 PQ14

10_0402_1% 10U_0805_25V6-K TYPEC@ PMBT3906
B
2

2 @ PC14 PR47
1 2 0.01U_0603_50V7-K VBUS_C_CTRL0 [54] 1M_0402_5% TYPEC@
1

1 1 2
2
1

1
PR48 TYPEC@ VSYSTEM
@ PC12 @ PR39 PR63 20K_0402_1%
0.47U_0402_25V6-K 100K_0402_1% 10M_0402_5% PR35 TYPEC@
2
1

100K_0402_5% PR54
2

1
2

@ PR28 TYPEC@ TYPEC@ 47K_0402_1%

2

2
20K_0402_1% PR49 TYPEC@
ISENSE

DRV
VIN

VOUT

1
D D
@ PR32 100K_0402_5%

1
100K_0402_1% 2 1 2 PQ15 2 TYPEC@
VSYSTEM
2

1 8 2 1 G 2N7002WT1G_SC-70-3 @ PQ16A G PR56

VCNTL POK +3VPD
2

S NTJD5121NT1G S 1M_0402_5%
3

3
D
TYPEC@

2
1
10 @ PU2 7 PR46 @ PC21 5

0.1U_0402_25V6
VINSEL OCSET 100K_0402_5% G
1

1
0.1U_0402_25V6
S
1

1
9 6

PC22 @
@ PR61 @ PR60 @ PR29 TYPEC@ PR22
169K_0402_1% 3.9K_0402_5% 3.9K_0402_5% EN DELAY 0_0402_5% @ PQ16B TYPEC@
2DCIN_ATTACHED
2

1 NTJD5121NT1G PR55
GND

[65] DCIN_ATTACHED#

2
1

130K_0402
PD_VBUS_C_N1
2

2
1

@ PR33 PR37
@ PR40 @ PC13 27.4K_0402_1% TYPEC@ PR23 TYPEC@ 47K_0402_1% TYPEC@
11
1

1
D D
0.1U_0402_25V6 0_0402_5%
2

2 100K_0402_1% 1 2 1 2 2 PQ11
[54] PD_VBUS_C_CTRL1
2

G @ PQ18 @ PR30 G 2N7002WT1G_SC-70-3

1

2N7002WT1G_SC-70-3 0_0402_5% APL3542AQBI-TRG_TDFN10_3X3 @ PC23

0.1U_0402_25V6

S S
3

2
@ PR62 1 2
+3VPD
1

24.3K_0402_1% TYPEC@ @ PR45

2

0_0402_5%
PR36
2

100K_0402_5%

1
2

@ PR44
TYPEC@ 0_0402_5%
1 2
TYPEC@ PR41 @ PR43
1

D D
0_0402_5% 0_0402_5%
DCIN_ATTACHED1 1 2 2 PQ8 PQ13 2 1 2
PD_VBUS_C_CTRL1_EC [57]
2N7002WT1G_SC-70-3

2N7002WT1G_SC-70-3

G @ G

1
S S
3

@ PR42
A A
100K_0402_5%
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 DCIN / VIN Detector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 65 of 82
5 4 3 2 1
 5 4 3 2 1

D D

PL3 EMC@
MURATA BLM18KG300TN1D
PRT7 under CPU bottom side for CPU thermal protection.
VMB2 VMB 1 2
ME@ JBATT1 PF2 This is for thermal team request.
SUYIN_125022HB008M203ZL 12A_32V_0501012.WRS PL4 EMC@
9 1 2 1 MURATA BLM18KG300TN1D
PTH1 1 2 BATT+
10 2 3 EC_SMCA 1 2
PTH2 3 4 EC_SMDA
11 4 5
PTH3 5 6 EMC@ EMC@

2
12 6 7 PC9 PC10 +5VLP
PTH4 7 8 1000P_0402_50V 0.01U_0402_25V +3VALW
8 +3VL

1
2

1
PESD5V0U2BT_SOT23-3
1

1
PC8

EMC_NS@

47K_0402_1%
12.7K_0402_1%
C C

1
PR15 0.1U_0603_16V7K

@ PR10

@ PR11
2
PR14 PR9
100_0402_1%

PD7
15K_0402_1%

1
100_0402_1%

2
PU1

2
NTC_V_1

OTP_N_003
1 8
VCC TMSNS1
@ PR13 2 7 OTP_N_002 2 1

100K_0402_1%_NCP15WF104F03RC
0_0402_5% GND RHYST1
EC_SMB_CK1 [57,67] [57,65,68] MAINPWON_EC 1 2 3 6 PR12
OT1 TMSNS2

1
20K_0402_1%
4 5
EC_SMB_DA1 [57,67] OT2 RHYST2

PRT7
PR16 G718TM1U_SOT23-8
100K_0402_1%

2
2 1 +3VALW

B
1 2
A/D B
BATT_TEMP [57,67]
PR17
10K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 66 of 82
5 4 3 2 1
 5 4 3 2 1

PQ114
AON7380 3
2
5 1

VSYSTEM2

4
D
EMC@ PQ104
D
PL102 AON7380
1UH_PCMB053T-1R0MS_7A_20% PR101 3 3
PL101
0.01_1206_1% 2 2
1 2 VSYSTEM3 1 2 VBUS 5 1 EMC@ 1 2 EMC@ 1 5 EMC@ EMC@

33U_D2_25VM_R40M
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
B+

2200P_0402_25V7-K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
.01U_0402_50V7-K
1

1
PQ103 2.2UH_PCMB063T-2R2MS_8A_20%

0.1U_0402_25V6-K
EMC@ EMC@
1

1
+ @ PC108 AON7380 PR102 PC106 PC107

PC104

PC109

PC110

PC111

PC112

PC113

PC114

PC116

PC135
PC138

4
5

5
0.1U_0402_25V7K PQ105 56_0402_5% 0.047U_0603_25V PR103
PC102

PC103

PC137
PC136

0.047U_0603_25V

2 2

2 2
2 1 AON7380 56_0402_5%
2

2
2 PR106

1 2

1 2
PC105 4 2.2_0603_5% PR104 4
EMC@ EMC@

1
1000P_0402_50V7-K 2.2_0603_5%
PC115 @ @ PR136 PC117 PC118 AON7380 PQ107

1
2
3

3
2
1
0.1U_0402_25V7K 1 2 330P_0402_50V7-K 30 25 330P_0402_50V7-K PQ106 AON7409
BTST1 BTST2

2
PC130 1
0.1U_0402_25V7K 0_0603_5% LX1_CHG 32 23 LX2_CHG 2 PR110
SW1 SW2

1
3 0.01_1206_1%
DL1_CHG DL2_CHG

2
PC119 29 26 5 1 2
@ PR108 @ PR111 1U_0603_25V7-K LODRV1 LODRV2 BATT+

2
DH1_CHG 31 24 DH2_CHG PC121

1U_0603_25V7-K
0_0402_5% 0_0402_5%

0.1U_0402_25V7K
HIDRV1 HIDRV2

1
1 2

0.1U_0402_25V7K
1 22 PC120

PC122
VBUS VSYS
1

1
1U_0603_25V7-K 0.1U_0402_25V7K

PC131

PC132
2

2
2 21 BATDRV#
ACN BATDRV#
C C

2
3 20
ACP SRP
1 2 VDDA 7 PU101 19
BQ25700_VDD VDDA SRN PR112 10_0603_5% 1 2
PR113 BQ25700RSNR_QFN32_4X4 BQ25700_VDD

1
10_0402_1% 6 28 1 2 PR114 10_0603_5% 1 2
PR117 PR119 40.2K_0402_1% ILIM_HIZ REGN PC124 2.2U_0603_10V7-K
255K_0402_1% 1 2 1 2 PC126 680P_0402_50V7-K
PC125 1800P_0402_50V7-K 16 17 1 2 1 2
COMP1 COMP2
1
PC123 2 1 PC133 PR120 20K_0402_1%

2
1U_0603_25V7-K 100P_0402_50V8-J 1 2
1 2 11 18 PC134 15P_0402_50V8-J
[6,57,70] VR_HOT# PROCHOT# CELL_BATPRES VDDA
2

2 @ PR121 0_0402_5%

1
1 2 13
PR116
220K_0402_1%
[57,66] EC_SMB_CK1 @ PR122 0_0402_5% SCL 8 1 2 PR118
IADPT ADP_I [57]
1 2 12 @ PR127 0_0402_5% 82K_0402_1%
[57,66] EC_SMB_DA1 @ PR123 0_0402_5% SDA 9 1 2
IBAT
1

1 2 4 @ PR129 0_0402_5%
CHRG_OK

2
[57] ACPRN @ PR125 0_0402_5% 10 1 2
PSYS PSYS [70]
2 1 5 @ PR130 0_0402_5%
[57] OTG PR126 10K_0402_1% ENZ_OTG 27
PGND D

1
15

100P_0402_50V8-J

100P_0402_50V8-J

100P_0402_50V8-J
CMPOUT

2
33 2
PAD

2
@ PR132 PR135 14 PQ111 PR124

PC129

PC127

PC128
G
D CMPIN PR131 [57,66] BATT_TEMP
1

B
0_0402_5% 100K_0402_5% S 100K_0402_1% B

3
1 2 2 PQ112 100K_0402_1% 2N7002WT1G_SC-70-3

2
[57] ACOFF G 2N7002WT1G_SC-70-3 2 1

1
S
3
1

PR128
PR133 @ PR134 1M_0402_5%
D

1
10K_0402_1% 0_0402_5%
1 2 2 PQ113
[65] DCIN_ATTACHED1 G 2N7002WT1G_SC-70-3
2

3
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 67 of 82
5 4 3 2 1
 5 4 3 2 1

+3VALW
FSW=750 KHz
B+ @
PU201
SYX198BQNC_QFN10_3X3
TDC:8A
D
2
PJ201
1 EMC@ EMC@ RF_NS@ +3V_VIN 7 2 +3V_PWRGD
OCP:11A D

2 1 EN2 PG @ PR202 PC203

2200P_0402_25V7-K

1
1 0_0603_5% 0.1U_0603_25V7-M

47P_0402_50V8-J

10U_0805_25V6-K
0.1U_0402_25V6-K
+3VALW

1
JUMP_43X79 PR201 8 6 +3VBS 1 2 1 2

PC232
IN BS

PC201

PC202
1M_0402_5% PL201 8A

PC230
2.2UH_PCMB063T-2R2MS_8A_20% PJ202
EMC@ EMC@

2
2

2
9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2 1

2
PR203
@ 0_0402_5% @ JUMP_43X118
3V5V_ON +3VALW_OUT 2 +3VALW_P EMC_NS@

2
1 4 1

2200P_0402_25V7-K
EN1 OUT PR205 PR204

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
@ 0_0402_5% 4.7_0603_5%
+3VALW_FB 100mA 1 1 1 1

1
PR206 3 5 1 2

PC204

PC205

PC206

PC207

PC210

PC211
2.2K_0402_1% FB LDO +3VL

2 1
EC_ON 1 2
[57] EC_ON 1 EMC_NS@ 2 2 2 2

2
PC208
4.7U_0603_6.3V6-K PC209
680P_0402_50V7K
+3VL 2

1
1
47K_0402_1%
1

2
@ PC213 PR208
PR216

0.1U_0402_25V6-K 1M_0402_5%
47K_0402_1%
1

PR217

1
PC212 PR207

2
0.01U_0402_25V7-K 1K_0402_1%
2

D
6

1 2 1 2
2
2

G
D
3

S
1

[57,65,66] MAINPWON_EC 5 NTJD5121NT1G

C G C
S PQ201A
4

NTJD5121NT1G

PQ201B

+3VALW

1
@ PR209
100K_0402_5%
@ PR210
0_0402_5% +5VALW

2
+3V_PWRGD 1 2
FSW=750 KHz
B+ @
PU202
SYX198CQNC_QFN10_3X3 @ PR211
TDC:8A
2
PJ203
1 RF_NS@ EMC@ EMC@ +5V_VIN 8 2 +5V_PWRGD
0_0402_5%
1 2
OCP:11A
2 1 IN PG @ PR212 PC217
2200P_0402_25V7-K
47P_0402_50V8-J

1 0_0603_5% 0.1U_0603_25V7-M
10U_0805_25V6-K

10U_0805_25V6-K
0.1U_0402_25V6-K

+5VALW
1

JUMP_43X79 9 6 +5VBS 1 2 1 2
PC231

PC233

PC215

PC214

PC216

GND BS PL202
PC218 2.2UH_PCMB063T-2R2MS_8A_20% PJ204
8A
2 EMC@ EMC@ 2
2

1 2+5V_VCC 5 10 +5VLX 1 2 +5VALW_P 1

VCC LX PR213 2 1

2
1U_0603_25V6M @ 0_0402_5% @ JUMP_43X118
B 3V5V_ON 1 4 +5VALW_OUT1 2 +5VALW_P EMC_NS@ B

2200P_0402_25V7-K
EN OUT PR214

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
100mA 4.7_0603_5% 1 1 1 1

1
+5VFB 3 7

PC219

PC220

PC221

PC222

PC223

PC224

PC227

PC228
FB LDO +5VLP

1
1 EMC_NS@ 2 2 2 2

2
2
PC225
4.7U_0603_6.3V6-K PC226
680P_0402_50V7K
2

1
PC229 PR215
6800P_0402_25V7-K 1K_0402_1%
1 2 1 2

6800pf soft start 2ms

47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 68 of 82
5 4 3 2 1
 A B C D

PJ301
2 1
2 1
@ JUMP_43X118

PJ302 +1.2V
+1.2VP 2 1
2 1
1
@ JUMP_43X118 1

+1.2VP PJ303
2 1
PJ304 +0.6VSP 2 1 +0.6VS
B+ EMC@ EMC@ RF_NS@ RF_NS@

1
2 1 B+_1.2V
2 1 PC301 @ JUMP_43X39
@ JUMP_43X79 10U_0603_6.3V6M

2200P_0402_25V

47P_0402_50V8-J

68P_0402_50V8J
0.1U_0402_25V6

2
10U_0805_25V6-K

10U_0805_25V6-K
1 1

1
PC302

PC304

PC307

PC305

PC306

255K_0402_1%
PC303
+0.6VS
2

2
2
TDC: 1.5A

1
PR301
100K_0402_1% +0.6VSP

+0.6VSP
+1.2VP
1 2
1.2V

10U_0603_6.3V6M

0.1U_0402_6.3V7-K
2
TDC: 12A

PR302

1
PC308

PC309
OCP: 15A

5
Fsw: 300KHz

14

11

13

19

20

2
PQ301

PGND

VID

VLDOIN

VTT
CS
AON7408L PR303 21
2.2_0603_5% PAD
4 1 2 1 2 18 1
BOOT VTTGND
PC310
0.22U_0603_25V7K DH_1.2V 17
UGATE VTTSNS
2 +0.6VSP
PL301

1
2
3
2
1UH_PCMC063T-1R0MN_+-20% 2

PU301 3
EMC@ EMC@ 1 2 LX_1.2V 16 RT8231AGQW
GND VTTREF_0.6V
+1.2VP PHASE
4 VTTREF_0.6V
EMC_NS@ VTTREF
2

PR306
2200P_0402_25V7-K

PR304 DL_1.2V 15 5.1_0603_5%

LGATE
2

4.7_0603_5% 12 2 1
470P_0402_50V7K
0.1U_0402_25V6

330U_D2_2V_R9M

1 VDD +5VALW

1
PR305

PGOOD
1
1

+ 5 PC315
PC312

PC313

PC311

@ PC314

6.04K_0402_1% 1

TON
VDDQ
1

5
PQ302 0.033U_0402_16V7K

FB

S5

S3

2
AON7380 PC316
2

2 2 1U_0402_10VA-K
EMC_NS@

10
4 2
2

PC317
680P_0402_50V7K

2 TON_1.2V
3
2
1

S5_1.2V

S3_1.2V
@ PR308
1
2

100K_0402_1%
1 2 +3VS
PR307
10K_0402_1% PR310

887K_0402_1%
@ 0_0402_5%
1

1 2

PR309
FB_1.2V
SM_PG_CTRL [7]

@ PR311

1
B+_1.2V 0_0402_5%
1 2 SUSP# [50,57]
1 2
[50,57,78] SYSON

1
3
@ PR312 3

0_0402_5% @ PC318

2
0.1U_0402_6.3V7-K

2
1
@ PR313 @PC319
47K_0402_5% 0.1U_0402_16V

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.2V/+0.6VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 69 of 82
A B C D
 5 4 3 2 1

B+ +5VALW

+VCC_ST

1
1 +3VS

1
PC401 PR401 PR402 PC402
0.01U_0402_25V7-K 1K_0402_5% 2_0402_5% 1U_0402_6.3V6-K
1

2
PC403 2

2
0.1U_0402_6.3V6-K

1
PR403 PR404 2
100_0402_5% 47_0402_5%

2
12

13
PR406

2
D D
10K_0402_1%

VRMP

VCC

1
PR407
@ 0_0402_5%
VR_ON 1 2 37 38 VGATE
[57] VR_ON EN VR_RDY VGATE [57]
PR408 PR409
@ 0_0402_5% 75_0402_5%
VR_SVID_ALRT# 1 2 33 31 1 2 VR_HOT# VR_HOT# [6,57,67]
[16] VR_SVID_ALRT# ALERT# VR_HOT#
PR410
51_0402_5%
VR_SVID_CLK 1 2 34 35 DRVON
[16] VR_SVID_CLK SCLK DRVON DRVON [71,72,73]
PR411
10_0402_5%
VR_SVID_DAT 1 2 32 22 PWM_1A
[16] VR_SVID_DAT SDIO PWM_1A PWM_1A [71]

PSYS 46 29 PR412 1 2 7.5K_0603_1% SW_1A

[67] PSYS PSYS CSP_1A SW_1A [71]

1
2 1 PC441 PR405
PR413 1U_0402_6.3V6-K 12K_0402_1%
PC404 16.5K_0402_1% 1 2

2
1000P_0402_25V7-K
VCC_SENSE 1 2 1 2
[16] VCC_SENSE

1
PR414
3.4K_0402_1% PU401 1 PRT401

1
MURAT_NCP15WF104F03RC
1 2 24 NCP81208MNTXG_QFN48_6X6 PC440
PR415 VSP_1A 1000P_0402_50V7-K
PLACE CLOSE TO

2
3.4K_0402_1% PC405 2
2 0.033U_0402_25V7K
PC406
VCCCPUCORE PL403
28 CSN_1A
1000P_0402_25V7-K CSN_1A CSN_1A [71]
1

PR416 PR417
910_0402_1% @ 0_0402_5%
1 2 25 23 1 2
VSN_1A TSENSE_1PH
PC407
3300P_0402_50V7-K
VSS_SENSE

1
[16] VSS_SENSE 1 2

2
PRT402
PC408 PR418 MURAT_NCP15WF104F03RC
PC409 1 2 15P_0402_50V8-J 26 0.1U_0402_25V6-K 61.9K_0402_1%
COMP_1A

2
PLACE CLOSE TO

2
PR419

1
1 2 1 2
2.49K_0402_1%
VCCCPUCORE PU402
PR420 PC410
47K_0402_1% 1500P_0402_50V7-K
C 2 1 27 C
ILIM_1A
PR421 16 PWM1_2PH
PWM1_2PH PWM1_2PH [72]
88.7K_0402_1%
1 2 30
IOUT_1A 17
PC411 1 2 270P_0402_50V7-M PWM2_2PH

PR422
PC412 1 21000P_0402_50V7-K 2.05K_0402_1%
10 1 2 CSP1 CSP1 [72]
VCCGT_SENSE 47 CSP1_2PH
[16] VCCGT_SENSE VSP_2PH 9
CSP2_2PH +5VALW
2

1
PC413 PR424 PC414
1000P_0402_25V7-K 1.05K_0402_1% 0.1U_0402_25V6-K PR423
1

2
1 2 48 10_0402_1%
VSN_2PH 8 1 2
CSREF_2PH CSN1 [72]
PC415 PR425
3300P_0402_50V7-K 27.4K_0402_1%
VSSGT_SENSE 1 2 2 1 1
[16] VSSGT_SENSE IOUT_2PH
PC416 1
470P_0402_50V8-J PC417 20150518
1 2 0.1U_0402_16V7-K
2
PR426
54.9K_0603_1%
2 7 1 2 CSP1
DIFFOUT_2PH CSSUM_2PH
3
FB_2PH

2
PC418 PC419
PR428 PR429 PC420 100P_0402_50V7-K 1000P_0402_25V7-K

1
510_0402_1% 4.75K_0402_1% 2200P_0402_25V7-K PR427 PR430
1 2 1 2 1 2 4 73.2K_0402_1% 165K_0402_1%
PR431 PC421 PC422 COMP_2PH 6 1 2 1 2
49.9_0402_1% 470P_0402_50V8-J 33P_0402_50V8-J CSCOMP_2PH PR432
1 2 1 2 1 2 12.4K_0402_1%
PC423 PR433 5 1 2
1000P_0402_25V7-K 2.74K_0402_1% ILIM_2PH PLACE CLOSE TO
1 2 1 2 PRT403 1 2 VCCGT PL406
PR434 MURAT_NCP15WM224J03RC
2.74K_0402_1%
[16] VCCSA_SENSE 1 2 45
VSP_1B PR435
B @ 0_0402_5% B
11 1 2 PRT404 1 2
TSENSE_2PH
2

2
MURAT_NCP15WF104F03RC

1
PC425 PR436
1000P_0402_25V7-K PC424 61.9K_0402_1% PLACE CLOSE TO
1

PR437 0.1U_0402_25V6-K
VCCGT PU403

2
1K_0402_1%

1
[16] VSSSA_SENSE 1 2 44
VSN_1B
PC427 36 PWM_1B
PWM_1B PWM_1B [73]
15P_0402_50V8-J PC426 1 2 3300P_0402_50V7-K
1 2 43 40 PR438 1 2 7.5K_0603_1% SW_1B
COMP_1B CSP_1B SW_1B [73]
PC428
0.01U_0402_25V6-K 1 2 PRT405 1 2
1 2 1 2 PR441 MURAT_NCP15WF104F03RC
41.2K_0402_1% 12K_0402_1%
ROSC_COREGT

1
PR440 1 2 42 PC429 PC439 PR439
ADDR_VBOOT

PLACE CLOSE TO
ICCMAX_2PH

ILIM_1B
ROSC_SAUS

0.018U_0402_50V7-J

3300P_0402_50V7-K

1.5K_0402_1%
ICCMAX_1A

ICCMAX_1B

PR442 VCCSA PL408

2

2
110K_0402_1%
1 2 39 41 CSB_1B
IOUT_1B CSN_1B CSB_1B [73]
TAB

PC430
270P_0402_50V7-M
15

21
14

18

19

20

49

1 2
102K_0402_1%
48.7K_0402_1%

15.8K_0402_1%

PC431
24K_0402_1%

24K_0402_1%

10K_0402_1%

1000P_0402_50V7-K
1 2
2

2
1

1
PR443

PR444

PR445

PR446

PR447

PR448

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 IMVP8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 70 of 82
5 4 3 2 1
 5 4 3 2 1

PL401
BLM18KG300TN1D
EMC@ EMC@ RF_NS@ 1 2
EMC@ B+
PC432 PC433 PC434 PC435 PC436 PC437 PL402
BLM18KG300TN1D

33U_D2_25VM_R40M

33U_D2_25VM_R40M

33U_D2_25VM_R40M
47P_0402_50V8-J
1

1
1 2

2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

PC438
0.1U_0402_25V6
1 1 1
EMC@ + + +

PC525

PC526

PC527
+VCC_CORE

2
2
2.2_0603_1%
2 2 2 TDC= 21A

5
PR449
2 1 @ @ @
D
IccMAX=31A D

2
PC442
0.22U_0603_25V7-K
HG_A1
OCP = 36A
PU402 4 PQ401

1
NCP81253MNTBG_DFN8_2X2 TPCA8065-H

1 8 PL403
BST DRVH 0.15UH_CMLE064T-R15MS0R725-88_35A_20%

3
2
1
2 7 SW_A1 1 4
[70] PWM_1A PWM SW
+VCC_CORE

2
3 6 2 3
[70,72,73] DRVON EN GND PR450 1
4 5

FLAG
4.7_0603_5%
+5VALW VCC DRVL + PC443
EMC_NS@ 330U_D2_2VM_R9M

1 1
1

PC444 LG_A1 4 4

9
1U_0402_10V 2
PC445
2

680P_0402_50V7K

2
3
2
1

3
2
1
PQ402 PQ403 EMC_NS@
TPCA8057-H TPCA8057-H
CSN_1A [70]

SW_1A [70]

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 71 of 82
5 4 3 2 1
 5 4 3 2 1

PL404
BLM18KG300TN1D
EMC@EMC@RF_NS@ 1 2
EMC@ B+
PC446 PC447 PC448 PC449 PC450 PC451 PL405
BLM18KG300TN1D

47P_0402_50V8-J
1

1
1 2

2200P_0402_25V7-K

PC452
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6
D D
EMC@

2
2
2.2_0603_1%

5
PR453
2 1 PQ404 +VCC_GT
TPCA8065-H
TDC= 18A

2
PC453
0.22U_0603_25V7-K
HG_B1 4 IccMAX=31A

1
PU403
NCP81151MNTBG_DFN8_2X2 OCP min = 40A
1 8 PL406
BST DRVH 0.15UH_CMLE064T-R15MS0R725-88_35A_20%

3
2
1
2 7 SW_B1 1 4
[70] PWM1_2PH PWM SW
+VCC_GT

2
3 6 2 3 1
[70,71,73] DRVON EN GND PR454 PC454
4 5 +
4.7_0603_5%
+5VALW VCC DRVL

330U_D2_2VM_R9M
FLAG
EMC_NS@

2 1
2
1

PC455 LG_B1 4 4
1U_0402_10V
9

PC456
2

680P_0402_50V7K

1
EMC_NS@

3
2
1

3
2
1
C PQ405 PQ406 C
TPCA8057-H TPCA8057-H

CSN1 [70]

CSP1 [70]

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_GT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 72 of 82
5 4 3 2 1
 5 4 3 2 1

PL407
BLM18KG300TN1D
EMC@EMC@ RF_NS@ 1 2
D
B+ D
PC457 PC458 PC459 PC460 EMC@

47P_0402_50V8-J
1

1
2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

PC461
0.1U_0402_25V6
2

2
2
2.2_0603_1%

5
PR457
2 1

+VCC_SA

2
PC462
0.22U_0603_25V7-K
PU404 HG_1PH4 PQ407 TDC= 4A

1
NCP81253MNTBG_DFN8_2X2 AON7408L
IccMAX=5A
1 8 PL408
BST DRVH 0.47UH_PCMB063T-R47MS3R675_18A_20% OCP = 9A

3
2
1
2 7 SW_1PH 1 4
[70] PWM_1B PWM SW
C +VCC_SA C

5
3 6 2 3
[70,71,72] DRVON EN GND
4 5
FLAG

+5VALW VCC DRVL

2
PR458
1

PC463 LG_1PH 4 PQ408 4.7_0603_5%

9

1U_0402_10V AON7408L
EMC_NS@
2

1 1
3
2
1
PC464
680P_0402_50V7K

2
CSB_1B [70]
EMC_NS@
SW_1B [70]

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_SA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 73 of 82
5 4 3 2 1
 A
B
C
D

+VCC_GT

1
2
1
2
1
2

5
5

PC513 PC488 PC465

+VCC_CORE

+VCC_SA
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2
PC514 PC489 PC466
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2

PC490 PC467
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC515
22U_0603_6.3V6M PC491 PC468
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC516
22U_0603_6.3V6M PC492 PC469
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC517
22U_0603_6.3V6M PC493 PC470
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC518
22U_0603_6.3V6M PC494 PC471
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
25pcs 22uF for +VCC_GT

12pcs 22uF for +VCCSA

1
2
1
2

PC519
22U_0603_6.3V6M PC495 PC472
22U_0603_6.3V6M 22U_0603_6.3V6M

4
4

1
2
PC520

1
2
1
2

22U_0603_6.3V6M
PC496 PC473

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC521
1
2
1
2

22U_0603_6.3V6M
23pcs 22uF for +VCC_CORE

PC497 PC474

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC522
22U_0603_6.3V6M
+VCC_GT

1
2

1
2
PC498
PC523 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

Issued Date
1
2
PC499
PC524 22U_0603_6.3V6M
1
2

22U_0603_6.3V6M

Security Classification
1
2

PC475
+VCC_CORE

PC500 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC476
PC501 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC477
PC502 22U_0603_6.3V6M

3
3

22U_0603_6.3V6M

2013/08/05
1
2

PC503
22U_0603_6.3V6M
1
2
1
2

PC504 PC478
+VCC_CORE
Based on PDDG rev 0.7 Table 5-1.

22U_0603_6.3V6M 22U_0603_6.3V6M
1
2
1
2

PC505 PC479
22U_0603_6.3V6M 22U_0603_6.3V6M
1
2

1
2

PC480
PC506 22U_0603_6.3V6M
22U_0603_6.3V6M
Deciphered Date
1
2

1
2

PC481
PC507 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

LC Future Center Secret Data

PC482
22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
+VCC_GT

1
2
1
2

PC508
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

22U_0603_6.3V6M PC483
22U_0603_6.3V6M
1
2

2
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2014/12/31
1
2

PC509
22U_0603_6.3V6M PC484
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22U_0603_6.3V6M
1
2
1
2

PC510
22U_0603_6.3V6M PC485
22U_0603_6.3V6M
1
2

PC511
B
1
2

22U_0603_6.3V6M
PC486
Size

Date:
1
2

22U_0603_6.3V6M
Title

PC512
1
2

22U_0603_6.3V6M
PC487
22U_0603_6.3V6M
Document Number

Thursday, August 25, 2016

PROCESSOR DECOUPLING

1
1

KENOBI
Sheet
74
of
82
Re v
2.0
A
B
C
D
 5 4 3 2 1

DIS@ PR633
10K_0402_1%
2 1
[28,33] VGA_ON
+VGA_B+ PL601 DIS_EMC@
MURATA BLM18KG300TN1D
@ PR601
D 0_0402_5%
+3VS_VGA 1 2 D

2 1
[9,33] VGA_APWR_ON DIS_EMC@ DIS_EMC@

2
1 2
PR602 @ B+
10K_0402_5% PL602 DIS_EMC@

DIS@

DIS@
2200P_0402_25V

10U_0805_25V6K
0.1U_0402_25V6

10U_0805_25V6-K
DIS@ PQ601 MURATA BLM18KG300TN1D
PR604 @ TPCA8065-H_DFN

1
10K_0402_5%

5
2 1

PC602

PC603

PC604

PC605
+ VGA_CORE

2
PD601 @
CUS357_SOD323-2

1
1 2
PR605 @ UGATE1_VGA 4 TDC= 2 6 A
100K_0402_5% DIS@ PC601
EDC =5 1 A

2
0.1U_0402_10V7-K
DIS@ PR606 PC610 DIS@ OCP = 5 8 A

2
+3VS_AON 2.2_0603_5% 0.22U_0603_25V7K

3
2
1
@ PC611 2 1 1 2
0.1U_0402_10V6-K
2 1 DIS@ PL603

2
.22UH 20% PCME064T-R22MS0R985

EN_VGA_CORE
DIS_EMC@ DIS_EMC@+VGA_CORE

BOOT1_VGA
PR607 DIS@ PHASE1_VGA 1 2
10K_0402_1% [28] VGA_PWM_VID 1 2

5
PR609 1 1

2200P_0402_25V7-K
22U_0603_6.3V6-M

22U_0603_6.3V6M

22U_0603_6.3V6M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
@ 0_0402_5% @ PR608
DIS_EMC_NS@ 2 2 2

0.1U_0402_25V6
1
PSI_VGA

1
1 2 0_0402_5% DIS@ PQ604 @ PQ603 + +

DIS@ PC612

DIS@ PC613

DIS@ PC614

DIS@ PC645

DIS@ PC646
[28] VGA_PSI
DIS@ PR612 TPCA8057-H_DFN TPCA8057-H_DFN PR610

PC649

PC650
20K_0402_1% 4.7_0603_5%

2
VREF_VGA LGATE1_VGA 1 1 1 2 2
2

1 2 4 4
@ PR611 DIS@ PR613

1
10K_0402_1% 20K_0402_1%
C
1 2 1 2 DIS_EMC_NS@ C

2
PC619

VID_VGA

PSI_VGA
VIDBUF
1

3
2
1

3
2
1
PC618 @ PR614 DIS@ 680P_0402_50V7K

1
2200P_0402_25V7-K 21K_0402_1%

1
DIS@ PR615
2K_0402_5% VGA_CORE Output Capacitor:

2
PR616 DIS@ PR617
2 x 330uF SP(9mohm) +3 x 22uF(0603)

1
@ 0_0402_5% 18K_0402_1%

2
1 2 1 2

HG1

BST1
VID

EN
PSI
VIDBUF
PC621 DIS@
4700P_0402_25V7K
PC620 DIS@ 1 2 REFIN 7 24 DIS@ PC622
0.01U_0402_25V REFIN PH1 4.7U_0603_6.3V6-K
1 2 VREF_VGA 8 PU601 23 1 2
PR619 DIS@ VREF LG1
1 2 FS 9 NCP81172MNTWG_QFN24_4X4 22 PR621 +VGA_B+
FS PGND @ 0_0402_5%
43K_0402_1% 10 DIS@ 21 PVCC_VGA 1 2 DIS_EMC@ DIS_EMC@
[25] GFXCORE_GND_SENSE_D FBRTN PVCC +5VALW

2200P_0402_25V7-K
PC624 DIS@ PR622 DIS@ FB_VGA 11 20

DIS@

DIS@
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
FB LG2
1

47P_0402_50V8-J 51_0402_1% PC625 33P_0402_50V8-J

PC623 @ 1 2FB1_VGA 1 2 1 2 COMP_VGA 12 19

TALERT#
COMP PH2

1
PGOOD
1000P_0402_50V7-K DIS@
2

TSNS
DIS@ PQ605

BST2

PC627

PC628

PC629

PC630
GND

VCC

HG2
[25] GFXCORE_VDD_SENSE_D 2 1 1 2FB2_VGA
1 2 TPCA8065-H_DFN

2
DIS@ DIS@

5
DIS@ PR624 DIS@ PC626 DIS@ PR625 PR627 PC635

25

13

14

15

16

17

18
10K_0402_1% 100P_0402_50V8-J 82K_0402_1% 2.2_0603_5% 0.22U_0603_25V7K
BOOT2_VGA 2 1 1 2

T ALERT_VGA
TSNS_VGA

PG_VGA
VCC_VGA
UGATE2_VGA 4
DIS@ PR628
5.9K_0402_1% PR629
B
VREF_VGA 2 1 @ 0_0402_5% B
1 2
DGFX_PWRGD [25,28]
100K_0402_1%_TSM0B104F4251RZ

3
2
1
0.1U_0402_10V6-K
2

1 2 PL606 DIS@
@ PRT601

@ PC636

+5VALW .22UH 20% PCME064T-R22MS0R985

DIS@ PR630 PHASE2_VGA 1 2
+VGA_CORE
2

2_0603_5%
1

5
1 1

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
DIS@ PC640
DIS_EMC_NS@ 2 2 2

2
1U_0402_10VA-K DIS@ PQ610 @ PQ609 + +

DIS@ PC637

DIS@ PC638

DIS@ PC639

DIS@ PC648

DIS@ PC661
2

TPCA8057-H_DFN TPCA8057-H_DFN PR631

4.7_0603_5%
LGATE2_VGA 4 4 1 1 1 2 2

1
DIS_EMC_NS@

2
DIS@ PR632 PC644

3
2
1

3
2
1
10K_0402_1% 680P_0402_50V7K
2 1
+3VALW

1
VGA_CORE Output Capacitor:
2 x 330uF SP(9mohm) +3 x 22uF(0603)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 VGA_CORE(NCP81174)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 75 of 82
5 4 3 2 1
 5 4 3 2 1

D D

@ PJ702
JUMP_43X118
PR701
@ 0_0402_5% 2 1
1 2 2 1
[57,77] EC_ON2

0.1U_0402_6.3V7-K
1

2
PC701 2 1
+1VSP 2 1 +1VALW

2
0.1U_0402_16V7-K PR702

PC702
210K_0402_1% +3VS

2
@ PJ703

1
JUMP_43X118

2
@ PR704

2
PR703 100K_0402_1%

24

25

26

27

28

29
210K_0402_1%
C C

1
+1VALW

REFIN2

REFIN

EN

GND2
VREF

RA
1
+5VALW 23 1 VDDPALW_PWRGD FSW=800KHz
GSNS PGOOD
22 2 @ PR705
TDC:10A
VSNS LP#
@ PR706
PC703
2 1 21 3
0_0402_5%
1 2
OCP:16A
0_0402_5% SLEW MODE
1 2 0.01U_0402_25V7-K20 4 @ PR707 PC704
TRIP NC 0_0603_5% 0.1U_0603_25V7K
PC705 19 PU701 5 BST_1V 1 2 1 2 PL701
@ PJ701 2.2U_0603_10V6-K GND1 BST 1UH_PCMC063T-1R0MN_+-20%
JUMP_43X79 1 2 18 TPS51367RVER SW1 6 SW_1V 1 2 EMC@ EMC@
V5 +1VSP
2 1 RF_NS@ EMC@ EMC@ VIN_1V 17 7
B+ 2 1 VIN3 SW2

2
2200P_0402_25V7-K
68P_0402_50V8J

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6

16 8 PR708

2200P_0402_25V7-K
VIN2 SW3
1

1@ 4.7_0603_5%
PC706

PC707

PC708

PC709

PC710

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
PC714 15 9
VIN1 SW4 EMC_NS@

1
47P_0402_50V8-J

PC716

PC717
1 1 1 1

PGND5

PGND4

PGND3

PGND2

PGND1
2

PC711

PC712

PC713

PC715
2

2
2 2 2 2
B B

14

13

12

11

10

1
PC718
680P_0402_50V7K
EMC_NS@

2
Mode Frequency

GND 400KHz

Float 800KHz

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/01 Deciphered Date 2014/08/01 +1VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 76 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+1.8VALW
TDC: 1A
Fsw: 1MHz

@ PJ802
PL801 JUMP_43X39

4
PJ801 1UH_PH041H-1R0MS_20%
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2 +1.8VSP 2 1
+5VALW +1.8VALW

PG
2 1 PVIN2 LX1 2 1

2
9 2
@ JUMP_43X39 PVIN1 LX2

1
PR803

1
PC801 PC802 8 3 4.7_0603_5%
C
10U_0603_10V 10U_0603_10V SVIN1 LX3 EMC_NS@ PR804 PC805
C

EMC@ EMC@
2

2
PU801 20K_0402_1% 22P_0402_50V

2 1

2200P_0402_25V7-K
22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
RT8068AZQW

1
5 6 PC804
20141226

PC842
GND
PR801 EN FB

PC806

PC807

PC808
NC
[57,76] EC_ON2 @ 0_0402_5% EMC_NS@ 680P_0402_50V

2
1 2EN_1.8VSP

11

7
2
1 2

1
@ PR802 @ PC803
@ PD801 1M_0402_5% 0.22U_0402_10V6-K

2
CUS357_SOD323-2 PR805

1
10K_0402_1%
B B

2
A Security Classification LC Future Center Secret Data Title A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.8VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 77 of 82
5 4 3 2 1
 5 4 3 2 1

D D

+2.5V
TDC: 2A
Fsw: 1MHz

@ PJ804
@ PJ803 PL802 JUMP_43X39

4
JUMP_43X39 1UH_PH041H-1R0MS_20%
2 1 VIN_+2.5VSP 10 1 2.5VSP_LX 1 2 +2.5VSP 2 1
+5VALW +2.5V

PG
2 1 PVIN2 LX1 2 1

2
9 2
PVIN1 LX2

1
PR808

1
PC809 PC810 8 3 4.7_0603_5%
C
SVIN1 LX3 EMC_NS@ C

1
10U_0603_10V 10U_0603_10V
EMC@ EMC@

2
PU802 PR809 PC813

2 1
31.6K_0402_1% 22P_0402_50V

2200P_0402_25V7-K
22U_0805_6.3VAM

22U_0805_6.3VAM

0.1U_0402_25V6
RT8068AZQW

1
5 6 PC812
20141226

GND
EN FB

2
PR806

PC814

PC815

PC816

PC843
NC
@ 0_0402_5% EMC_NS@ 680P_0402_50V

2
1 2 EN_2.5VSP
[50,57,69] SYSON

11

7
2

1
@ PR807 @ PC811
1M_0402_5% 0.22U_0402_10V6-K

2
PR810

1
10K_0402_1%
B B

2
A Security Classification LC Future Center Secret Data Title A

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +2.5V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 78 of 82
5 4 3 2 1
 5 4 3 2 1

@ PD802
CUS357_SOD323-2

1 2

D DIS@ PR811 D
100K_0402_1%
1 2
[28] FB_PWR_EN

1
DIS@ DIS@
PR812 PC817
200K_0402_1% 0.1U_0402_16V

2
2
+1.5VS_VGA
TDC: 6.8A
OCP: 12A
Fsw: 650KHz
PJ805
B+ DIS_EMC@ DIS_EMC@ DIS@
2 1 DIS@ 8 1 @ PR813 PC822
2 1 IN EN 0_0603_5% 0.1U_0603_25V7K DIS@ PL803
@ JUMP_43X79 6 BS_1.5VSP 1 2 1 2 1UH_PCMC063T-1R0MN_+-20% @ PJ806

2200P_0402_25V7-K
10U_0805_25V

0.1U_0402_25V
BS
1

1
JUMP_43X118
C
9 10 SW_1.5VSP 1 2 +1.5VSP DIS_EMC@ DIS_EMC@ 2 1
C
PC818

PC819

PC844
GND LX 2 1 +1.5VS_VGA
2

2
PU803 FB 4 FB_1.5VSP
3 +3VALW
ILMT

2
7
+3VS BYP DIS_EMC_NS@
@ PR814 SYX198DQNC DIS@ DIS@ DIS@ DIS@
0_0402_5% 2 DIS@ PR820

2200P_0402_25V
22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
PG 1 1 1 1

1
1 2 5 4.7_0603_5% DIS@

PC829

PC830
LDO

1
1

2
PC824

PC825

PC826

PC827

PC828
4.7U_0402_6.3V6-M
330P_0402_50V

2
2 2 2 2

1
1 2

PC821
4.7U_0402_6.3V6-M

1
DIS@
DIS_EMC_NS@

2
@ PR815 PC823

PC820

2
2

2
100K_0402_1% 680P_0402_50V
@ PR816 DIS@

1
0_0402_5% PR817

1
DIS@ 1K_0402_1%
PR827 PR818
1

1
@ 0_0402_5% 30.9K_0402_1%
[25] VDDQPWRGD 1 2 DIS@

2
B B

2
DIS@
PR819
20K_0402_1%

1
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.5VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 79 of 82
5 4 3 2 1
 5 4 3 2 1

D D

B+ +5VLP/ 100mA
DCIN Adapter SILERGY Richtek
SYX198CQNC +5VALW/8A RT8068A 1.8VALW/1A
PWM FOR 1.8VALW
FOR SYSTEM EC_ON2 EN
EC_ON EN PGOOD +5V_PWRGD

SILERGY +3VLP/ 100mA Richtek

TI SYX198BQNC RT8068A 2.5V/1A
Power Dual BQ25700 PWM FOR 2.5V
Switch Circuit +3VALW/8A SYSON EN
Battery Charger FOR SYSTEM
EC_ON EN PGOOD +3V_PWRGD
Buck-Boost

Richtek Richtek
RT8068A 1.05VS_VGA/2.6A
RT8231A +1.2V/ 6A
C
1.05VS_VGA for 15" only C

FOR DDR4 VGA_ON EN

SMBus SYSON S5 +0.6V/1.5A
SM_PG_CTRL S3
TYPE-C

NCP81253 VCORE/TDC 21A/EDC 28A

ON

Batt. MOSFET NCP81208 NCP81151 VCCGT/TDC 18A/EDC 31A

VR_ON EN
For SKL CPU
NCP81253 VCCSA/TDC 4A/EDC 5A

ON
B NCP81172 +VGA_CORE TDC 26A /EDC 51A
B

VGA_PWM_VID VIDs
VGA_ON EN For N16 GPU
Battery

TI V1.00A/10A
TPS51367
FOR V1.00A
EC_ON2 EN PGOOD

SILERGY FOR VRAM /7A

SYX198D
VRAM DDR3 1.5V for 14"
FB_PWR_EN EN VRAM GDDR5 1.35V for 15"
PGOOD

A A

Security Classification LC Future Center Secret Data Title

Issued Date Deciphered Date Power Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 80 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 81 of 82
5 4 3 2 1
 5 4 3 2 1

D D

C C

BLANK

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/09/01 Deciphered Date 2016/12/31 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KENOBI
Date: Thursday, August 25, 2016 Sheet 82 of 82
5 4 3 2 1