DELAY IN

VHDL
SIGNAL ASSIGNMENTS:

  Example of signal assignment

  z <= x and y; 

In other words, a signal z takes the value of the logical AND of two
signals x and y. In its simplest form a signal assignment passes the value of one
signal directly to another:

z <= x;

This can be enhanced to provide more complex logical operations:

  z <= not ((x and y) or (a and b));

 Thus it is possible to describe a wide variety of gates and other combinational

logic, simply using signal assignments.

INERTIAL DELAY MODEL:

In reality, of course, the output of a piece of real hardware does not
change instantaneously when an input changes. Inevitably, there is a delay.

Inertial delay is the default delay model. An input value must be stable
for a specified pulse rejection limit duration before output responds. If the
input is not stable for specified limit, no output change occurs.

It is suitable for modelling delays of switching circuits.

This delay model is often used to filter out unwanted spikes and
transients on signals.

Syntax:
signal <= reject time-expression inertial value-expression after time_expression ;

(A pulse whose duration is shorter than the time limit specified in the reject
clause will not be transmitted)
 Figure shows a simple example of a non inverting buffer with an inertial
delay of 10 ns and pulse rejection limit of 4ns.

Z <= reject 4ns inertial A after 10ns;

Events on signal A that occur at 5 ns and 8 ns are not stable for the
inertial delay duration and hence do not propagate to the output. Event on A
at 10ns remains stable for more than the pulse rejection time, and therefore,
the value is propagated to the target signal Z after the inertial delay; Z gets the
value 1' at 20 ns. Events on signal A at 25ns and 28 ns do not affect the output
since they are not stable for the pulse rejection limit duration. Transition 1' to
'0' at time 30 ns on signal A remains stable for at least the for the duration of
pulse rejection limit, and therefore, a '0' is propagated to signal Z with a delay
of 10 ns; Z gets the new value at 40 ns. Other events on A do not affect the
target signal Z.

If the assignment has no reject time specified, then the pulse rejection
limit is same as inertial delay value. e.g.

Out_ <= inertial Inpu after 8 ns;

1 t

Out_ <= inertial Inpu after 2 ns;

2 t
For out_1 pulse, rejection limit is also 8ns; similarly for out_2, it is 2ns.
 Since it is the default delay model, no keyword needs to be explicitly
specified. e.g.

z <= x after 4 ns; 

This is an inertial delay. In other words, the signal is delayed by 4 ns, and in
addition, any pulse that is less than 4 ns wide is suppressed, as shown in Figure
below.

NOTE:

TRANSPORT DELAY:
Transport delay models delays through elements with no inertial delay,
e.g., wires.
This delay represents pure propagation delay; that is any changes on the
input are transported to the output.
To use transport delay model, the keyword transport must be used in a
signal assignment statement. E.g.
 Z <= transport A after 10 ns;

In this case, spikes would be propagated through instead of being

ignored, as in the inertial delay case.

TRANSPORT DEALY VS INERTIAL DELAY:

TRANSPORT DELAY INERTIAL DELAY

ARCHITECTURE beh OF delay_line ARCHITECTURE beh OF buf

BEGIN BEGIN
b <= TRANSPORT a AFTER 20 ns; b <= a AFTER 20 ns;
END beh; END beh;