Power

Electronic Module
by Krishna Shenai

T
o enable the rapidly emerging and imminent energy economy, high-volt-
age (HV) and high-current robust power electronic modules (PEMs) are
needed at low cost. PEMs typically consist of a number of semiconductor
power switches and driver chips; intelligent power modules often contain
sensing and protection circuitry. In the entire supply chain of power elec-
Enabling the tronics systems—from materials to end-user applications, including the original
equipment manufacturers (OEMs)—the PEM is the key building block, as it forms the
21st-century heart of a power electronic system. The performance, cost, and durability of the entire
power electronic system critically hinge on those of the PEM. In addition, major busi-
energy ness opportunities in power electronics are often enabled by the advances in power
economy semiconductor devices. One such opportunity currently available to the power elec-
tronics community has been created by the advances in wide-bandgap (WBG) power
switching devices, which were first introduced by Shenai et al. in the 1980s [1].
One of the key challenges in the development of high-power PEMs has always been
to obtain a sufficiently large safe operating area (SOA) as required by many power
electronic systems, especially when operating under hard-switching conditions. The
demand from high-reliability OEM applications, such as the computer power supplies
in high-end servers, telecom power supplies, and traction inverters, may place strin-
gent lifetime requirements on the PEM, based on the considerations that originate

Digital Object Identifier 10.1109/MPEL.2014.2330459

Date of publication: 5 September 2014

background image: ©istockphoto.com/Hong Li

Image courtesy of
Dr. Kevork Haddad, Semikron America.

2329-9207/14©2014IEEE September 2014 z IEEE Power Electronics Magazine 27

from the mean time between failure (MTBF) of the power
converter under extreme field operating conditions. How-
ever, current power converter design approaches only con-
sider in an ad hoc manner the maximum junction tempera-
ture (T j max) of the power semiconductor switch within the
PEM in assessing the MTBF of the power converter in the
OEM application. This conventional design approach needs
to be revisited, especially since most power semiconduc-
tor failures occur during transient switching conditions,
and the semiconductor chip is unlikely to be in the isother-
mal condition [2]. This feature requires serious consider-
ation, as PEMs based on WBG power switching devices are
expected to operate at much higher T jmax than their silicon
counterparts.
This article provides a status report on advanced silicon
and WBG PEMs and discusses the key challenges that must
be addressed when developing future compact power elec-
tronics systems targeted for deployment in the emerging
energy economy. For silicon, the focus is on HV and high-
power insulated-gate bipolar transistor (IGBT) power mod-
ules, as they represent the most advanced PEM technology
in the market today. For WBG technology, the discussion
is limited to converter-level package optimization of low-
voltage point-of-load (POL) power converters that employ
gallium nitride (GaN) power transistors.

High-Power Modules
•N-Enhancement Layer •Short Channel
Emitter In the past ten years or so, dramatic improvements in HV
and high-power silicon IGBT module technology have been
•P •P achieved in terms of energy efficiency, cost, and reliability.
Figure 1(a) shows the typical planar IGBT cell design
•Low Gate-Collector employed, where improved on-state conduction and low
Capacitance Miller capacitance are obtained by increasing the minority
carrier injection efficiency and decreasing the gate-collector
•N-Base
overlap capacitance [3]. The planar soft punch-through
•SPT Buffer (SPT) design approach provides for increased carrier con-
•P+ centration at the collector and reduces both conduction and
•Collector turn-off losses. The planar cell design facilitates an easy inte-
(a)
gration of low Miller capacitance, good turn-on controllabil-
ity, and fast voltage decay at turn-on, without adversely
affecting other important device parameters. As shown in
Figure 1(b), 6.5-kV IGBT power modules rated at 750 A are
commercially available in industry-standard housing with a
190 # 140 -mm footprint. These power modules are opti-
mized for high-reliability traction applications and consist of
aluminum silicon carbide base plates and aluminum nitride
substrates with excellent thermal capability and high turn-off
ruggedness and can sustain an isolation voltage of
6,500-V SPT + HiPak Modules 10.2 kVrms . Figure 1(c) shows a systematic reduction in
Rated at 750 A
power loss achieved using the SPT-IGBT technology.
(b) A more recent development in HV-HiPak technology per-
tains to the development of a reverse conducting IGBT (RC-
6.0
IGBT) concept integrated with a free-wheeling diode, as shown
4,500 V

5.5 SPT
in Figure 2(a) [4]. The bimode insulated gate transistor (BIGT)
3,300 V

5 0.
6,500 V

provides a potential solution for future high-voltage applica-

4.5
2,500 V
Vce,on (V)

tions that demand compact systems with increased power lev-

40
1,700 V

els. The new device can operate in both free-wheeling diode

3.5
1,200 V

and IGBT modes by utilizing the same available silicon vol-

3.0 SPT+
ume. Therefore, the BIGT is targeted to fully replace the state-
2.5
of-the-art two-chip IGBT/diode approach with a single BIGT
2.0
chip [Figure 2(b)]. This is achieved while also improving the
1.5
0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 overall performance, especially under hard-switching  condi-
Voltage Class (V) tions with low losses, soft-switching characteristics, and high
(c) SOA, as shown in Figure 2(c).
Further  improvement in IGBT power module performance
fig 1 (a) The cell design, (b) a 6.5-kV/750-A HV-HiPak power
module, and (c) the loss reduction achieved with SPT-IGBT and
can be achieved using a silicon carbide (SiC) Schottky barrier
diode technology. [Image (b) courtesy of Dr. Arnost Kopra, ABB diode (SBD) as the free-wheeling diode. One such commer-
Switzerland.] cial rendering of this hybrid technology is shown in Figure 3;

28 IEEE Power Electronics Magazine z September 2014

it consists of 1.2-kV silicon
IGBTs and 1.2-kV SiC SBD
MOS Cell
chips [5]. Because of a very Emitter
low stored charge in an SiC
SBD compared with a silicon Gate p
n+ n-
bipolar power diode, reduced MOS Cell
switching energy with an SiC
SBD may enable a higher con- IGBT RC-IGBT
verter switching frequency.
Buffer Buffer
All-SiC power modules capa-
ble of switching > 50 kW with
improved energy efficiency are Anode Anode Segment n+ Short
also available using 1.2-kV SiC
power metal–oxide–semicon-
ductor field-effect transistor Lifetime Control Layer
BIGT RC-IGBT
Pilot-IGBT Buffer
(MOSFET) and SiC SBDs.

Low-Power Modules
Pilot-Anode Anode Segment n+ Short
Nonisolated POL power con-
(a)
verters are used in computers,
telecommunication systems,
handheld electronics, automo-
biles, and a host of other appli-
cations. With the ever-increas- Standard
IGBT/Diode BIGT
ing demand for lower-power- Substrate Substrate
consumption electronics, the
chip supply voltage has 600-A Module
steadily gone down from 5 V
to well below 2.5 V, and it is
projected to approach 1 V in 4# IGBTs 6# BIGTs
the very near future [6]. At the 2# Diodes
same time, the chip size has 125-A Substrate 150-A Substrate
increased, and, consequently,
these larger chips demand
higher power at lower volt-
ages. The majority of POLs are 900-A Module
nonisolated step-down buck (b)
converters, often having a
large step-down ratio from as 10 100
high as 28-V input to 1.2-V out- IGBT–BIGT IGBT/Diode
Leakage Current (mA)

Leakage Current (mA)

Comparison on 10 BIGT
put. The most straightforward
Chip
way to improve power density 1
1 Full Module
in a traditional buck converter
is to increase switching fre-
0.1 IGBT/Diode
quency, enabling a volumetric 0.1 IGBT
reduction in the output induc- IGBT 2x Anode
0.01 BIGT
tor and capacitor. However, an BIGT
BIGT 2x Anode
increase in the converter 0.01 0.001
switching frequency also 75 100 125 150 175
0

0
0

0
00

00

00

00
00
00

00

results in higher switching Temperature (°C)

2,

6,

7,
1,

4,

5,
3,

losses; thus limiting current Bias (V)

silicon-based solutions to the
range of a couple of hundred
kilohertz to 1 MHz.
GaN power transistors
have emerged as a possible
(c)
fig 2 (a) The device cross section, (b) the module construction, and (c) a performance comparison
of a 6.5-kV standard IGBT/diode combination and integrated BIGT device in an HV-HiPak1 power
module. The leakage currents measured are for 600-A power modules at 125 °C. (Images courtesy
of Dr. Arnost Kopra, ABB Switzerland.)

September 2014 z IEEE Power Electronics Magazine 29


fig 3 Hybrid 1.2-kV/300-A silicon IGBT/SiC SBD and all-SiC MOS-
FET/SiC SBD power modules using the SKiM packaging technology.
(Image courtesy of Dr. Kevork Haddad, Semikron America.)
160
140
FOM = (QGD + QGS2)*RDSON(pC*X)
replacement for silicon devices in low-voltage POL converter
applications because of their superior on-state and switching
performances. The state-of-the-art enhancement-mode GaN
(eGaN) power transistors have lateral structures with break-
down voltage ratings in the range of 40–200 V [7]. A compari-
son of switching figures of merit (FOM) for 100-V devices is
shown in Figure 4(a); the eGaN field effect transistors (FETs)
offer nearly a 66% smaller FOM compared to silicon power
transistors with similar ratings. The superior characteristics
enable not only many new applications but also create more
stringent requirements for packaging and thermal manage-
ment. Figure 4(b) shows the packaging evolution, which
clearly suggests that at operating voltages below about
200  V leadless, dual-side-
cooled packaging, such
as DirectFET, PolarPAK,
and land grid array (LGA)
become elegant solutions,

especially for POLs with

120 QGS2
multimegahertz switching
frequencies [8].
100
The challenge is not
QGS2 just limited to the packag-
80
ing of discrete chips alone;
60 the common-source and
QGS2 QGD
high-frequency power
QGS2 Q
40 GD loop inductances need to
QGD
be minimized at the con-
QGS2 QGD
20 verter level. Thus, the PCB
QGD layout becomes important
0 to increase the overall
100-V 80-V 80-V 80-V 80-V
eGaN@FET MOSFET 1 MOSFET 2 MOSFET 3 MOSFET 4
power conversion efficien-
cy of the POL converter
(a)
and to improve the ther-
mal management [9]. Since
Drain
the chip current ratings of
Gate commercial eGaN FETs
are typically limited to be-
Source low 50 A or so, paralleling
of devices to increase the
SO-8 LFPAK DirectFET LGA current ratings presents
Device Loss Breakdown 90 additional challenges. Ex-
SO-8 perience has shown that
2.5 Package VIN = 12 V 85 LFPAK
DirectFET a single high-frequency
Die VOUT = 1.2 V
Efficiency (%)

2 LGA loop with paralleled eGaN

Power Loss (W)

IOUT = 20 A 80
1.5 82% FS = 1 MHz FETs results in significant
75 efficiency loss and severe
1 73% chip heating (Figure 5).
70
47% 18% A solution to this prob-
0.5
18% 27% 53% 82% 65 lem is to create separate,
0 0.5 1 1.5 2 2.5 3 3.5
identical parasitic loops
SO-8 LFPAK DirectFET LGA Switching Frequency (MHz)
with single-chip devices
(b)
and then tie the outputs
fig 4 (a) The FOM comparison for 80-V devices (VDS = 40 V, I DS = 15 A). (b) The packaging evolution
with an external bus con-
showing a reduction in package parasitic elements [8]. (Images courtesy of Dr. Alexander Lidow, Efficient nection [10]. As shown in
Power Conversion Corp., United States.) Figure 5(a) and (b), this

30 IEEE Power Electronics Magazine z September 2014

design approach leads to improved efficiency and better ther- challenge in the construction of robust power modules tar-
mal management. geted for compact high-power converters. Figure 6 shows
the packaging layers and corresponding thermal equiva-
New Packaging Considerations lent circuit of a power module with single-sided cooling.
Whereas silicon IGBT power modules are dominating the Heat is mostly generated within a few micrometer at the
high-voltage and high-power markets, GaN power transis- top surface of the active device region, where the electric
tors are slowly penetrating the low-voltage and low-power field is high and is governed by the Poynting vector that
applications. In either case, package parasitic reduction represents the directional energy flux density (the rate of
and chip-level thermal management appear to be the key energy transfer per unit area, in units of W/cm2) of an elec-
technology challenges hindering further advancement. As tromagnetic field [13]. In the Abraham form, the Poynting
the converter switching frequency is increased for its min- vector vS is denoted as
iaturization, besides thermal gradients arising from in-
creased power losses, electromagnetic interference will
become an important issue to tackle. An accurate mea- vS = Ev x H
v ,(1)
surement of chip-to-chip
interconnect parasitic el-
ements as well as ad- 97
vanced electromagnetic
and thermal simulation 96.5
tools need to be devel-
Efficiency (%)

4 II eGaN FETs
oped that correlate chip 96
design and processing
parameters to power
95.5
module performance Conventional
and reliability. Single-Loop Design
95
The data sheets for Proposed
state-of-the-art commer- Four-Loop Design
cial WBG power devices 94.5
2 6 10 14 18 22 26 30 34 38 42
contain incomplete, in-
Output Current (A)
consistent, and errone-
ous information on key (a)
device parameters [11].
In addition, the spread T1 T3
in key device param-
SR1 SR3
eters from chip to chip
is too large. Almost al- SR2 SR4
ways, individual chips T1-4 SR1-4
should be characterized T2 T4
in detail before they are
inserted into the power FLIR 1 101 FLIR 1 89.0
module. The higher chip 120 120
cost and large chip-to-
chip variations lead to
the increased module
cost. The bidirectional
conduction capability of
lateral GaN power tran- 50 50
sistors may be an attrac-
°C °C
tive feature from a cost Trefl = 20 Tatm = 20 Dst = 0.1 FOV 37 z = 2.0 Trefl = 20 Tatm = 20 Dst = 0.1 FOV 37
reduction point of view, 9/19/13 3:51:20 PM -40- +120 e = 0.96 9/19/13 8:11:54 PM -40- +120 e = 0.96
as it may lead to the com-
(b)
plete elimination of free-
wheeling diodes [12].
fig 5 (a) The efficiency and (b) thermal images of 48-V/12-V POL converters with one and four sepa-
T he r m a l  m a n a ge - rate loops switching at 300 kHz and delivering I = 30 A. Both devices in the synchronous buck con-
OUT
ment is ex pected to verter use 100-V/25-A eGaN FETs. (Images courtesy of Dr. Alexander Lidow, Efficient Power Conversion
present a formidable Corp., United States.)

September 2014 z IEEE Power Electronics Magazine 31


PTH
TJ
Z(th)SUB
Solder Active  Region
Substrate TSUB
Z(th)SUB-C
Case
TC
  Grease Z(th)CS
Thermal
TS
Heat Sink Z(th)SA
TA
Ambient
fig 6 The typical packaging layers and thermal equivalent of
a single-sided cooled power module.
where E v is the electric field, and H
v is the magnetic field.
As per the energy conservation law, the Poynting’s theorem
leads to
du
= - d.v
S-v v ,(2)
Jf.E
dt
where v
Jf is the current density of free charges, and u is the
electromagnetic energy density. From (2), it is clear that
local current density and electric field determine the amount
of heat generated, and, hence, provide the limiting factors in
the formation of a local “hot spot” that eventually leads to
thermal runaway. This observation is important because the
heat generated is highly localized and is not uniform within
the semiconductor. It has been shown recently that the semi-
conductor substrate plays an important role in determining
the maximum junction temperature T jmax . The choice of
semiconductor substrate and its properties (such as the
thickness and electrical and thermal conductivities) will play
a critical role in the reliability of the power semiconductor
chips within the power module [14]. This feature is critical in
the construction of future power modules based on WBG
power switching devices.
Summary and Conclusions
This article has discussed some critical issues related to the
design and optimization of a power semiconductor switch
module for emerging power electronics applications, espe-
cially when employing new WBG power switching devices.
The package parasitic elements and thermal management
constraints may dictate the overall system cost, perfor-
mance, and reliability. The PEM is thus expected to drive
the growth of power electronics as it forms the key compo-
nent of a power system.
Acknowledgments
I am indebted to several industrial colleagues with whom I
have had very fruitful collaborations for many years. In partic-
ular, I would like to thank A. Kopta, M. Rahimo, and L. Sto-
rasta from ABB Switzerland Ltd. Semiconductors; G. Geney,
32 IEEE Power Electronics Magazine z September 2014
K. Haddad, and T. O’Reilly from Semikron, Inc.; and A. Lidow,
D. Reusch, J. Strydom, and M. de Rooij from Efficient Power
Conversion Corporation for providing the latest experimental
and simulation data. I am also indebted to Wayne Johnson
from Tennessee Tech University for useful discussions.
About the Author
Krishna Shenai (kshenai@anl.gov) is a principal electrical
engineer within the Energy Systems Division at Argonne
National Laboratory in Illinois. He is a fellow of the American
Physical Society, the American Association for the Advance-
ment of Science, and the Institution of Electronics and Tele-
communication Engineers-India and a member of the Serbian
Academy of Engineering. He is a Fellow of the IEEE.
References
[1] K. Shenai, R. S. Scott, and B. J. Baliga, “Optimum semiconductors for
high-power electronics,” IEEE Trans. Electron Devices, vol. 36, no. 9, pp.
1811–1823, Sept. 1989.
[2] M. Trivedi and K. Shenai, “Failure mechanisms of IGBTs under short cir-
cuit and clamped inductive switching stress,” IEEE Trans. Power Electron.,
vol. 14, no. 1, pp. 108–116, Jan. 1999.
[3] A. Kopta, M. Rahimo, S. Eicher, and U. Schlapback, “A landmark in elec-
trical performance of IGBT modules utilizing next generation chip technolo-
gies,” in Proc. 18th Int. Symp. Power Semiconductor Devices ICs, Naples,
Italy, June 4–8, 2006, pp. 1–4.
[4] A. Kopta, M. Rahimo, and R. Schnell, “Next generation high performance
BIGT HiPak modules,” Power Electron. Eur., no. 5, pp. 22–25, 2010.
[5] A. Wintrich, “Power modules for electric and hybrid vehicles,” Bodo’s Power
Syst., pp. 24–26, Feb. 2009.
[6] K. Shenai, “Potential impact of emerging semiconductor technologies on
advanced power electronic systems,” IEEE Electron Device Lett., vol. 11,
no. 11, pp. 520–522, Nov. 1990.
[7] A. Lidow, J. Strydom, M. de Rooij, and Y. Ma, GaN Transistors for Effi-
cient Power Conversion, 1st ed. El Segundo, CA: Efficient Power Conver-
sion Corp., 2012.
[8] J. Strydom, M. de Rooij, and A. Lidow, “Gallium nitride transistor packag-
ing advances and thermal modeling,” EDN China, Tech. Rep., Sept. 2012.
[9] D. Reusch and J. Strydom, “Understanding the effect of PCB layout on
circuit performance in a high frequency gallium nitride based point of load
converter,” in Proc. IEEE Applied Power Electronics Conf., 2013, pp. 649–655.
[10] A. Lidow and M. de Rooij, “Paralleling eGaN FETs,” White Paper WP005,
Efficient Power Conversion Corp., El Segundo, CA, 2012.
[11] K. Shenai, “A critique of wide bandgap semiconductor device datasheets,”
ECS Trans. GaN SiC Power Technologies 4, to be published, Oct. 2014.
[12] T. Morita, S. Tamura, Y. Anda, M. Ishida, Y. Uemoto, T. Ueda, T. Tanaka,
and D. Ueda, “99.3% efficiency of three-phase inverter for motor drive using
GaN-based gate injection transistors,” in IEEE Applied Power Electronics
Conf. Dig., 2011, pp. 481–484.
[13] J. H. Poynting, “On the transfer of energy in the electromagnetic field,”
Philos. Trans. Royal Soc. London, vol. 175, pp. 343–361, Jan. 1884.
[14] K. Shenai, “Modeling the impact of substrate material on junction tem-
perature limitations in semiconductor power switching devices,” in Proc.
GOMACTech Conf., Charleston, SC, Apr. 1–4, 2014, pp. 497–500.