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Diode-Transistor Logic (DTL) : University of Connecticut 56
Diode-Transistor Logic (DTL) : University of Connecticut 56
University of Connecticut 56
Diode Logic
VA VOUT AND VCC
VB GATE
VA VOUT
OR
GATE VB
University of Connecticut 57
Level-Shifted Diode Logic
VCC=5V With either input at 0V, Vx=0.7V,
AND DL is just cut off, and VOUT=0V.
GATE RH With both inputs at 1V, VX=1.7V and
VA VOUT VOUT=1V.
x
DL RL
VB
With VA=VB=5V, both input diodes
are cut off. Then
VCC − 0.7V
VOUT = RL
RH + RL
n Level shifting eliminates the voltage degradation from the input to the
ouput. However,
n the logic swing falls short of rail-to-rail, and
n the inverting function still is not available without using a transistor!
University of Connecticut 58
Diode-Transistor Logic (DTL)
VCC
VA RC
VB VOUT Primitive Precursor
to DTL
VC Q1
n If any input goes high, the transistor saturates and VOUT goes low.
n If all inputs are low, the transistor cuts off and VOUT goes high.
n This is a NOR gate.
n “Current Hogging” is a problem because the bipolar transistors can
not be matched precisely.
University of Connecticut 59
Diode-Transistor Logic (DTL)
VCC
RB RC
VOUT Improved gate with
VA
reversed diodes.
VB Q1
VC
n If all inputs are high, the transistor saturates and VOUT goes low.
n If any input goes low, the base current is diverted out through the
input diode. The transistor cuts off and VOUT goes high.
n This is a NAND gate.
n The gate works marginally because VD = VBEA = 0.7V.
University of Connecticut 60
Diode-Transistor Logic (DTL)
VCC
RB RC Basic DTL
VA x VOUT NAND gate.
VB Q1
VC RD
University of Connecticut 62
DTL Power Dissipation
RB=3.4kΩ VCC
RC=4.8kΩ PL =
RD=1.6kΩ
RB RC
VA x VOUT
VB Q1
VC RD
PH =
University of Connecticut 63
DTL Fanout
RB=3.4kΩ
RC=4.8kΩ VCC I CS =
RD=1.6kΩ
βF=50 RB RC
VA x VOUT
VB Q1
VC RD
I BS =
I CS =
n Good fanout requires high
β F, large RD /RB.
N max =
University of Connecticut 64
930 Series DTL (ca 1964 A.D.)
βF=50 VCC n One of the series diodes is
replaced by Q1, providing
1.75kΩ 6kΩ more base drive for Q2 and
improving the fanout (Nmax
2kΩ = 45).
VA Q1 n Does Q1 saturate?
VOUT
VB
Q2
VC 930 DTL Characteristics
5kΩ
VOH / VOL 5.0V / 0.2V
VIH / VIL 1.5V / 1.4V
Fanout 45
Dissipation 10mW
tP 75ns
University of Connecticut 65
930 DTL Propagation Delays
βF =50
CL=5pF VCC n tPLH >> tPHL
2kΩ ts =
VA Q1
VOUT
VB
Q2
VC
5kΩ
tr ≈
University of Connecticut 66
Transistor-Transistor
Logic (TTL)
University of Connecticut 67
Why TTL?
n The DTL input uses a
VA
number of diodes which take
VB DTL up considerable chip area.
VC
n In TTL, a single multi-emitter
BJT replaces the input
diodes, resulting in a more
VA
area-efficient design.
VB TTL
VC n DTL was ousted by faster
TTL gates by 1974.
University of Connecticut 68
Basic TTL NAND Gate.
VCC=5V
n ALL INPUTS HIGH.
• QI is reverse active.
RB RCP
• QO is saturated.
VOUT
D1 • VOL = VCES
VA QI QO
VB RD n ANY INPUT LOW.
VC • QI is saturated.
• QO is cut off.
• VOH = VCC
University of Connecticut 71
TTL Switching Speed: tPLH
VOUT
VCC=5V 5
4
RB RC RCP
3
VOUT 2
VA QI QS
VB QO 1
CL
VC RD
0 t (ns)
0 100 200 300
University of Connecticut 73
TTL with Active Pullup
n With a high output, VCC=5V
n QS is cutoff
RB RC
n QP is forward active
n With a low output, QP
VOUT
n QS is saturated VA QI QS
n QP should be cutoff VB QO
VBP = VEP =
VBEP =
University of Connecticut 76
Standard TTL: VTC
β F =70
VCC=5V n VIN=0. QI is saturated; QS, QO
β R = 0.1
are cutoff; QP is forward active.
4kΩ RC 130Ω
1.6kΩ VOH =
QP
VIL =
1/6 NSC 7404
Hex Inverter
(at the edge of conduction, IC=0)
University of Connecticut 77
Standard TTL: VTC
β F =70
VCC=5V n Second Breakpoint. QO turns on.
β R = 0.1
RC
VIN =
4kΩ 130Ω
1.6kΩ
VOUT =
QP
VIN QI QS DL
VOUT n Third Breakpoint. QO saturates.
QO
VIH =
1kΩ
University of Connecticut 78
Standard TTL: VTC
1/6 NSC 7404
VCC=5V VOUT
Hex Inverter 5
4kΩ RC 130Ω 4
1.6kΩ
3
QP
QI QS 2
VIN DL
VOUT
1
QO
β F =70
β R = 0.1 1kΩ
0 VIN
1 2 3 4 5
VNML = VNMH =
University of Connecticut 79
Standard TTL: Low State ROUT
100 2.4 mA 2 mA For the saturated BJT
1.6 mA with IB = 2.4 mA, the
collector current (mA)
80 output impedance is
0.08V 1.2 mA
60
0.8 mA
ROL =
21 mA
40
The very low output
IB = 0.4mA
impedance means that
20 noise currents are
translated into tiny
Characteristics for a 0
noise voltages. Thus
Texas Instruments only a small noise
junction isolated 0 0.1 0.2 0.3 0.4 0.5
digital npn BJTat 25 oC. margin is neccesary.
collector-emitter voltage (V)
University of Connecticut 80
Standard TTL: Input Current
1/4 TI 7400 Quad
VCC=5V n IIH (QI is reverse active)
2-input NAND
RC
I BI =
4kΩ 130Ω
1.6kΩ
QP
VA QI QS DL
VB VOUT I IH =
QO
β F =70
β R = 0.1 1kΩ n IIL (QI is saturated)
I IL =
University of Connecticut 81
Standard TTL: DC Fanout
1/4 TI 7400 Quad
VCC=5V n With high inputs,
2-input NAND
I CI =
4kΩ RC 130Ω
1.6kΩ
I CS =
QP
VA QI QS DL I BO =
VB VOUT
QO n To keep QO saturated,
β F =70
β R = 0.1 1kΩ
N max =
4kΩ RC 130Ω
1.6kΩ
QP
VA QI PL =
QS DL
VB VOUT
QO
β F =70
β R = 0.1 1kΩ
N = 10
P=
University of Connecticut 83
Advanced TTL Designs
n Schottky Clamping. QS and QO may be Schottky clamped,
preventing saturation. This greatly improves tPLH.
n Darlington Pullup. The Darlington pullup arrangement
increases the average output drive current for charging a
capacitive load. Although RCP limits the maximum output
current, this maximum drive is maintained over a wider range of
VOUT than with a single pullup transistor.
n Squaring Circuit. Active pull-down for the base of the output
transistor squares the VTC, improving the low noise margin. An
added benefit is faster charge removal for the output transistor.
n Improved Fabrication. Smaller devices, and oxide isolation,
have steadily reduced parasitic capacitances and reduced RC
time constants.
University of Connecticut 84
Darlington Pullup
n QP2 is added, forming a Darlington
VCC=5V
pair with QP.
RC n The EB junction of QP2 introduces
RCP
900Ω 50Ω a 0.7V level shift, so DL can be
QP
eliminated.
QP2 n QP2 can not saturate, so Schottky
clamping is not neccessary.
REP
3.5kΩ VOUT n REP is needed to provide a
discharge path for QP2 base
charge.
University of Connecticut 85
Squaring Circuit
VOUT
5 VIL 7400
VOUT
QS 74S00
QO VOH 4 BP2
RBD 3
RCD
500Ω 2
250Ω
QD 1 BP3
VOL
0 VIN
1 2 3 4 5
VIH
n There is no path for QS emitter current until QD and QO turn on.
n QS and QO begin to conduct simultaneously.
n BP1 is eliminated from the VTC; in other words, the VTC is “squared.”
n VIL is increased, improving the low noise margin.
University of Connecticut 86
Schottky TTL (74S / 54S Series)
1/4 74S00
quad 2-input NAND VCC=5V
Features:
RB RC RCP n Schottky clamping
2.8kΩ 900Ω 50Ω
n Schottky anti-ringing diodes
QP
n Darlington pullup circuit
QP2
n Squaring circuit
QI QS REP
VA 3.5kΩ n Scaled resistors
VB VOUT
QO
Performance:
RBD
RCD
500Ω n P = 20 mW
250Ω
QD n tP = 3 ns (15 pF)
n PDP = 60 pJ
University of Connecticut 87