Control Unit (single cycle implementation) Building the control unit

• Control unit sends control signals to data path and

memory depending
• Decompose the problem into
– on the opcode (and function field)
– Data path control (register transfers)
– results in the ALU (for example for Zero test)
– ALU control
• These signals control
• Setting of control lines by control unit totally specified
– muxes; read/write enable for registers and memory etc.
in the ISA
• Some “control” comes directly from instruction – for ALU by opcode + function bits if R-R format
– register names – for register names by instruction (including opcode)
• Some actions are performed at every instruction so no – for reading/writing memory and writing register by opcode
need for control (in this single cycle implementation) – muxes by opcode
– incrementing PC by 4; reading instr. memory for fetching next – PC by opcode + result of ALU
inst.
10/22/2004 CSE378 Control unit 1 10/22/2004 CSE378 Control unit 2
Single cycle impl. Single cycle impl.

Example ALU Control

• Limit ourselves to: • ALU control: combination of opcode and function bits
– R-R instructions: add, sub, and, or, slt – • Decoding of opcodes yields 3 possibilities hence 2
• OPcode = 0 but different function bits
bits
– Load-store: lw, sw
– Branch: beq – AluOp1 and ALUOp2
• ALU control • ALU control:
– Need to add for: add, lw, sw – Input 2 ALUop bits and 6 function bits
– Need to sub for: sub, beq – Output one of 5 possible ALU functions
– Need to and for :and – Of course, lots of don’t care for this *very* limited
– Need to or for :or implementation
– Need to set less than for : slt

10/22/2004 CSE378 Control unit 3 10/22/2004 CSE378 Control unit 4

Single cycle impl. Single cycle impl.

Where are control signals needed

Implementation of Overall Control Unit
(cf. Figure 5.13)
• Register file
• Input: opcode (and function bits for R-R instructions) – RegWrite (Register write signal for R-type, Load)
• Output: setting of control lines – RegDst (Register destination signal: rd for R-type, rt for
Load)
• Can be done by logic equations
• ALU
• If not too many, like in RISC machines – ALUSrc (What kind of second operand: register or
– Use of PAL’s (cf. CSE 370). immediate)
– In RISC machines the control is “hardwired” – ALUop (What kind of function: ALU control for R-type)
• If too large (too many states etc.) • Data memory
– Use of microprogramming (a microprogram is a hardwired – MemRead (Load) or MemWrite (Store)
program that interprets the ISA) – MemtoReg (Result register written from ALU or memory)
• Or use a combination of both techniques (Pentium) • Branch control
– PCSrc (PC modification if branch is taken)
10/22/2004 CSE378 Control unit 5 10/22/2004 CSE378 Control unit 6
Single cycle impl. Single cycle impl.

1
 MIPS FloorPlan & Control lines
Basic 3 Operation 1-bit ALU

10/22/2004 CSE378 Control unit 7 10/22/2004 CSE378 Control unit 8

Single cycle impl. Single cycle impl.

Chain Together 32 “3 Op 1-bit ALUs” Basic 4 Operation 1-bit ALU

10/22/2004 CSE378 Control unit 9 10/22/2004 CSE378 Control unit 10

Single cycle impl. Single cycle impl.

Adding SLT to Chain Together 32 “1-bit ALUs”

1-bit ALU &
Detect Overflow

10/22/2004 CSE378 Control unit 11 10/22/2004 CSE378 Control unit 12

Single cycle impl. Single cycle impl.

2
 ALU floorplan & Symbol Control lines

10/22/2004 CSE378 Control unit 13 10/22/2004 CSE378 Control unit 14

Single cycle impl. Single cycle impl.

How are the control signals asserted Control lines

Signal R-type lw sw beq
RegDest 1 0 X X
ALUSrc 0 1 1 0
• Decoding of the opcode by control unit yields MemtoReg 0 1 X X
RegWrite 1 1 0 0
– Control of the 3 muxes (RegDst, ALUSrc,MemtoReg): 3 MemRead
MemWrite
0
0
1
0
0
1
0
0
control lines Branch 0 0 0 1
ALUOp1 1 0 0 0
– Signals for RegWrite, Memread,Memwrite: 3 control lines ALUOp0 0 0 0 1

– Signals to activate ALU control (e.g., restrict ourselves to 2)

– Signal for branch (1 control line)
• decoding of opcode ANDed with ALU zero result
• Input Opcode: 6 bits
• Output 9 control lines

10/22/2004 CSE378 Control unit 15 10/22/2004 CSE378 Control unit 16

Single cycle impl. Single cycle impl.

Computing the Control Computing the Cycle Time

Op5
Signal R-type lw sw beq Op4
Op5 0 1 1 0 Op3
Op4 0 0 0 0 Op2 Suppose the following times apply ...
Op1
Op3
Op2
0
0
0
0
1
0
0
1 Op0 Memory units: 10ns Instruction Mix GCC
Op1 0 1 1 0
ALU and adders: 10ns
Op0 0 1 1 0 Register file ref: 5ns 22% Load
AND AND AND AND
RegDest 1 0 X X All other operations are 0ns. 11% Store
ALUSrc 0 1 1 0 Charges for instructions are ...
MemtoReg 0 1 X X
RegWrite 1 1 0 0 RegDst R-format: 30ns 49% R-type
MemRead 0 1 0 0 ALUSrc OR Load inst: 40ns
MemWrite 0 0 1 0 Store inst: 35ns 16% Branch
MemtoReg
Branch 0 0 0 1
RegWrite OR
Branch: 25ns 2% Jump
ALUOp1 1 0 0 0
ALUOp0 0 0 0 1
Jump: 10ns
MemRead
MemWrite
Branch
ALUOp1
ALUOp0

10/22/2004 CSE378 Control unit 17 10/22/2004 CSE378 Control unit 18

Single cycle impl. Single cycle impl.