CAD Tools (L-Edit) To Implement Layout Design

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VLSI Lab

LABORATORY REPORT
Spring 2017

LAB 03
Title of Lab Experiment : Introduction of modern CAD
tools (L-Edit) to implement layout design of Digital Circuits.
Engr. Aneela Sabir
UMER RIAZ i120583 B
STUDENT NAME ROLL NO SEC

Submission Date: 16th Feburary 2017

______________________________________
LAB ENGINEER SIGNATURE & DATE

MARKS AWARDED: /10


________________________________________________________________
NATIONAL UNIVERSITY OF COMPUTER AND EMERGING SCIENCES (NUCES),
ISLAMABAD

LAB 03 Introduction of modern CAD tools (L-Edit) to


: implement layout design of Digital Circuits.

1. Learning Objectives:
 Software learning L-Edit.
 Implementation of Layout of NMOS,PMOS in L-Edit.
2. Equipment Required:
Software : L-Edit
Introduction of modern CAD tools (L-Edit) to LAB:03
implement layout design of Digital Circuits.
3. Lab Summary:
In this Lab I have implemented NMOS and PMOS Layout’s in L-EDIT software
and also viewed the cross sectional diagrams of NMOS and PMOS Layout’s. First
I opened L-edit and install tanner, Then selected CMOS025 library process for
design rules. After that I select Green color that is for Active region and draw a
rectangle shape Active area. Make another square of active area by the side. Then I
selected Red color Poly Silicon and draw a rectangle shape that is perpendicular to
the Active area. Then draw Blue color Metal to connect two Active regions by the
help of Black color Contact. Then draw N select and P select given in figures
below and at the end draw P well or N well also to cover the whole figure. After
that check errors by the help of DRC click. If no errors then go to tools and click on
cross section to view the cross sectional Diagram. All tasks are completed in the
lab and are shown to the instructor. Screen shots are attached of the tasks that are
completed in lab.
4. Tasks:
NMOS Layout:

NMOS Cross Sectional View:

VLSI LAB NUCES, ISLAMABAD Page 2 of 4


Introduction of modern CAD tools (L-Edit) to LAB:03
implement layout design of Digital Circuits.

PMOS Layout:

PMOS Cross Sectional View

Submission Declaration by the Student:


In submitting this lab write-up to the Lab Engineer/Instructor, I hereby declare that:
 I have performed all the practical work myself
 I have noted down actual measurements in this writeup from my own working
 I have written un-plagarised answers to various questions
 I have/have not obtained the desired objectives of the lab.
Reasons of not obtaining objectives (if applicable):
___________________________________________________________________
___________________________________________________________________
VLSI LAB NUCES, ISLAMABAD Page 3 of 4
Introduction of modern CAD tools (L-Edit) to LAB:03
implement layout design of Digital Circuits.
___________________________________________________________________

Umer 16th,Feb2017
Student’s signature and Date

Student Evaluation by the Lab Engineer:


The Lab Engineer can separate this page from the writeup and keep it for his/her own record. It must
be signed by the student with date on it.
 Lab Work: objectives achieved (correctness of measurements, calculations, answers to questions
posed, conclusion) ________/30
 Lab Writeup: Neatness, appropriateness, intime submission ________/10
 Troubleshooting: Were the student able to troubleshoot his/her work when it was purposedly
changed? ________/10
 TOTAL: ________/50

Feedback on student behaviour:


Encircle your choice. -2 means poorest/worst/extremely inadequate/irrevlevant, 0 gives an average
score, and +2 means best/most relevant/most adequate.

 Did the student join the lab at the start/remained in lab? -2 -1 0 1 2


 Did the student remain focused on his/her work during lab? -2 -1 0 1 2
 Rate student's behaviour with fellows/staff/Lab Engineer? -2 -1 0 1 2
 Did the student cause any distraction during the Lab? -2 -1 0 1 2
 Was the student found in any sort of plagiarism? -2 -1 0 1 2
Additional comments (if any) by the Lab Engineer:
__________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________________________________________________
___________________________
Lab Engineer’s signature and Date

VLSI LAB NUCES, ISLAMABAD Page 4 of 4

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