B.E/B.

Tech EXAMINATIONS, April/May 2019

Third Semester
Electronics and communication Engg
EC8392-DIGITAL ELECTRONICS
Regulation 2017
Answer All the Questions
Part-A (10X2=20)

1.What is the largest binary number that can be expressed with 14 bits?
Determine the equivalent decimal and hexadecimal numbers.
11 1111 1111 11112 = 3FFF16 = 3 × 163 + 15 × 162 + 15 × 161 + 15 × 160 = 16, 383 10
11 1111 1111 11112 = 16, 38310 = 377778 = 3FFF16
2.Find the complement of F=wx +yz and then show that FF’=0.

3.Draw the truth table for a half adder circuit and write the Boolean expressions for sum and carry.

4.What is meant by a decoder circuit?

Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output lines. One of these
outputs will be active High based on the combination of inputs present, when the decoder is enabled. That
means decoder detects a particular code. The outputs of the decoder are nothing but the min terms of ‘n’
input variables lineslines, when it is enabled.

5.Draw the logic diagram and functions table of a SR latch implemented using NAND gates.
6.How many flipflops will be complemented in a 10-bit ripple counter to reach the next count after this count
of ‘1001100111’?

Add 1 to the value and we will get 1001101000.

Total 4 bits are being toggled.

7. Define a “flow table”.

A state transition table with its internal state being symbolised with letters. During the design of
asynchronous sequential circuits, it is more convenient to name the states by letter symbols without
making specific reference to their binary values. Such a table is called a flow table

8. Distinguish between non-critical face and critical race.

critical race
If the final stable state depends on the order in which the state variables changes, the race condition is
harmful and it is called a critical race. This should be avoided.
non-critical face:
If the final stable state that the circuit reaches does not depend on the order in which the state variables
changes , the race condition is not harmful and it is called a noncritical race.
9. A DRAM chip uses two dimensional address multiplexing. It has 13 common address pins with the row
address having one bit more than the column address. What is the capacity of the memory?
The DRAM chip has 13 rows and 14 columns, for a total of 27 address lines. 2 27 = 268, 435, 456 memory
locations. Also, 227 = 27 × 2 20 = 128 × 2 20 = 128 M.

13+12 = 25 Address lines, => Memory Capacity = 225 words

10.A standard TTL gate has the following current specifications:
IOH=400µA,IIH=40µA IOL=16mA, IIH=1.6mA calculate the fanout.
During high condition => Each NAND gate provides 400 uA current at output Each NAND gate sources 60
uA current at input.
Fan-outHIGH = IOH / IIH = 400 / 60 = 6 (Rounded down since cannot drive part of a gate!) During low
condition => Each NAND gate provides 16 mA current at output Each NAND gate sources 1.6 mA current
at input. Fan-outLOW = IOL / IIL = 16 / 1.6 = 10 Fan-out of NAND gate is the lower value… => Fan-out = 6
Part-B( 5X13=65)
11. (a) Use karnaugh map method to simplify the following Boolean function.
F( A,B,C,D) =∑m(2,4,6,10,12)+d(0,8,9,13)
Implement the Boolean function,F using not more than two NOR gates.
(OR)
(b) Implement the following function using Quine McClusky method.
F=∑m(6,7,8,9)+d(00,11,12,13,14,15)
12. (a) With neat diagram, explain the working of a four bit adder –subtractor circuit.
(OR)
(b) With a truth table and logic diagram, explain the operation of a four input priority encoder.

13.(a) Draw the neat diagram of a 4 bit universal shift register and explain its operation.
(OR)

(b) S sequential circuit has two JK flipflop A and B , two inputs x and y and one input z. the flipflop input
equation and circuit output equation are:
JA =Bx+B’Y’ JB =A’x
KA = B’xy’ KB= A+xy’ z= Axy+Bx’Y’
Draw the logic diagram and state table of the circuit. Also derive the state equations for A and B.
14.(a) An asynchronous sequential circuit is described by the excitation function, Y=x1x2’ +(x1+x2’) and the
output function z=y . Draw the logic diagram of the circuit. Derive the transition table and output map.
Also discuss about the behavior of the circuit.
(OR)
(b) Briefly explain about race free state assignment with relevant examples.

15. (a) Implement the full adder circuit using PLA by deriving the PLA programmable table.
(OR)
(b)Explain about the tri-state TTL output configuration with a neat diagram.
Part-C(1X15=15)
16. (a) Derive the ROM programming table for the combinational circuit that squares a 4 bit number of
products terms.
(OR)
(b) Design a counter with T flip-flops that goes through the following binary repeated sequence
0,1,3,7,6,4. Show that when binary states 010 and 101 are taken to be don’t care conditions, the
counter may not operate properly. Find a way to correct the design.

B.E/B.Tech EXAMINATIONS, NOVEMBER/DECEMBER 2019

Third Semester
Electronics and communication Engg
EC8392-DIGITAL ELECTRONICS
Regulation 2017
 Answer All the Questions
Part-A (10X2=20)
1.State De-Morgans’s theorem and mention its use.

2.Convert decimal 8723 to both BCD and ASCII codes . For ASCII an even parity bit is to be append at the left.
3. Convert a two to four line decoder with enable input to 1:4 demultiplexer.
4.Implement Full adder using two half adder.
5.Construct a T FlipFlop from a D-FF.
6.What is the difference between mealy and Moore state machines?
7.Distinguish between fundamental mode asynchronous sequential circuit and pulse mode asynchronous
sequential circuits.
8. What is called dynamic hazard in asynchronous sequential circuit?
9.Explain fan-in and fan-out of a standard TTL IC.
10.What is programmable logic array? How it differs from ROM?
Part-B( 5X13=65)
11.a)Simplify the following using QuineMc-Clusky method
F( A,B,C,D) =∑(0,1,2,3,5,7,8,10,12,13,15) (13)
(OR)
b.i) Given F(A,B,C,D) =∏(1,3,6,9,11,12,14), draw the K-Map and obtain the simplified expression. (06)
ii) Simplify and implement F( A,B,C,D) =∑(0,4,8,9,10,11,12,14) using only NOR-OR logic. (07)
12.a) Explain the operation of BCD to Excess -3 code converter. (13)
(OR)
b.i) Explain 4 bit magnitude comparator with three outputs: A>B,A=B,A<B. (08)
ii) Explain the operation of two bit binary multiplier in detail. (05)
13.a) Design a sequential circuit which has three flipflop A,B and C; one input X_in: and one output Y_out.The
state diagram is shown in figure 1. The circuit is to be designed by treating the unused state as don’t care
conditions.Analyze the circuit obtain from the design to determine the effect of the unused states. Use D-
Filipflop in the design. (13)

(OR)
b. i) Design a BCD synchronous counter which counts in the sequence. (10)
0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,0000
ii) Discuss the working of 4 bit Johnson counter with neat diagram. (03)
14. a) An asynchronous sequential circuit is described by the following excitation and output function.
Y=X1X2’ +(X1+X2’)Y,Z=Y
i) Draw the logic diagram. (05)
ii) Derive the transition table and output map. (05)
iii) Describe the behavior of the circuit. (03)
(OR)
b) i)Discuss in detail about Races. (06)
ii) Explain the race free state assignment. (07)
15.a) i) Implement the following using PLA. (06)
F1=A’B +AC’ +A’BC’
F2=(AB+AC +BC)’
ii)Explain TTL log logic family with totem pole output. (07)
(OR)
b) i) State the advantages of CMOS logic circuit. (03)
ii) Explain static RAM cell using MOSFET. (03)
iii)Write a notes on FPGA with neat diagram. (07)
Part-C(1X15=15)
16.a) i)Design an odd parity generator that generates an odd parity bit every input string of 3 bits.
ii)Explain the need of Parity Checker circuit with necessary diagrams. (15)
(OR)
b.Derive the state table and state diagram of the sequential circuit shown in figure. Explain the function that
the circuit performs. (15)