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Understanding the Switching Mechanism in RRAM using in-situ TEM

i i 2 i i
K.L. Pe/ ", R. Thamankar , M. Sen , M. Bosman , N. Raghavan , K. Shubhakar
2
J Engineering Product Development, Singapore University o/Technology and Design, Singapore 48 7372 Institute 0/ Materials Research and
2
Engineering (IMRE), Pusionopolis Way, Singapore138634. *Email: peykinleong@sutd.edu.sg.Ph: +656303661

Summary low compliance current switching.

The understanding of the switching mechanisms in resistive random
access memory is of interest as one can use the fundamental Metal-rich Nano-filaments
For higher compliance current settings of >IOf..lA, the top electrode
mechanisms to better design the memory structure for enhancing both
switching and reliability performance. Various analytical methods have would play an important role in the switching mechanisms. To study

been explored to better understand the wear-out and eventual failure this in detail, an asymmetric NilHfD2/SiOx!n + Si(I00) (i.e., MIS)

mechanisms of RRAM stacks. This includes atomic-scale structure was used for in-situ TEM analysis. "In-situ" electrical testing

characterization methods like STM-/AFM-based techniques as well as was carried out using a scanning tunneling microscopy (STM) holder

enhanced TEM techniques and it derivatives like in-situ analysis while inside a TEM. A highly doped Si(I00) was used as a starting substrate

stressing the RRAM samples through electrical, optical and mechanical for the 100nm Ni/3nm HfD2/0.7nm SiOx MIS samples. This sample

means at evaluated temperature. In this talk, we show that a direct was further processed to get a comb-shaped structure by focused ion

observation of the mechanisms responsible for the switching beam (FIB) milling, giving multiple "isolated" test samples for local

phenomena in metalloxide/semiconductor(MIS) RRAM stacks is stressing in during TEM analysis. The whole sample was attached to a

possible by retrofitting a TEM sample holder with an electrical feed­ grounded copper TEM grid. A STM-based tungsten tip was used for in­

through to a STM tip that applies an electrical bias to the MIS RRAM situ electrical stressing of the individual test structure (Figs. 2(a) & (b».

stack of interest. Real-time (or in-situ) switching information can be For electrical switching, a voltage sweep from 0 to 5V in steps of 0.3

obtained for both SET and RESET cases. The developed techniques secN was initally applied to the device to establish a forming process.

have been proven reliable in performing switching cycles many times More detials of the SET and RESET process can be found in ref. 2 & 3.

while observing the switching phenomena under TEM analysis at nano­ Upon a SET process, an isolated trapezoidal-shape defect was always

scale. observed in the n+ Si substrate as shown in Figs. 2(c-e) with its size
increases with increasing compliance current. Fig. 3(a) shows the I-V
Introduction
traces of a stressed sample while being observed under a TEM analysis.
Resistive random access memory (RRAM) has attracted much attention
A sudden increase in the leakage current of about 2 orders of magnitude
in research community due to its high-density, fast speed, and low
was found at around 13seconds. Figs. 3 (b)-(e) show the micrographs
energy operation in the possible nonvolatile random access memory
taken at different SET stages from a recorded video. Upon detailed
(NVM) application. RRAM devices work under the principle of
analysis, it was found that heavy atoms from the top metal electrode
resistance switching between high resistance state (HRS) and low
suddenly migrated/diffused into the dielectric stack and then the Si
resistance state (LRS) forming essentially the 'O'and '1'of the binary
substrate, forming a unique geometrical defect which was an inverted
logic. RRAM cell consists two metal electrodes separated by a metal
pyramid. The TEM results in Figs. 3(f) & (g) further confirm a bowl­
oxide such as Si02, Ti02 and HfD2. Initially the RRAM cell is
shape nano-filament. Figs. 3(h) & (i) show the chemical analysis of the
subjected to a SET process where a conductive path or filament is
nano-filament using EELS and EDS, confirming that the diffusion of Ni
formed between the top and bottom electrodes separated by the metal
from the top electrode into the dielectric and the silicon substrate during
oxide. The transition between the two states can be a complicated
a SET process. Similar results of a RESET process are shown in Figs.
process depending on the level of compliance current used in the
4(a)-(e). The ON/OFF ratio is more than 1000 leading to the switching
memory switching. At lower compliance current (such as <1Of..lA) [I],
off the device evidently confirmed by a very low current level.
we see that the switching occurs due to the conductive path formation
Physically, due to the lower resolution of in-situ TEM analysis,
mainly by oxygen vacancies, while at higher compliances, the
observation of minute microstructural change was not possible. On the
conduction path is mainly metal-rich (i.e., metal nano-filament) by the
other hand, high resolution TEM and STEM micrographs in Figs. 4(d)
formation of migration or diffusion of top metal electrode materials into
and (e) and the EELS and EDS chemical analysis clearly show that the
the oxygen vacancy-rich oxide defect network [2,3]. In this invited
filament has ruptured and is disconnected in the dielectric.
paper, a detailed study of switching mechanism in
metal/oxide/semiconductor (MIS) stacks by in-situ TEM analysis is
One of the major driving forces that causes the "switch-off' / rupture of
presented. The focus is on understanding the physical mechanisms
the nano-filament during RESET is the Joule heating at high current.
responsible for the SET and RESET process and the associated
Carefully EELS analysis shown in Fig. 5 reveals that Ni residuals are
structural and chemical compositional change in RRAM stacks [2-4].
present in the in the neighbourhood of the original "nano-filament"
location in the dielectric, but their concentration is much less than after
Oxygen Vacancy-rich Nano-filaments
the forming/SET transition. It is believed that these residual metal
To study the effect of the low current compliance in MIS stacks, we
atoms/complexes/compounds in the oxide network are the key
used nano-transistor structures that were electrically stressed until a
contributor to a higher leakage profile of the RRAM stack upon more
SET was observed and then subjected it to TEM analysis. Fig. I(a)
switching cycles, leading to a narrowing of the window and lower
shows an example of the TEM cross-sectional micrograph of a
endurance. It is worth to mention that for the SET and RESET process
poly/SiON gate transistor in which a SET was programmed. The
described in Figs. 3 and 4 could be repeated many times on the same
electrical location of the leakage path is at the center of the channel
filament using in-situ basing, while the switching voltage and current
length. The HRTEM micrograph (Figs.l(b) and (c» show a DBIE
are well reproduced during the cycles which we observed on other real­
found at the breakdown responsible for the increase in the leakage
time TEM analyzes.
current of the 2 nm gate oxide after the SET process. It is inferred
Conclusion
clearly that the percolation path directly atop of DBIE is invisible in
Our in-situ TEM analysis of MIS RRAM stacks show that the switching
ordinary TEM/STEM microscopic modes. Subsequently, TEMIEELS mechanisms of the SET and RESET process for compliance current of
analysis was performed at the breakdown location (i.e., above the > IOf..lA is highly correlated to metal nano-filaments formed by metal
DBIE), in an attempt to analyze the chemical nature of the percolation migration/diffusion from the top electrode. The dissolution of the metal
2
path. Detailed analysis of the Si L ,3 edge at the "breakdown oxide" nano-filament in the dielectric network upon RESET is found to
above DBIE shown in Fig. I(d) revealed a relative increase in the EELS responsible for the high resistance state but at an expense that metal
intensities from 100 eV to 105 e V, suggesting the presence of Si atoms residuals in the oxide can lead to reliability concerns. Oxygen vacancies
coordinated with less than 4 oxygen atoms (i.e., sub-oxide with oxygen are found to be another key composition in the nano-filament for low

vacancies) and possible Si nano-scopic clustering (i.e., defective nano­ current switching (lOf..lA). The scaling of RRAM devices will be
determined by the size the nano-filament.
Si wire) at the core of the conduction path [5]. Oxygen-rich vacancy
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Fig. I(a) TEM cross-sectional
transistor stack with a dielectric breakdown, similar to
a SET process in ReRAM where the leakage current
surges by 1-2 orders after switching. The location
measured electrically is at the center of the channel
length, as highlighted in the dotted circle [I].
' D BIE':
105 110
Energy loss (eV)
views of a nano­ Fig. I(b) High resolution TEM lattice micrograph of the Fig. I(d) Background corrected Si_L2•3 edge spectra
breakdown (i.e., switching) location in I(a). DBlE is from breakdown (solid), non-breakdown (dash-dotted)
marked and the oxide area on top of the DBIE bump is gate oxide and oxide/Si interface (short-dashed) of
displayed. (c) Annular Dark field micrograph of the I(a). The inserted figure shows the enlarged plot from
breakdown location. It shows no difference for the oxide 105 eV to I10 eV for breakdown and non-breakdown
area on top of the DBIE bump as compared to the non­ oxide [I].
breakdown oxide [I].

(a)
(b)

Different pillars as individual

electrical stressing sites
I-------J-------�

Fig. 2 Set-up for atomic-scale studies of filament formation and resolution in MIS stacks by real-time TEM analysis. (a) NilHfO,lSiO'/n+Si stack is attached to a Cu
support grid which is electrically grounded. Using a dedicated TEM holder, a STM tip is placed at the top (metal electrode) side for biasing. (b) The TEM sample in detail.
Several finger-shaped trenches are cut with FIB, to produce different sites for electrical stressing; this allows a systematic study of the dielectric breakdown for various
current/voltage settings. TEM analysis was done for increasing order of compliance currents (lIlAIlOJ.lAIlOOJ.lA) using in-situ electrical stressing set-up shown in (a).
Nano-filaments and NiSi-like defects were formed in the oxide and Si substrate as shown in (c) small (IJ.lA), (d) medium (lOJ.lA) or (e) large (lOOJ.lA), respectively [2,3].

In-silu
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Fig. 3 TEM analysis of B Pt 0:005
nano-filament formation of a SET 10' ,�. ;1 ....oI.! �'0"
� W,tip N" '"
process. (a)
stressing while
Real-time
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analysis. g JP • ':�'-i! ' • \.
(b)-(e) Real-lime TEM �
micrographs show the formation �
Snm
of a metal filament, punching
through the dielectric layer into 10-6 !
the silicon substrate during a SET
},. ,;" }� ,;'" ';0 1,
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process. The times indicated in Time (Second)

the ITIlcrographs correspond to U, 13.23, 14.00 and 16.00 seconds from
the start of the electrical stressing during TEM analysis, respectively. (f)­
(g) High resolution TEM & HAADF STEM micrographs of the SET
stack in (e). (h)-(i) EELS and EDS results that map the chemistry of the ""'
nano-filament r21.
Referenc;;7
el.al,
1. X. Li Appl.

10"�A "., Constant voltage stressing@2.6V B·' • 0:005 c':· -' . .� 5:17 5
Phys. Lett. 93, 072903
(2008). 2. X. Wu el 01.,
g 10-5
E
I RESET
�.
'
if:i� .
f
ltf·,\/t:.I;.' t� ':t'l\lI�t\\i:"\i�':iO'
') , . 'Il '
.'..... , f ...� . ' . \'
JAP, 113, 114503
(2013). 3. X. Wu el 01.,
i!!
5 10�
I"
1 I . , " •
�
'\ ' ,' .\'.' , t . �'''. Adv. Electron. Mater., I,
11500130 (2015). 4. M.
� r:.....j'\J�. .
U
-.-JI�l Mei el.al, Microelect.
10.' Rel.,10.1016/j.microrel.
10 12 14 2015.12.037. 5. X. Li,
Time (Second) et. 01, Appl. Phys. Lett.,
Fig. 4 In-situ TEM analysis of nano-filament resolution of a RESET process. (a) Real-lime 93, 26, 262902, (2008)
electrical stressing while TEM analysis. (b) & (c) Real-time TEM micrographs showing the 6. W.H. Liu el. ai, IEEE
morphology of the metal filament. The times indicated in the micrographs correspond to 0 IEDM, 6.5.1, 2009.
and 5 seconds respectively upon electrical stressing. (d)-(e) High resolution TEM & HAADF
STEM micrographs of the RESET stack in (c). (f)-(g) EELS and EDS results mapping the
chemistry of the electrically "switched-off' device shown in (c) [2]. Poe.iriofIjnm)

Fig. 5 (a) An example of

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, . (shown by 2 dotted red lines)
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.

. �. . ., . after in-situ electrical

Ni depletion • •
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.. .' .. .' (b) a RESET case. (c)
,..
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Vertical EDX Ni profile (red
\ J.. . circles) across the Ni
u -=::... .. �� U
U electrode, large filament and
Si substrate, of the location
indicated by the red striped line in (a). (d) Vertical EDX Ni profile (red circles) across the Ni
electrode, nano-filament and Si substrate, of the location indicated by the red striped line in (b) [4].