BITS Pilani

Pilani Campus

MEL G 621: VLSI Design

Basics of MOS
Outlines

Introduction

MOS Capacitor

Electrical Characteristics of MOS

nMOS I-V Characteristics

pMOS I-V Characteristics

Gate and Diffusion Capacitance

Pass Transistors

RC Delay Mode

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
MOS Device

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS Device

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS Capacitor

MOS structure forms capacitor

Carrier concentration and its local distribution within semiconductor
substrate is manipulated by external voltages applied to the gate and
substrate terminals.
VG
Metal
Oxide
Oxide layer 10-50nm

P-type doped Silicon

VB

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus


Identify the type of substrate
E0
qχ
EC

1.1eV Ei
qφF
EF

EV

Energy Band Diagram

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

P Substrate

Fermi Potential
E0
φ F = (EF – Ei)/q
qχ
-Ve qφFp = kT/q ( ln(n /N ))
i A
EC
+Ve qφFn = kT/q ( ln(ND/ni))

1.1eV Ei

Work Function
qφFp
EFp
qφ S = qχ + ( EC- EF)
EV
Energy required for electron to Move from
fermi level to free space. Energy Band Diagram

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

 Metal Oxide Semiconductor
E0
qχ=
qφM 0.95eV qχ=
4.1eV EC
4.15eV
EFm
EC

Ei
8eV
EFP

EV

EV
Energy band diagram of components that make up MOS
Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
Example

Given equilibrium fermi potential of doped silicon substrate is
equals to 0.2 ev E0
qχ

Electron affinity of silicon : 4.15ev
EC


Determine the work function ? 1.1eV Ei
qφFp
EFp

EV

Energy Band Diagram

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus


Work function of the doped silicon

qφ S = 4.15eV + 0.55 eV + 0.2eV

= 4.9eV

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

 Metal Oxide Semiconductor
E0
qχ=
qφM 0.95eV qχ=
4.1eV EC
4.15eV
EFm
EC

Ei
8eV
EFP

EV

EV
Energy band diagram of components that make up MOS
Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
Built-in potential

Work function of the doped silicon
= qφ S= 4.15eV + 0.55 eV + 0.2eV = 4.9eV


Work function of Aluminum gate
= q φ M = 4.1eV


Built in potential difference across MOS system is

= -0.8V

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Energy band diagram MOS system

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Energy band diagram

Work function difference:

Voltage drop occurs across the MOS
System

Part of this built in voltage drop
occurs across the insulating layer

The rest drop at the silicon surface
next to the silicon-oxide interface

Energy band at surface bends due to
voltage drop across MOS

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Energy band diagram

Surface fermi level move close to
intrinsic fermi level.
 Fermi potential at surface φS is
smaller in magnitude than bulk
Fermi potential φF
 Work Function Difference qφM- q φS
 Flat band Voltage VFB = φ M - φ S

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS under External Bias

Gate terminal controlling parameter

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MOS under External Bias

Gate terminal controlling parameter

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS under External Bias

Cause the band to bend downwards. Holes repelled back from
surface causing Depletion region.
 Thickness of depletion region xd

Hole charges in a thin horizontal layer parallel to the surface is
dQ = -q NA dx

Change in surface potential required to displace this charge sheet
dQ by a distance xd from surface – Using Poisson’s Equation

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS under External Bias

Integrating along the vertical dimension (perpendicular to surface)
yields


Depth of depletion region is :


The depletion region charge density, which consists solely of fixed
acceptor ions in this region:

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS under External Bias

Gate terminal controlling parameter

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Inversion

A Further increase in positive bias downward bending of energy
bands will increase as well
 Ei (mid gap energy level) becomes smaller than Efp (fermi level on
surface

Means semiconductor becomes n type semiconductor

Condition is called surface inversion

Density of mobile electrons on the surface becomes equal to the
density of holes in the bulk substrate

Requires surface potential has the same magnitude, but the reverse
polarity as the bulk Fermi potential.

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Inversion (continue...)

Further increase in the gate voltage leads to an increase of mobile
electron concentration on the surface

But not to an increase of the depletion depth. Thus, the depletion
region depth achieved at the onset of surface inversion is also equal
to the maximum depletion depth, xdm, which remains constant for
higher gate voltages

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Threshold Voltage

Factors affecting threshold voltage:

Work function difference between gate and channel

Gate voltage component to change the surface potential

Gate voltage component to offset the depletion region charge

Voltage component to offset the fixed charges in gate–oxide and
in silicon-oxide interface

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Threshold Voltage

Factors affecting threshold voltage:

Work function diff =
φ GC = φ F( substrate) - φ F (gate)
 Change surface potential by - 2φ F

To offset depletion region charge due to fixed acceptor ions
located in depletion region QB/Cox

Gate voltage component to offset positive charge at the
interface: -Qox/Cox

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Threshold Voltage

Factors affecting threshold voltage:

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Threshold Voltage

General expression
 Substrate Fermi potential φ F negative for nMOS, positive for
pMOS
 Depletion region charge density QB & QBO negative for nMOS
positive for pMOS
 Substrate bias voltage VSB Positive for nMOS, negative for
pMOS

Substrate bias coefficient, positive for nMOS and negative for
pMOS
 VT positive for nMOS, VT negative for pMOS
Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
Current Voltage Relationship

Analytical derivation of MOS I-V Relationship

Require several approximations to simplify the problem

3-D

Gradual channel
approximation
(CGA)

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Current Voltage Relationship
 Channel Voltage with respect to source is Vc(y)


Assuming the threshold voltage constant along the entire
length of the channel y = 0 to y = L


Assuming Ey is dominant comparing to Ex


Current flow becomes a one dimensional problem

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
Gradual Channel Approximation

 VS = VB = 0V

 VGS and VDS external Parameters controlling ID

 VGS > VTO

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Boundary Conditions
 Vc(y = 0) = Vs = 0
 Vc( y = L) = VDS

Assuming the entire channel inverted
 VGS >= VT0
 VGD = VGS - VDS >= VT0
 Channel current ID is due to electrons in the channel region
traveling from source to drain under the influence of Ey

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Total mobile charge
 QI (y) – Total mobile electron charge in the surface inversion layer (
as a function of VGS and VC(y))
 QI(y) = - Cox [ VGS – VC(y) - VT0 ]

Incremental resistance dR of the differential channel segment dy is
dR -ve of the inversion layer
charge Q1


Assume channel charge density is uniform accross this segment
Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Apply ohms law

Voltage drop across dy is

 Integrating on both sides i.e from (0-VDS), (y=0, y= L)

 Using QI(y) = - Cox [ VGS – VC(y) - VT0 ]) (already derivated)

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 ID = µ n (Cox/2 )(W/L) [ 2(VGS- V TO) VDS – VDS2
= (k’/2). (W/L). [ 2(VGS- V TO) VDS – VDS2]

ID = (k/2) [ 2(VGS- V TO) VDS – VDS2]

where k’ = µn Cox and k = k’ ( W/L)

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Transistor in saturation
 The value of gate to source voltage VGS needed to cause surface
inversion

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Transistor in saturation

Inversion layer charge at the source end
QI( y=0) = -COX ( VGS- VTO)


Inversion layer charge at the drain end

QI( y=L) = -COX ( VGS- VTO- VDS)

 At the edge of saturation VDS = VDSAT

VDS = VDSAT = VGS- VTO


The inversion layer charge at the drain end becomes zero

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Transistor in saturation

The effective channel length L’ = L - ∆L


The pinch off point moves from the drain end of the channel toward
the source with increase in VD
 ∆L is the length of the channel segment with Q = 0
I

The remaining portion of the channel between the pinch of point and
the drain will be in depletion mode
 Since Q (y) = 0 for L’<y<L, the channel voltage at pinch-off point
I
remains at VDSAT
i.e., V ( y = L’) = V
C DSAT

ID (sat) = µ n (Cox/2 )(W/L') [ (VGS- V TO)2]

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Transistor in saturation
 For VDS > VGS - VTO MOS is in saturation

 For VDS ≥= VDSAT = VGS – VTO


Drain current remains more or less constant

 ID(sat) = µn (Cox/2 )(W/L') [ (VGS- V TO)2]

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Transistor in saturation
 As L’ decreases with increasing VDS, the saturation Mode current
ID( sat) also increases with VDS


Approximating effective channel length L’ = L - ∆L

 ID( sat) = [1/(1-∆L/L)] µn (Cox/2 )(W/L) [ (VGS- V TO)2]

term accounting for channel length modulation

 By empirical relation : (1-∆L/L) = 1- λVDS ( λ empirical model parameter)

ID( sat) = µ n (Cox/2 )(W/L) [ (VGS- V TO)2] (1+ λVDS )

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
For nMOS Transistor
 ID = 0 for VGS < VT

 ID(lin) = µn (Cox/2 )(W/L) [ 2(VGS- V TO) VDS – VDS2]

for VGS > = VT
VDS < VGS – VT

 ID( sat) = µn (Cox/2 )(W/L) [ (VGS- V TO)2] (1+ λVDS)

for VGS >= VT
VDS >= VGS - VT

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

 Questions ?

Thanks

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus