Minimum & Maximum Mode

Systems
‰In the minimum mode, all the control
signals for the memory and I/O are
generated by the microprocessor

This reduces cost but provides low

functionality.
‰In the maximum mode, a separate IC called
the 8288 Bus Controller is used to provide
control signals for memory and I/O operations.
‰The minimum mode signals can be
divided into the following basic groups:

address\data bus
status
control
interrupt
DMA
‰In the maximum mode, a separate IC
called the 8288 Bus Controller is used to
provide control signals for memory and
I/O operations.

The S0-S2 pins are decoded by the 8288 to provide control

signals as ALE, DEN, DT/-R, -IOWC (I/O Write Command),

-IORC (I/O Read Command), -MWTC (Memory Write

Control), -MRDC (Memory Read Control), -INTA etc.

 Address / data bus
‰As an address bus , they are used to
carry address information to the memory
and I/O ports
‰The address bus is 20 bites long and consists
of signal lines A0 through A19
‰The 16 data bus lines D0 through D15 are
actually multiplexed with address lines A0
through A15
By “multiplexed “We mean that the bus works as
an address bus during one period of time and as
a data bus during another period
 Status Signals
‰The four most signification address lines , A19
through A16 are also multiplexed , but in this
case with status signals S6 through S3

‰These status bites are output on the bus at

the same time that data are transferred over the
other bus lines
‰Bits S4 and S3 together form a 2 – bit binary
code that identifies which of the 8086 internal
segment registers was used to generate the
physical address that was output on the address
bus during the current bus cycle
 Control signals
‰The control signals are provided to
support the 8086's memory and I/O
interfaces
They control functions such as:
¾when the bus is to carry a valid address
¾in which directions data are to be
transferred over the bus
¾when valid wire data are on the bus
¾when to put read data on the system bus
 Interrupt signals

Interrupt operations fall into two classes

software or hardware initiated

Hardware interrupts can be classified

as non-maskable or maskable

Interrupts result in a transfer of control

to a new program location
 DMA
‰The direct memory access (DMA)
interface of the 8086 minimum -mode
system consists of the HOLD and HLDA
signals

‰When an external device wants to take

control of the system bus, it signals this
fact to the 8086 by switching HOLD to the 1
logic level .
 Registers 0f 8086 cpu
‰There are four different 64 KB segments
for instructions, stack, data and extra data.
‰To specify where in 1 MB of processor memory
these four segments are located the processor
uses four segment registers

1-Code segment (CS) is a 16-bit register containing

address of 64 KB segment with processor
instructions
‰The processor uses CS segment for all
accesses to instructions referenced by
instruction pointer (IP) register

¾CS register cannot be changed directly.

¾The CS register is automatically updated during

far jump, far call and far return instructions.
2-Stack segment (SS) is a 16-bit register containing
address of 64KB segment with program stack.

¾the processor assumes that all data referenced by

the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment.

¾SS register can be changed directly using POP

instruction.
3-Data segment (DS) is a 16-bit register containing
address of 64KB segment with program data

¾the processor assumes that all data referenced by

general registers (AX, BX, CX, and DX) and index
register (SI, DI) is located in the data segment.

¾DS register can be changed directly using POP

and LDS instructions
4-Extra segment (ES) is a 16-bit register
containing address of 64KB segment, usually with
program data

¾the processor assumes that the DI register

references the ES segment in string manipulation
instructions

¾ES register can be changed directly using POP

and LES instructions.
 General registers
‰The eight, 16-bit general purpose registers are
used for arithmetic and logical operations.

‰In addition, the four data registers labeled AX,

BX, CX and DX may be further subdivided for 8-
bit operations into a high-byte or low-byte
register, depending where the byte is to be
stored in the register
 Flag Registers
‰After the execution of an instruction the
flags may be set (1), cleared or reset (0),
unchanged or undefined

‰Undefined means that the value of the flag

prior to the execution of an instruction may not
be retained and its value after the instruction is
executed cannot be predicted

Flags are a 16-bit register containing nine 1-bit

flags