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Rajarajeswari College of Engineering: Analog and Digital Electronics Laboratory Manual 15CSL 37
Rajarajeswari College of Engineering: Analog and Digital Electronics Laboratory Manual 15CSL 37
Rajarajeswari College of Engineering: Analog and Digital Electronics Laboratory Manual 15CSL 37
Author
Prof.VM.Saravanaperumal
Asst. Professor /CSE
© Rajarajeswari college of engineering 2017
Directions to use PSPICE:
Go to: Start → Programs → Cadence → OrCAD Capture CIS
Select: File → New → Project → (Enter the Project name, and select Analog or Mixed
A/D)
Select: Place → Part ( select the required components)
Select: Place → Wire ( connect the components using wire)
Select: Place → Ground (to ground the circuit)
Select: PSPice → New simulation ( create a new simulation profile)
Set the 'Run to time' as t= 1/ f (f= frequency of input waveform)
Set the 'Maximum step size' as: 0.0001m
Check the 'Skip the Initial Transients bias point calculation' box
Select: PSPice → Run
Introduction to Xilinx
Xilinx is one of most popular software tool used to synthesize VHDL/Verilog code. This tool
includes many steps. To make user feel comfortable with the tool the steps are given below:-
• Double click on Project navigator. (Assumed icon is present on desktop).
• Select NEW PROJECT in FILE MENU.
• Enter following details in New Project Wizard – Create New Project window –
Project name : PANNA
Project location : C:\Xilinx\PANNA
Top-Level source type : HDL
• Click Next.
• Enter following details in New Project Wizard – Device Properties window –
Product Category : All
Device family : Spartan3
Device : XC3S200
Package : FT256
Speed :-4
Top-Level Source Type : HDL
Synthesis Tool : XST (VHDL/Verilog)
Simulator : ISE Simulator (VHDL/Verilog)
Preferred Language : Verilog
• Enable Enhanced Design Summary and Click Next for three times and finally Click Finish.
• In Sources window Right Click on xc3s200-4ft256, select New Source…
Enter the following details in New Source Wizard – Select Source Type window –
File name : and_gate
4 Designgates. and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic
a)Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the
5 simplified logic expression using 8:1 multiplexer IC.
b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify its
working.
6 Designgates. and implement code converter I)Binary to Gray II) Gray to Binary Code using basic
7 Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using basic Logic
Gates with an even parity bit.
a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.
8 b) Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge triggering.
Simulate and verify its working.
a) Design and implement a mod-n (n<8) synchronous up counter using J-K Flip-Flop ICs and 9
demonstrate its working.
b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and verify its
working.
10(n<=9)
Design and implement an asynchronous counter using decade counter IC to count up from 0 to n
and demonstrate on 7-segment display (using IC-7447).
11 Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC through IC74393 dual
4-bit binary counter).
12 Open ended experiment – 1: To study 4-bit ALU using IC-74181.
EXPERIMENTS
1. EXPERIMENT NO: 01
2. TITLE: SCHMITT TRIGGER
3. LEARNING OBJECTIVES:
• To learn about the Op-Amp based Schmitt trigger circuit and understand its working.
• To learn simulation of Op-Amp based Schmitt trigger circuit.
4. AIM:
• To design and implement an inverting Schmitt trigger using Op-Amp for a given UTP and
LTP values. .
• To implement a Schmitt trigger using Op-amp using a simulation package for two sets of
UTP and LTP values.
5. MATERIAL / EQUIPMENT REQUIRED:
6. THEORY / HYPOTHESIS:
Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse. Here, the
input voltage triggers the output voltage every time it exceeds certain voltage levels called
the upper threshold voltage VUTP and lower threshold voltage VLTP. The input voltage is
applied to the inverting input. Because the feedback voltage is aiding the input voltage, the
feedback is positive. A comparator using positive feedback is usually called a Schmitt
Trigger. Schmitt Trigger is used as a squaring circuit, in digital circuitry, amplitude
comparator, etc.
7. PROCEDURE / PROGRAMME / ACTIVITY:
1. Test all the components.
2. Rig up the circuit according to the circuit diagram.
3. Apply VCC =12V, VEE = -12V.
4. Apply a sinusoidal signal of peak voltage say 5V, with a frequency of 500Hz.
5. Observe the rectangular output on the CRO, measure the UTP and LTP values, compare
them with the design values.
6. Keep the CRO in X-Y mode (Vin to X-channel, Vout to Y-channel). Observe the transfer
curve which is called the Hysteresis curve.
8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:
• a) Hardware Implementation
Let us design an inverting Schmitt trigger for a UTP =+1V and LTP = -1V
Let VCC = +12V (= +Vsat)
VEE= -12V (= -Vsat) , R2 =1K
We know UTP = +BVsat , ie 1V= (R 2 /(R1 + R2))12V
ie 1 = 1K/ (R1 + 1K )* 12
R1 + 1K =12K
R1=12K -1K = 11K
The above design will set an LTP =
-1V 11. GRAPHS / OUTPUTS:
-
1. EXPERIMENT NO: 2
2. TITLE: RELAXATION OSCILLATOR
3. LEARNING OBJECTIVES:
• To learn about the rectangular waveform generator circuit and understand its working.
• To learn to implement a rectangular waveform generator using a simulation package.
4. AIM:
• To design and implement a rectangular waveform generator(op-amp relaxation oscillator)
for a given frequency.
• To implement a rectangular waveform generator (Op-amp relaxation oscillator) using a
simulation package, and observe the change in frequency when all the resistors values are
doubled
5. MATERIAL / EQUIPMENT REQUIRED:
6. THEORY / HYPOTHESIS:
As the name indicates, here there is no input signal, but circuit produces a square wave
output that swings between +Vsat and –Vsat. The capacitor charges through the feedback
resistor R, exponentially towards +Vsat. But capacitor voltage never reaches +Vsat because
the voltage crosses the UTP. When this happens the output wave switches to –Vsat. With
the output now in negative saturation, the capacitor discharges. When the capacitor voltage
crosses through zero, the capacitor starts charging negatively toward –Vsat.When the
capacitor voltage crosses the LTP, output switches back to +Vsat. The above events repeat,
resulting in rectangular output.
7. PROCEDURE / PROGRAMME / ACTIVITY:
1. Check all the components
2. Rig-up the circuit according to the circuit diagram.
3. Apply +Vcc of say 15V and –VEE of -15V.
4. Connect the CRO channel-1 across the capacitor and channel-2 across the output.
5. Observe the output rectangular waveform and capacitor waveform.
6.Calculate the period of the waveform, T.
7. Note down the out put voltage (+Vsat and –Vsat) and UTP and LTP
voltages. (Observed Vsat will be < +Vcc and | - Vsat | < | -VEE |)
8. Draw the graph of the output waveform and the capacitor voltage waveform.
b) Simulation
Case 1: for the original circuit
b)
Case 1: Period of the output waveform =
___________ms Frequency f = ___________Hz
Case 2: With all resistors doubled:
Period of the output waveform =____________ms
Frequency f = ___________Hz
-
1. EXPERIMENT NO: 03
2. TITLE: ASTABLE MULTIVIBRATOR
3. LEARNING OBJECTIVES:
• To learn about the astable multivibrator circuit using 555 timer for a given frequency and
duty cycle.
4. AIM:
• To design and implement an Astable multivibrator using 555 timer, for a given frequency
and duty cycle.
5. MATERIAL / EQUIPMENT REQUIRED:
6. THEORY / HYPOTHESIS:
• Multivibrator is a form of oscillator, which has a non-sinusoidal output. The output
waveform is rectangular. When 555 timer is used as astable multivibrator, it has no
stable states, which means it cannot remain indefinitely in either state. This results in
rectangular output.
• The multivibrators are classified as:
• Astable or free running Multivibrator: It alternates automatically between two states
(low and high for a rectangular output) and remains in each state for a time
dependent upon the circuit constants. It is just an oscillator as it requires no external
pulse for its operation.
• Monostable or one shot Multivibrator: It has one stable state and one quasi stable
state. The application of an input pulse triggers the circuit time constants. After a
period of time determined by the time constant, the circuit returns to its initial stable
state. The process is repeated upon the application of each trigger pulse.
• Bistable Multivibrators on other hand have both stable states. It requires the
application of an external triggering pulse to change the output from one state to
other. After the output has changed its state, it remains in that state until the
application of next trigger pulse.
7. PROCEDURE / PROGRAMME / ACTIVITY:
1. All the components are tested.
2. Circuit is rigged up according to the circuit diagram.
3. Connect CRO-CH1 to pin no.6 (or 2) and CH2 to pin no.3 (Vout) of the 555.
4. Apply a Vcc of +10V.
5. Observe the capacitor voltage waveform at pin no.6. Observe the output waveform at pin
no.3.
6. Note down the period, pulse width, UTP, LTP and VH values.
1. Period,T = _________ms
2. Therefore frequency, f =_________Hz
3. Pulse width, W =___________ms
3. Duty cycle, D = W/T = ________%
4. UTP =_________V
5. LTP=_________V
6. High level of output, VH =__________Volts. (Low level is zero volts).
10. FORMULA / CALCULATIONS:
When 555 timer IC is connected to run as an Astable multivibrator, it gives rectangular
output. Let T be the period of the output waveform. Then duration of T during which output
is high,
-
1. EXPERIMENT NO: 04
2. TITLE: ADDERS AND SUBTRACTORS
3. LEARNING OBJECTIVES:
• To realize the half adder circuits using basic gates.
• To realize the half substractor circuits using basic gates.
Difference=a b+a b
Borrow = ab
Sum = a b c + a b c + a b c + a b c
Carry = A·B + A·C + B·C
-
1. EXPERIMENT NO: 05
2. TITLE: EVM & 8:1 MUX
3. LEARNING OBJECTIVES:
• To learn about various applications of multiplexer.
• To learn and understand the working of IC 74151.
• To learn to realize any function using Multiplexer.
• To develop a Verilog code for an 8:1 Multiplexer using dataflow modeling in Xilinx
simulator.
4. AIM:
• To simplify 4 variable logic expression, simplify it using Entered Variable Map and realize
the simplified logic expression using 8:1 Multiplexer IC.
• To develop the Verilog / VHDL code for an 8:1 multiplexer, simulate and verify its
working.
5. MATERIAL / EQUIPMENT REQUIRED:
• IC 74151, IC 7404
• Patch Cords & IC Trainer Kit
• PC with Windows XP, XILINX software.
6. THEORY / HYPOTHESIS:
0 1
2 If function equals 1 for both values of MEV, enter 1.
1 1 1
0 - 0
6 Iff = 0 for MEV= 0 and f=0 for MEV=1, enter 0.
1 0
0 0 0
7 Iff = 0 for MEV= 0 and f=- for MEV=l, enter 0.
1 -
0 - 1
8. Iff = – for MEV= 0 and f=1 for MEV=1, enter 1.
1 1
0 1 1
9 Iff = 1 for MEV= 0 and f=- for MEV= –, enter –.
1 -
• Assume that the following 4-variable Boolean function is to be implemented using 8:1
multiplexer IC 74151.
Y = F(A,B,C,D) = ∑ (0,1,2,4,5,6,8,9,12,13,14).
• Entered Variable Map Simplification and the simplified expression is shown below:
The Entered Variable Map Truth-Table corresponding to the above expression is shown below:
• Pin Diagram:
Circuit Diagram:
MUX8to1(A,B,C,D0,D1,D2,D3,D4,D5,D6,D7,
Y); input A,B,C,D0,D1,D2,D3,D4,D5,D6,D7;
output Y;
reg Y;
always @ (A or B or C or D0 or D1 or D2 or D3 or D4 or D5 or D7)
case ({A, B, C})
0: Y = D0;
1: Y = D1;
2: Y = D2;
3: Y = D3;
4: Y = D4;
5: Y = D5;
6: Y = D6;
7: Y = D7;
endcase
endmodule
9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:
a)
-
1. EXPERIMENT NO: 06
2. TITLE: Code Converters
3. LEARNING OBJECTIVES:
• To learn the importance of non-weighted code.
• To learn to generate gray code.
4. AIM:
• Design and implement code converter I)Binary to Gray II)Gray to Binary Code using
basic gates.
5. MATERIAL / EQUIPMENT REQUIRED:
• IC 7404 1, IC 7432 2, IC 7411 2 or IC 7486 2
• Patch Cords & IC Trainer Kit
6. THEORY / HYPOTHESIS:
• Binary Codes: A symbolic representation of data/ information is called code. The base or
radix of the binary number is 2. Hence, it has two independent symbols. The symbols used
are 0 and 1. A binary digit is called as a bit. A binary number consists of sequence of bits,
each of which is either a 0 or 1. Each bit carries a weight based on its position relative to the
binary point. The weight of each bit position is one power of 2 greater than the weight of the
position to its immediate right. e. g. of binary number is 100011 which is equivalent to
decimal number 35.
• Gray Codes: It is a non-weighted code; therefore, it is not a suitable for arithmetic
operations. It is a cyclic code because successive code words in this code differ in one bit
position only i.e. it is a unit distance code.
BOOLEAN EXPRESSIONS:
G3=B3
G2=B3⊕B2 = B3B2 + B3B2
G1=B1⊕B2 = B1B2 + B1B2
G0=B1⊕B0 = B1B0 + B1B0
BOOLEAN EXPRESSIONS:
B3 = G3
B2 = G3⊕G2 = G3G2 + G3G2
B1 = G3⊕G2⊕G1 = G3⊕(G2G1 + G2G1)
= G3(G2G1 + G2G1)' + G3(G2G1 + G2G1)
= G3(G2 G1 + G2G1) + G3(G2G1 + G2G1)
= G3G2 G1+ G3G2G1+ G3G2G1+G3
G2G1 B0=G3⊕G2⊕G1⊕G0
9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:
-
1. EXPERIMENT NO: 08
2. TITLE: MASTER-SLAVE JK FLIP-FLOP
3. LEARNING OBJECTIVES:
• To learn about various applications of flip flops.
• To learn and understand the working of IC 7410.
• To learn and understand the working of J-K Master Slave Flip flop.
• To develop Verilog/VHDL code for positive edge triggered D Flip-Flop using behavioral
modeling in Xlinx simulator.
4. AIM:
• To study the truth table of J-K Master Slave flip flop and verify the same.
• To develop Verilog/VHDL code for positive edge triggered D Flip-Flop and simulate its
working.
5. MATERIAL / EQUIPMENT REQUIRED:
b) Simulation
module DFF(Clock, D, Q);
input Clock, D;
output Q;
reg Q;
always @ (posedge Clock)
Q = D;
endmodule
9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:
a)
-
1. EXPERIMENT NO: 09
2. TITLE: SYNCHRONOUS UP-COUNTER
3. LEARNING OBJECTIVES:
• To learn about synchronous Counter and its application.
• To learn and understand the working of IC 7476.
• To learn the design and the working of synchronous counter.
• To develop Verilog/VHDL code for mod-8 up counter using behavioral modeling in Xilinx
simulator.
4. AIM:
• To Design and implement mod n (n<8) synchronous up-counter using J-K Flip Flop.
• To develop Verilog/VHDL code for mod-8 up counter and simulate its working.
5. MATERIAL / EQUIPMENT REQUIRED:
• IC 7476 2
• IC 7408 1
• Patch Cords & IC Trainer Kit,
• PC with Windows XP, XILINX software.
6. THEORY / HYPOTHESIS:
• A Counter is a sequential circuit that goes through a prescribed sequence of states up on
application of input pulse. Counter are in two categories –
• Ripple Counter (Asynchronous Counter) – consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected to
the clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB
receives the clock pulses.
• Synchronous Counter – the input pulses / clock pulses are applied to all clock pulse
inputs of all the flip-flops simultaneously.
• The ripple counter requires a finite amount of time for each flip flop to change state. This
problem can be solved by using a synchronous parallel counter where every flip flop is
triggered in synchronism with the clock, and all the output which are scheduled to change
do so simultaneously.
• The counter progresses counting upwards in a natural binary sequence from count 000 to
count 100 advancing count with every negative clock transition and get back to 000 after
• But during design, we normally know the transition from the present state to the next state,
called Transition table. The transition table is derived using the truth table. Truth table is
constructed using the given counter.
• Here, given counter is mod-5. i.e., the given sequence is: 0, 1, 2, 3, 4, 0, . . .
Now, construct the Excitation table of JK flip-flop using the State diagram / Characteristic table of
JK flip flop. A table that lists the required inputs for a given change of state is called ‘Excitation
table’.
Now by using the excitation table and the transition table, evaluate the flip-flop inputs as shown
below.
Go for K-Map simplification, and after K-Map simplification, expressions for the flip-flop inputs
are as shown below:
Circuit Diagram:
b)
-
1. EXPERIMENT NO: 10
2. TITLE: ASYNCHRONOUS COUNTER
3. LEARNING OBJECTIVES:
• To learn about asynchronous counter and decade counter.
• To learn and understand the working of IC 7490.
• To understand the working of mod-n asynchronous counter using decade counter.
4. AIM:
• Design and implement an asynchronous counter using decade counter IC to count up from
0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
5. MATERIAL / EQUIPMENT REQUIRED:
• IC 7490 1
• IC 7411 1
• IC 7447 1
• Patch Cords & IC Trainer Kit
6. THEORY / HYPOTHESIS:
• A Counter is a sequential circuit that goes through a prescribed sequence of states up on
application of input pulse. Counter are in two categories –
• Ripple Counter (Asynchronous Counter) – consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected to
the clock pulse input of the next higher order flip-flop. The flip-flop holding the LSB
receives the clock pulses.
• Synchronous Counter – the input pulses / clock pulses are applied to all clock pulse
inputs of all the flip-flops simultaneously.
• A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal. In
asynchronous counter a clock signal is provided for one flip-flop and its output is provided
as clock source for next flip-flop. The output of asynchronous counter is not synchronized
with clock signal.
• A decade counter follows a sequence of 10 states and returns to zero after the count of nine.
Such a counter must have at least 4 flip flops to represent each decimal digit since a decimal
digit is represented by a binary code with at least 4 bits.
© Rajarajeswari college of engineering 2017
7. PROCEDURE / PROGRAMME / ACTIVITY:
• Explained along with the circuit diagram.
8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:
• Pin Diagram:
IC 7490 (Decade counter) Internal Diagram of 7490
IC 7447
Divide-by-9: QAQD to AND Gate, then ANG Gate output to R1 and R2 / QAQD to R1R2.