IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO.
4, APRIL 2011 699
A CMOS Instrumentation Amplifier With 90-dB
CMRR at 2-MHz Using Capacitive Neutralization:
Analysis, Design Considerations, and Implementation
Apisak Worapishet, Senior Member, IEEE, Andreas Demosthenous, Senior Member, IEEE, and
Xiao Liu, Member, IEEE
Abstract—The benefits of using “current feedback” in instru-
mentation amplifier (IA) design are well known. In this paper,
we analyze the mismatch mechanisms, both random and sys-
tematic types, which influence the common-mode rejection ratio
(CMRR) performance of the local current feedback IA topology.
We derive analytical expressions for the common-mode gain fre-
quency response due to random mismatches (transconductance,
drain-source conductance and parasitic capacitance) and verify
the integrity of the analysis through simulation. To address the
systematic mismatch in the drain capacitance of the input pair
transistors, we employ capacitive neutralization and verify its
effectiveness in practice from the fabricated IA chip samples in
a 0.35- m CMOS process technology. The measured average
common-mode gain improvement for the 20 fabricated samples
employing our neutralization technique is about 20 dB at 2 MHz
( 3 dB bandwidth). When taking into account the differential
gain response (33.7 dB), the average CMRR of the neutralized IA
at 2 MHz exceeds 90 dB. The IA occupies an area of 0.068 mm
and dissipates 0.85 mW from a 3-V power supply. The circuit is
intended for a wideband bioimpedance spectroscopy application.
Index Terms—Capacitive neutralization, CMOS, common-mode
gain, component mismatches, high-frequency, high CMRR, instru-
mentation amplifier (IA), local current feedback, medical applica-
tions, wide bandwidth.
I. INTRODUCTION
I NSTRUMENTATION amplifiers (IAs) are very important
circuits in many sensor readout systems where there is
a need to amplify small differential signals in the presence
of large common-mode interference. Application examples
include automotive transducers [1], industrial process control
[2]–[4], linear position sensing [5], and biopotential acquisition
systems [6]–[11]. We have a particular interest in the design
of integrated instrumentation for medical impedance imaging
Manuscript received February 20, 2010; revised June 28, 2010; accepted Au-
gust 17, 2010. Date of publication November 15, 2010; date of current ver-
sion March 30, 2011. This work was supported in part by the UK Engineering
and Physical Research Council (EPSRC) under Grant EP/E029426/1 and Grant
EP/G061629/1, and in part by the British Council Researcher Exchange Pro-
gramme. This paper was recommended by Associate Editor J. S. Chang.
A. Worapishet is with the Mahanakorn Microelectronics Research Centre
and Department of Telecommunication, Mahanakorn University of Technology,
Bangkok 10530, Thailand (e-mail: apisak@mut.ac.th).
A. Demosthenous and X. Liu are with the Department of Electronic and
Electrical Engineering, University College London, Torrington Place, London
WC1E 7JE, U.K. (e-mail: a.demosthenous@ee.ucl.ac.uk; x.liu@ee.ucl.ac.uk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2010.2078850
1549-8328/$26.00 © 2010 IEEE
using bioimpedance measurements [12], [13]. In clinical ap-
plications the use of bioimpedance imaging, also known as
electrical impedance tomography (EIT) [14], offers advantages
over other medical imaging techniques. Unlike computerized
tomography (CT) and X-rays, EIT does not emit ionizing
radiation, and unlike magnetic resonance imagining (MRI),
EIT is silent, highly portable, and inexpensive. EIT works
by reconstructing the differences in electrical conductivity
inside a body. In a typical bioimpedance measurement system,
a differential alternating current is applied through a pair of
surface electrodes to the body tissue and the resulting voltages
are picked up by another electrode pair and amplified for
further processing [15]. The front-end amplifier is required to
have high input impedance to avoid part of the injected current
shunted into the recording electrodes which would cause errors
in the measurement; hence the requirement for an IA.
The main common-mode interference in bioimpedance mea-
surements occurs at the working frequency and is produced by
the current injected into the body to make the measurements
[16]. In the case of EIT, the differential signal measured between
adjustment pair of electrodes can be as small as a few tenths of
a microvolt V whereas the common-mode interference can
be in the hundreds of millivolt (mV) range.
For imaging of cancer biomarkers which is our target appli-
cation, it is necessary to measure bioimpedance over a wide fre-
quency range (10 kHz to 1 MHz) and in multifrequency mode
(bioimpedance spectroscopy). Furthermore, it is required that
the minimum detectable input signal be as low as 20 V. The
need for wide bandwidth (BW) operation dictates that the IA
should have high common-mode rejection ratio (CMRR) at high
frequencies. CMRR is defined as the ratio of the differential gain
over the common-mode gain [17]. To obtain good accuracy in
the measurement, our specification for the IA requires a min-
imum CMRR of 80 dB up to 2 MHz ( 3 dB BW). However, to
the best of our knowledge, neither off-the-shelf monolithic IAs
nor those reported in the literature meet this specification. The
CMRR of high-performance IAs such as the AD8221 [18] is 80
dB only up to about 100 kHz. Although commercial high-speed
differential receiver amplifiers such as the AD8129/AD8130
[19] feature high CMRR at high frequencies, their current con-
sumption is very high ( 10 mA). In addition, we are aiming
for a low-power, fully-integrated, system-on-chip solution for
the targeted bioimpedance spectroscopy system. The design of
a low-power IA with high CMRR at high frequencies is a very
challenging task.
700 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011
There are two basic approaches to the design of an IA: resis-
tive feedback (e.g., 3-opamp topology [11]) and current feed-
back [20]. In the case of resistive feedback, the CMRR is lim-
ited by the degree of matching of the resistors in the feedback
network; only balancing technique is employed. In the case of
current feedback, higher CMRR performance is achieved be-
cause both isolation and balancing techniques are employed. In
addition, the current feedback approach offers a higher oper-
ating BW than resistive feedback [20]. A typical current feed-
back IA consists of a resistive-degenerated input transconductor
(i.e., converter), a resistive-degenerated output transcon-
ductor, and one or more high gain feedback loops. If a single
feedback loop is applied around both transconductors, the IA is
classified as direct [6] or indirect [21] current feedback. In the
direct current feedback IA the two transconductors are stacked
and this limits the input common-mode voltage range and the
minimum supply voltage. If two isolated local feedback loops
are used, one around the input transconductor and one around
the output transconductor, the IA is classified as local current
feedback [22]. Both the direct and indirect current feedback IA
topologies are subjected to a number of parasitic poles associ-
ated with each of the stages around the loop. As a result, this
complicates the frequency compensation and poses a limitation
on high-frequency operation.
On the contrary, in the local current feedback IA topology,
each local loop contains a smaller number of internal parasitic
poles and thus, this topology potentially offers a higher oper-
ating BW for a given current consumption. For these reasons
we have chosen the local current feedback IA topology im-
plemented with a current mirror load (drain load) in the input
transconductor [7]. One advantage of the current mirror load
over the resistor load implementation [22] is insensitivity to the
input offset voltage of the sensing (or loop) amplifier connected
across the input and output nodes of the current mirror load.
In addition, the current mirror load provides a large local loop
gain due to its high-impedance output node. As a result, the
sensing amplifier can be single stage with relatively low gain.
This yields a consequent benefit to stability and high BW op-
eration due to reduction of the parasitic poles around the loop,
hence a simple and power-area efficient implementation. Anal-
ysis of the CMRR performance of the local current feedback IA
has been limited to low-frequencies [23].
In this paper, we analyze the mismatch mechanisms (both
random and systematic types) that influence the CMRR perfor-
mance of the local current feedback IA from low-to-high fre-
quencies and design the circuit to meet the CMRR specifica-
tion of minimum 80 dB up to 2 MHz. To address the system-
atic mismatch in the drain capacitances of the input pair transis-
tors, we use capacitive neutralization and verify its effective-
ness through simulation and measurements from the fabricated
IA chip samples in a 0.35- m CMOS process technology.
The remaining sections of the paper are organized as fol-
lows. Section II presents the common-mode gain frequency re-
sponse analysis of the IA’s input stage for random mismatches
(transconductance, drain-source conductance and parasitic ca-
pacitance) taking into account the dominant poles and zeros of
the common-mode voltage transfers. Analytical expressions for
the feedback current for each mismatch parameter are derived,
Fig. 1. Simplified schematic of the local current feedback IA with current
mirror load in the input transconductor.
yielding the overall common-mode gain response of the IA.
Section III discusses the expressions in terms of their frequency
characteristics and their relative contribution to the overall mis-
match feedback current. Section IV examines the systematic
mismatch in the drain capacitances of the input pair transistors
and proposes the use of capacitive neutralization to mitigate this
imbalance. The IA circuit implementation and design consider-
ations are detailed in Section V. Simulated and measured re-
sults are presented in Section VI, followed by conclusions in
Section VII.
II. IA COMMON-MODE GAIN RESPONSE ANALYSIS
Fig. 1 shows the simplified circuit schematic of the local cur-
rent feedback IA [7], [22]. The input transconductor stage uses
a simple current mirror load (drain network) and current source
biasing (source network). The sensing amplifier serves to ex-
actly balance the drain currents of transistors and by
adjusting the complementary currents and . A direct result
of this is that the input differential voltage is forced across re-
sistor and hence and of the input stage essentially
acts as a unity-gain buffer. Similarly, the high gain amplifier
balances the drain currents of transistors and in the
output transconductor stage. Since currents and are exact
copies of and , respectively, the output voltage appears
across resistor . Hence, the dc gain of the IA is given by the
ratio . Placing a capacitor in parallel with resistor
creates a dominant pole, which sets the 3 dB BW of the IA.
A. Analysis Formulation
The common-mode gain characteristics of the IA due to
random mismatches can be analyzed by focusing only on the
input stage. This is because the mismatch effects of the sensing
amplifier and the output transcondutance stage are greatly
suppressed by the high gain of the local feedback loops. Fig. 2
shows the small-signal model of the IA’s input stage where it is
assumed that the output conductances of are much less
than their corresponding transconductances. The voltages at the
drain terminals, and , are sensed by the amplifier which
drives the differential feedback current . The feedback path
is via the source terminals and . In the figure, and
WORAPISHET et al.: A CMOS INSTRUMENTATION AMPLIFIER WITH 90-dB CMRR AT 2-MHz 701

the relative mismatch between the drain capacitance of the

Fig. 2. IA input stage model for common-mode gain analysis.
are respectively the transconductances and drain-source
conductances of the input transistors and . are
the transconductances of the drain transistors and . b)
are the output conductances of the current sources and
. All parasitic capacitances are included to allow a study of the
high-frequency mismatch characteristics. and are
respectively the gate-source and gate-drain capacitances of the
input transistors and , and and are respec-
tively the total capacitances of the source and drain terminals,
including those from the input and load/source transistors as well
as the amplifier stages that are connected to the terminals. To
facilitate the analysis and description, the resistors in the model,
except , are expressed by the conductance parameters.
In order to systematize the common-mode analysis, we have
chosen to introduce mismatches via the following definitions:
drain network. The signs for each of the mismatch parameters
defined above result in cumulative contributions.
A set of equations governing the common-mode gain char-
acteristics of the IA can be formulated by first applying KCL at
the drain and source terminals of the input stage. Next, to obtain
the equations for the common-mode signal responses, we take
the sum between the drain equations at and , and between
the source equations at and . Similarly, to obtain the equa-
tion for the differential-mode signal response, we take the dif-
ference between the drain equations at and , and between
the source equations at and . These sum and difference
equations of the KCL node equations enable us to understand
the underlying mechanism that leads to a finite common-mode
gain due to component mismatches. In particular, the sum equa-
tions will be employed to determine the common-mode voltages
of the IA. If there are mismatches, the common-mode voltages
will give rise to differential current injections into the circuit.
Subsequently, the difference equations will be employed to de-
termine the circuit response, and hence the finite common-mode
gain of the IA can be computed. In order to simplify the anal-
ysis, the following approximations are applied to those sum and
difference equations:
a)
c)
d)
e)
f) .
With reference to Fig. 2, are the transconductances of
transistors. and are respectively the conductances
and the capacitances associated with terminals. Note that the
symbols , , and represent the nominal value of their
corresponding parameters. Also, and are respectively
the common-mode voltages and their nominal voltage. is
the relative mismatch of the parameter under consideration.
Consequently, the equations governing the common-mode
signals, and , of the
input stage are given by

(1)

(2)
and those governing the differential-mode signals,
, and the feedback current , are given by
(3) and (4)
where the symbols , , , , , , and
represent the nominal value of their corresponding param-
eters. With reference to Fig. 2, , , , and
respectively represent the relative mismatches between the
transconductance, drain-source conductance, gate-source ca-
pacitance, and gate-drain capacitance of the input transistors
and . Also, and are the relative mismatches
between the output conductance and capacitance of the source (3)
network, represents the relative mismatch between the
transconductance of the current mirror transistors, and is
702 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011

(4)

The common-mode gain characteristics of the IA are also de-

pendent upon the sensing condition of amplifier in Fig. 2. For
a balanced sensing scheme, the amplifier is of a differential
type where its input terminals sense the voltage difference be-
tween the drain terminals of the input transistors. Typically, the
sensing amplifier together with the high impedance at the output
of the drain active load provide a high differential loop gain
within the operating BW, whereas the common-mode loop gain
is small ( 1). Following this, we have , i.e.,
a differential-mode virtual ground condition. Note that to in-
clude the offset voltage of the sensing amplifier, the relation can
be modified to where represents a constant offset
voltage. It is also possible for an unbalanced or single-ended
sensing at the drain terminals of the input transistors. However,
this scheme leads to systematic common-mode gain responses
hence it is not of practical and analysis interest.

B. Qualitative Description of the Common-Mode Responses

To seek a qualitative insight from the set of equations in (1)

to (4), we start by showing the common-mode and differential-
mode equivalent half circuits of the IA’s input stage. These are
described by the common-mode equations in (1) and (2), and
the differential-mode equations in (3) and (4), and are shown
in Fig. 3(a) and 3(b), respectively. By virtue of superposition
between the common-mode and differential signal responses,
we can deduce the mechanism that gives rise to finite common-
mode gain responses due to component mismatches in the IA.
Consider the common-mode half circuit of Fig. 3(a). Upon
the presence of the common-mode input , the common-mode
voltages and are deviated from the quiescent operating
points, and these can be determined from (1) and (2). As a con-
sequence, the incremental common-mode voltages produce in-
cremental common-mode currents through the admittances of
the resistive and capacitive circuit components.
If mismatches exist, the incremental common-mode currents
between each pair of components will be slightly different,
yielding nonzero differential current sources , ,
, , , , , and in the differential-mode
half circuit of Fig. 3(b), as defined in (3) and (4). This im-
plies that the differential mismatch currents will follow the
frequency characteristics of the common-mode voltages and
their developed or controlled admittances. These mismatch
current sources in the differential circuit of Fig. 3(b) produce
the differential voltages and , as well as the differential
currents, particularly the feedback current as a result of the
high gain negative feedback mechanism for differential signals
at the input stage. By using (3) and (4), , and can be
determined. The mismatch current is also fed to the output
Fig. 3. (a) Common-mode equivalent half circuit. (b) Differential-mode equiv-
alent half circuit (capacitance omitted).
transconductor stage, yielding a finite output voltage and
hence a finite common-mode gain in the IA.
C. Derivation of Analytical Common-Mode Responses
Upon solving (1) and (2), it can be shown that with the dom-
inant pole/zero approximation [24], the common-mode drain
and source voltages, and , as well as the common-mode
gate-source and gate-drain voltages, and , all exhibit an
-domain transfer characteristic of the form
(5)
where and respectively represents the dominant zero and
pole, and is the dc gain. Since the common-mode voltages
share identical pole locations, by solving (1) and (2) and ap-
plying (5), the dominant pole magnitude is derived as given
in Table I. By following the same procedure, the dominant zero
magnitude for each common-mode voltage is derived and
these are also given in Table I.
Further approximation of the voltage characteristics can
be obtained by recognizing that it is typical for an IA to
have the overall BW set by one single dominant pole. For
the local current feedback IA of Fig. 1, this is set by the
time constant at the output transconductor stage, where
WORAPISHET et al.: A CMOS INSTRUMENTATION AMPLIFIER WITH 90-dB CMRR AT 2-MHz 703

TABLE I
DC GAIN AND DOMINANT ZERO AND POLE MAGNITUDES OF COMMON-MODE VOLTAGE TRANSFERS

TABLE II TABLE III

EXTRACTED SMALL-SIGNAL CIRCUIT PARAMETERS OF THE DESIGNED IA CALCULATED DC GAIN AND POLE/ZERO MAGNITUDES OF COMMON-MODE
VOLTAGES

poles/zeros associated with the differential-mode circuit are at

frequencies beyond the BW of the IA and can be neglected.
This is justified by the fact that the degeneration resistance
in the differential-mode circuit is much smaller than the
the should be somewhat less than the inversed conductances and , which determine
pole frequency (in Hz) in Table I. Thus, for the the dominant pole of the common-mode voltages. Solving (3)
analysis within the BW of the IA, the pole associated with the and (4) and applying the condition , , the
common-mode voltages can be omitted. approximated closed-form expressions of the current transfer
From Table I we observe that the transconductances and with , are summarized in Table IV for
are associated with the zero magnitude of the source each mismatch parameter. Note from Table IV that the effect
voltage , gate-drain voltage , and drain-source voltage associated with the offset voltage of the sensing amplifier is
, similar to the expression. As a result, these zeros suppressed by the factor due to the use of a current
should be located beyond the BW of the IA and can also be mirror as the drain load. The common-mode gain frequency
omitted. On the other hand, the much smaller conductances response of the IA for each mismatch parameter in Table IV
and are associated with the zeros of the drain voltage is obtained by
and gate-source voltage . Consequently, the dominant zeros
of and tend to be located at frequencies below the BW (6)
of the IA and hence, must be included in the analysis. Using
the extracted small-signal circuit parameters of the designed The sum of all these common-mode gain frequency responses
IA (see Section V) in Table II and the analytical expressions yields the overall common-mode gain frequency response of
in Table I, the calculated magnitudes (in Hz) of and the IA.
are given in Table III. When compared with the 3 dB corner
frequency (2 MHz) of the IA, the locations of the zeros follow
the discussion above, thus validating the approximation. III. DISCUSSION OF THE ANALYTICAL EXPRESSIONS
Based upon the above pole/zero approximations of the
common-mode voltages, the mismatch current sources in the A. Frequency Characteristics
differential-mode half circuit of Fig. 3(b) can be determined. For frequencies well below the zero frequencies of
Then, the voltages , and the feedback current the common-mode voltages and , the current transfers
can be derived. In this case, we can further assume that the in Table IV due to the (trans)conductance mismatches ,
704 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011

TABLE IV B. Relative Contribution of Mismatch Currents

APPROXIMATED FEEDBACK CURRENT TRANSFERS DUE TO MISMATCHES AND
OFFSET VOLTAGE Let us now investigate the relative contribution to the overall
mismatch current for each of the mismatch components. This
can be of great importance when designing and optimizing the
IA for a high CMRR at high frequencies. Only the effect of
random mismatches is considered in this section. The systematic
mismatch will be discussed in Section IV.
We base our observations again on the expressions in Table IV,
noting the underlying mechanism that the mismatch currents are
dependent upon the admittances and their developing or con-
trolling common-mode voltages. This implies that the mismatch
current will be larger if the admittance and/or the common-mode
voltage are higher, and vice versa. Another parameter that must
be considered is the multiplying factor associated
with the mismatch currents that produce nonzero differential
voltages in the differential-mode half circuit of Fig. 3(b), par-
ticularly the source voltage , when flowing to the source
feedback terminals. This will produce additional current flowing
through the degeneration resistor which further increases
the mismatch current, yielding the factor . Since
is typically small to allow a large differential gain and low noise
in the IA, the factor can be somewhat larger than unity. This
can greatly enlarge the overall random common-mode gain of
, , and remain constant, following the characteris- the IA, and must be taken into consideration in the design.
tics of the common-mode voltages and the (trans)conductances At low frequencies, the mismatch currents due to the
that are practically constant over the range. Over the same (trans)conductances dominate since the admittances of the capac-
frequency range, the current transfers due to the capacitance itance mismatches are comparatively negligible. By considering
mismatches , , , and , exhibit linear frequency the relative values between the (trans)conductances , ,
dependency, following the characteristics of capacitive admit- and , and their developing or controlling voltages from the
tances which increase linearly with frequency. transfer responses in Table I, as well as the factor
As we approach the zero frequencies of the common- associated with their mismatch expressions in Table IV, we
mode voltages and , which are located below the BW may deduce that the mismatch components , and
of the IA (see Table III), their voltage magnitudes start to dominate at low frequencies, where their relative contributions
rise linearly with frequency. Because and control the depend upon the actual values chosen for a target design.
transconductances and , respectively, the current trans- The above discussion and the expressions in Table IV also
fers due to and start to exhibit linear frequency indicate suppression of the (trans)conductance mismatch cur-
dependency. Similarly, because and develop across rents by the drain-source conductance of the input transis-
and , the current transfers due to and start to tors, and/or the output conductance of the current source. This
exhibit quadratic frequency dependency. However, the current typifies the isolation characteristic of the current feedback IA,
transfers due to the conductance mismatches , , and where small and are generally recognized to provide im-
the capacitance mismatches , , remain similar to their provement on the low-frequency CMRR performance.
corresponding low-frequency characteristics. This is because As frequency increases, the capacitance mismatch currents
the characteristic zeros of their developing voltages ( , , or increase and their effect are no longer negligible. Again, by con-
) are located well beyond the BW of the IA (see Table III) sidering the relative values between the capacitances , ,
and thus, the voltage magnitudes remain practically constant. and , and their developing or controlling voltages from the
Another important indication from the analytical expressions transfer responses in Table I, as well as the factor as-
in Table IV is the fact that, at high frequencies approaching the sociated with their mismatch expressions in Table IV, it follows
BW of the IA, all the capacitive mismatch currents are indepen- that, given the same mismatch error, the mismatch is dom-
dent of the output conductance of the current source. This inant. It should be noted that even though the high-frequency
is remarkably opposite to the low-frequency common-mode characteristics of the mismatch currents due to and be-
responses where should be low to enable large suppression come quadratically-dependent as described in Section III-A and
of the mismatch errors. This implies a possible omission of the Table VI, this appears quite close to the BW of the IA. As a re-
cascode transistor arrangement in the feedback current source. sult, the effect is quickly attenuated and the contributions from
As a result, potential benefits in terms of BW and stability and to the overall mismatch current are still relatively
due to fewer nondominant poles around the feedback loop small.
can be gained. Other benefits include supply voltage reduction Another important effect that requires attention at high
and larger output swing due to a smaller voltage headroom frequencies is the characteristic zeros in the voltage transfers
requirement. and . As a consequence, the mismatch currents
WORAPISHET et al.: A CMOS INSTRUMENTATION AMPLIFIER WITH 90-dB CMRR AT 2-MHz 705

Fig. 4. Schematic diagram of the IA using neutralization capacitor to balance the drain capacitances of the input pair transistors.

due to and become linearly dependent against A simple means to suppress this adverse effect is to insert a
frequency. Similar to what was described before, however, the neutralization capacitor at the terminal of the current mirror
effect is quickly suppressed since the zeros are located near the load, to reduce the parameter in (9) by balancing the capaci-
BW of the IA. tances and . To allow good tracking against process and
temperature variations, the neutralization capacitor is im-
IV. SYSTEMATIC MISMATCH AND CAPACITIVE plemented by the gate capacitance of a MOS transistor in non-
NEUTRALIZATION saturation operation as shown in Fig. 4, since this is of a sim-
Upon examining the IA schematic of Fig. 1, we note that there ilar type as at the terminal . Assuming the MOS total
exists a systematic mismatch in the drain capacitances and gate capacitance under nonsaturation operation is
(see small-signal circuit in Fig. 2) due to the inherent asym- , and the MOS gate-source capacitance under saturation
metrical topology of the current mirror load ( and ). operation is , it can be shown that, for the
With reference to the circuit in Fig. 1, the expressions for the same length as the current mirror transistors, the width
total drain capacitance are given by of the neutralization MOS capacitor is given by

(7) (10)
(8) where is the width of the current mirror transistors.
With the use of the capacitive neutralization to suppress the
where is the total common-mode capacitance at the input
systematic mismatch, the high-frequency CMRR can be dra-
of the differential sensing amplifier , and are the
matically improved, practically at no cost to other performance.
gate-source capacitances of the drain transistors. Also,
However, this improvement is limited by both the random mis-
and are respectively the drain-bulk capacitances of the
match and the inherent asymmetrical circuit configuration of
input transistors and the drain transistors. By assuming perfect
the drain active load in the IA. As indicated by the developed
matching of components, i.e., and
expression in Table IV for , one may increase the product
, the mismatch
and/or the transconductance in order to further sup-
parameter is given by
press the parameter . This can be obtained by trading off
power consumption for a larger or , and/or trading off
(9)
noise for a larger , etc. Note however that, with reference to
Fig. 9 (see Section VI-A) the effect of even with 5% residual
mismatch gives a lower common-mode gain compared to the
Since the gate-source capacitance at the drain termi- sum of the other capacitance mismatches, each with 1% error.
nals typically constitutes a large proportion of the effective drain This relative contribution thus should be carefully taken into ac-
capacitance , the mismatch parameter can be consid- count in the tradeoff.
erably larger than the case with only the random mismatches. It should be noted that the capacitive neutralization in this
Hence, the effect of the systematic drain capacitance mismatch work is entirely different from the neutralizing capacitor tech-
can dominate the common-mode gain response of the IA at high nique for wideband amplifiers under a differential signal excita-
frequencies. tion in [25] and [26], which makes use of the bridge capacitors
706 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011
TABLE V
IA TRANSISTOR DIMENSIONS
scheme to compensate for the input/output parasitic coupling
capacitance in the transistors.
Although one may employ the dynamic element matching
(DEM) to suppress the mismatch [27], it typically requires a
high clock frequency beyond the BW of the IA. Another point
worth discussing is the fact that the systematic mismatch
arises from the use of a current mirror as the drain load. An
obvious means to avoid such mismatch is to change the load
to a current source type. However, this would require addi-
tional circuit complexity and power consumption, because a
common-mode feedback circuitry would be necessary for set-
ting up the dc drain voltages. Hence, the current mirror load
equipped with the neutralization capacitance is a more ef-
ficient solution in terms of simplicity, compactness and low
power requirement. The effectiveness of the neutralization tech-
nique will be demonstrated in Section VI.
V. CIRCUIT IMPLEMENTATION
An IA using the local current feedback topology in Fig. 1 but
with pMOS input transistors (to eliminate the body effect in the
input pair transistors) was designed, simulated and fabricated
using the 0.35- m austriamicrosystems CMOS process tech-
nology [28] for a differential gain of 50 V/V (set by
), 3 dB BW of 2 MHz, and 3 V supply voltage
operation. The bulk terminal of each nMOS transistor was con-
nected to the negative supply (0 V) while that of each pMOS
transistor was connected to its source terminal (n-well tech-
nology). The simulations and layout were carried out in Ca-
dence Analog Environment using the design kit provided by the
foundry.
The full schematic of the designed IA is shown in Fig. 4 and
its transistor dimensions are listed in Table V. The sensing am-
plifier in the first stage was implemented by a simple transcon-
ductor ( A, ) whose output currents are
copied to the input and output transconductor stages. Although
the use of cascoding can reduce the capacitances and the
conductances at the source terminals, for our specific IA
design, their relative impact on the CMRR is negligible as sug-
gested later in Figs. 6 to 8 (see Section VI-A). For this reason
together with the high BW requirement, no cascode transis-
tors were used for the feedback current sources ( and
to ease the design at high frequencies with no impact on the
high-frequency CMRR performance as indicated by the anal-
ysis. The output stage merges the transconductor and sensing
Fig. 5. A microphotograph of the fabricated chip with four versions of the IA.
From left: using fixed nMOS neutralization capacitor, using nMOS variable neu-
tralization capacitor, using pMOS variable neutralization capacitor, and nonneu-
tralized. The chip was designed and tested at University College London.
amplifier into a single circuit, realized by a symmetrical CMOS
transconductance operational amplifier with cascode transistors
for high loop gain and high BW operation. The cascode tran-
sistor pairs , and , are biased by the external
dc voltage sources (1.2 V) and (1.8 V), respec-
tively. The dc level of the output voltage is set by the ex-
ternal voltage source (1 V). To allow testing at high fre-
quencies, an on-chip 5 V pMOS source follower (not shown)
with an output impedance of about 50 succeeds the IA. The
source follower does not affect the CMRR of the IA.
The IA’s input stage dictates noise performance. Since the
BW of the IA extends to high frequencies (2 MHz), thermal
noise dominates over flicker noise. Hence, using only the
thermal noise contribution, the input-referred voltage noise of
the IA can be calculated as
(11)
where is Boltzmann’s constant, is the absolute temperature,
and is the BW in Hz over which the noise is measured. To
minimize the thermal noise contribution of resistor , its re-
sistance must be set to a small value (here 400 ). Biasing the
input stage transistors with a quiescent drain current of 37.5 A,
to obtain a total input integrated noise in the referred BW (i.e.,
MHz) of less than 20 V (rms), we ended up with the
transistor dimensions in Table V for and (the di-
mensions were fine tuned in Cadence) and with their extracted
trans(conductance) and parasitic capacitance values in Table II.
The sizing of the transistors in Table V was chosen to be rel-
atively large for layout matching purposes (especially the non-
minimum length).
For good linearity, the maximum differential input signal
range should be restricted to the value of the product
(here 30 mV) where is the quiescent drain current of the
input stage current source transistors and (see Fig. 4).
Increasing the input signal much beyond this limit, would result
) in appreciable output harmonic distortion.
The chip microphotograph is shown in Fig. 5. The layout
employed common-centroid and interdigitation for matched de-
vices. The layout area of the IA including routing and the output
WORAPISHET et al.: A CMOS INSTRUMENTATION AMPLIFIER WITH 90-dB CMRR AT 2-MHz 707

Fig. 6. Simulated (point lines) versus theoretical (solid lines) common-mode Fig. 7. Simulated (point lines) versus theoretical (solid lines) common-mode
gain responses due to transconductance and conductance gain responses due to the capacitive mismatches and . The mismatch
mismatches. The mismatch parameters were set to 1%. parameters and were set to 1%.

buffer is 0.068 mm (the pMOS follower occupies 0.022 mm ).

Four versions of the IA were implemented on chip (see Fig. 5)
with identical component parameters and layouts. The only dif-
ference is the addition of the neutralization capacitor in
three of the IAs for suppression of the systematic drain capac-
itance mismatch of the input pair transistors (see Fig. 4). One
IA used a grounded fixed nMOS capacitor, one used a variable
nMOS capacitor, and the other used a variable pMOS capac-
itor, each with their drain and source terminals shorted. These
MOS capacitors used the same length as the nMOS transis-
tors and in the current mirror load. The width
of the fixed capacitor was initially selected in accordance with
(10), and subsequently refined with the help of postlayout sim-
ulation. The variable MOS capacitors used a width of 30 m
and a length of 5 m; the capacitance value could be altered by
varying the voltage applied to the shorted drain-source terminal Fig. 8. Simulated (point lines) versus theoretical (solid lines) common-mode
[29]. The purpose of the variable capacitors was to investigate gain responses due to the capacitive mismatches and . The mismatch
the effect of the neutralization capacitance value on the overall parameters and were set to 1%. Both capacitive mismatches are plotted
at two different values of the current source output conductance: and .
common-mode gain of the IA. In total 20 chips were fabricated
and tested with all samples working.
the simulated responses for the capacitance mismatches for 1%
mismatch. Also shown in the same plots are the theoretical
VI. SIMULATED AND MEASURED VERIFICATIONS common-mode gain responses based on the current expressions
in Table IV and using (6). As seen from these plots, the simu-
A. Simulated Versus Theoretical Characteristics
lated and theoretical common-mode gain characteristics are in
We first consider the case when the IA is equipped with the good agreement up to frequencies beyond the BW (2 MHz) of
neutralization technique. The small-signal circuit parameters the IA. This validates all the approximations taken to simplify
of the neutralized IA’s input stage were extracted as listed in the analysis in Section II and the accuracy of the analysis. As
Table II for verification of the theoretical derivations. To enable the frequency approaches the 10 MHz region, there are discrep-
investigation of each of the mismatch effects via simulation, ancies. This is primarily due to the effects of the nondominant
deterministic mismatches were included in the transistor-level poles/zeros neglected in the analysis.
schematic to set the trans(conductance) and capacitance mis- Furthermore, in order to verify that at high frequencies the
matches (i.e., the factors ) in the circuit parameters in Table II. common-mode gain responses due to the capacitive mismatches
Moreover, to avoid interfering with the operating conditions of and , are insensitive to the current source output conduc-
the IA, these were set up by adding resistors, capacitors, and tance , the gain responses were also simulated with a 10 times
independent current sources. smaller (modified with the use of ideal negative resistors). As
Fig. 6 shows the simulated common-mode gain responses seen in Fig. 8, at high frequencies, a smaller has negligible
versus frequency for the (trans)conductance mismatches for impact on the common-mode gain responses due to the and
1% mismatch (i.e., ). Similarly, Figs. 7 and 8 show mismatches. However, at low-to-intermediate frequencies,
708 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011
Fig. 9. Simulated (point lines) versus theoretical (solid lines) common-mode
gain responses due to capacitance mismatches. Shown is the response for the
systematic drain capacitance mismatch, compared to the response of
for 1% mismatch . Also shown is
the response for a 5% deviation in the neutralization capacitance from its
optimum value.
a smaller helps to suppress the common-mode gains due to
the and mismatches. At frequencies near the BW of the
IA, the responses converge to the cases with larger . This con-
forms to the discussion of the analysis in Section III-A.
We now turn to the nonneutralized IA. Based on the parame-
ters in Table II, the systematic drain capacitance mismatch due
to the asymmetrical circuit topology at the current mirror load
of the IA was calculated as . Fig. 9 shows the simu-
lated and theoretical common-mode gain responses for the sys-
tematic drain capacitance mismatch only, in comparison with
the sum of the common-mode gain responses due to the rest of
the capacitance mismatches (i.e., ) for 1% mis-
match (i.e., ). As seen from the
plot, the theoretical and simulated responses match well, thus
confirming the integrity of the analysis. Also indicated from the
plot is that the effect of the systematic drain mismatch by far
dominates the overall common-mode gain response of the IA,
particularly at high frequencies. When compared to a practical
case, with say 5% deviation in the capacitance from the op-
timum neutralization value, we can see in Fig. 9 that the simu-
lated common-mode gain response due to the drain capacitance
mismatch can still be kept as low as 60 dB even at frequencies
beyond the BW of the IA.
B. Measured Characteristics
For the common-mode measurements, a signal generator
(Agilent 33250A) was used to apply a 0.8-V peak-peak si-
nusoid signal with a dc offset of 1.4 V to the IA inputs, and
the residual IA output voltage was monitored on a spectrum
analyzer (Agilent E4411B) over the frequency range 100 kHz
to 10 MHz. Shown in Fig. 10 are the measured common-mode
gain responses of the nonneutralized IA and the fixed-capacitor
neutralized IA, taken from the average measurements of all
20 chips. The spread of the common-mode gain between all
20 samples featuring the fixed neutralization capacitor was
measured to be within 10 dB of the average value.
Fig. 10. Measured and Monte Carlo simulated average common-mode gain
responses for the nonneutralized and fixed-capacitor neutralized IA designs.
Let us now consider the high-frequency measured character-
istics in the vicinity of the IA’s BW at 2 MHz. Without neutral-
ization, the common-mode gain response in Fig. 10 increases
at a rate approaching 12 dB/octave from about 500 kHz up
to 5 MHz, beyond which the slope gradually drops and the gain
eventually begins to fall as a result of the limited IA BW. On the
other hand, with the neutralization capacitor the common-mode
gain response stays relatively constant over the frequency range
up to 10 MHz. The average common-mode gain improvement
at 2 MHz and 10 MHz is about 20 dB and 22 dB, respectively.
The improvement in the common-mode gain response of the
IA at high frequencies due to the fixed neutralization capacitor,
is also demonstrated by the postlayout Monte Carlo simulations
(taken from the average of 250 runs) shown in Fig. 10. The sim-
ulated and measured characteristics follow a very similar trend
(the difference is attributed to layout matching limitations). This
confirms the effectiveness and robustness against process vari-
ation of the drain neutralization technique in suppressing the
systematic drain capacitance mismatch. In addition, the fact that
the common-mode gain response of the neutralized IA is quite
flat against frequencies implies that, in these specific IA de-
signs, other random capacitance mismatches are negligible and
the systematic drain mismatch is the dominant factor in deter-
mining the high-frequency common-mode gain response. This
is in line with the theoretical discussion and simulation above.
To further support this claim, the effect of the neutralizing
capacitance value on the common-mode gain of the IA was ex-
amined using the variable capacitor designs. Fig. 11 shows the
measured common-mode gain at 2 MHz for a typical IA sample
using the nMOS variable neutralization capacitor. By varying
the dc bias voltage applied to the drain-source ter-
minal of the variable capacitor, the capacitance value could be
altered between about 100 fF and 650 fF. As seen in Fig. 11,
the common-mode voltage gain of the IA changes as
is swept, and a minimum value is reached corresponding to the
optimum neutralization capacitance value. All 20 samples ex-
hibited this type of minimum common-mode gain behavior for
a specific value (the spread of the value for
the minimum is about 20 mV between all 20 samples). Similar
WORAPISHET et al.: A CMOS INSTRUMENTATION AMPLIFIER WITH 90-dB CMRR AT 2-MHz
Fig. 11. Measured common-mode response at 2 MHz for a typical IA sample
against the bias voltage applied to the nMOS variable neutralization
capacitor. By varying the neutralization capacitance value is altered.
The minimum value in the common-mode gain corresponds to the optimum
neutralization capacitance value.
Fig. 12. Measured differential voltage gain and CMRR versus frequency for
the fixed-capacitor neutralized IA. The error bars indicate the maximum spread
from all chips.
behavior was observed for the IA samples using the variable
pMOS capacitor.
The measured differential voltage gain of a typical IA chip
sample is shown in Fig. 12. It should be noted that the capaci-
tance neutralization does not affect the differential gain. From
the plot, the dc gain is 33.7 dB (the deviation between all sam-
ples is less than 2%) and the 3 dB BW is about 2 MHz. Also
shown in Fig. 12 is the CMRR of the fixed-capacitor neutralized
IA using the measured common-mode gain data in Fig. 10. The
CMRR plot in Fig. 12 is representative of typical chip perfor-
mance. The error bars in the plot indicate the maximum spread
from all 20 chips. As seen in the figure, at 2 MHz the average
CMRR of the neutralized IA is about 91 dB. At this frequency,
the lowest and highest CMRR from all samples are 83 dB and
101 dB, respectively.
The measured results of the neutralized IA are summarized in
Table VI and these are in good agreement with the specification.
709
TABLE VI
SUMMARY OF THE IA MEASURED PERFORMANCE AND SPECIFICATION
VII. CONCLUSIONS
We have presented a detailed analysis on the common-mode
gain frequency responses of the local feedback IA topology due
to mismatches in the transconductance, drain-source conduc-
tance and parasitic capacitance parameters in the input stage,
from low-to-high frequencies (up to about 10 MHz). The in-
tegrity of the analytical expressions for the random mismatches
has been verified through simulation. In addition, we have iden-
tified that the systematic mismatch at the drain capacitance of
the IA with the current mirror load is the major contribution to
a low CMRR at high frequencies. To mitigate this effect, we
have used capacitive neutralization and demonstrated its effec-
tiveness from the fabricated CMOS IA chip samples, achieving
an average CMRR in excess of 90 dB up to the circuit’s 2 MHz
BW. To our knowledge, this represents the best high-frequency
CMRR performance ever reported for a CMOS IA with low cur-
rent consumption. An integrated wideband bioimpedance spec-
troscopy system using the described neutralized IA is currently
being developed.
ACKNOWLEDGMENT
The authors would like to thank Peter Langlois for his sug-
gestions and help during the testing of the chips.
REFERENCES
[1] B. D. Miller and R. L. Sample, “Instrumentation amplifier IC designed
for oxygen sensor interface requirements,” IEEE J. Solid-State Cir-
cuits, vol. 16, no. 6, pp. 677–681, Dec. 1981.
[2] V. Schaffer, M. F. Snoeij, M. V. Ivanov, and D. T. Trifonov, “A 36 V
programmable instrumentation amplifier with sub-20 V offset and a
CMRR in excess of 120 dB at all gain settings,” IEEE J. Solid-State
Circuits, vol. 44, no. 7, pp. 2036–2046, Jul. 2009.
[3] J.-M. Redouté and M. Steyaert, “An instrumentation amplifier input
circuit with a high immunity to EMI,” in Proc. 2008 Int. Symp. Elec-
tromagn. Compatibility—EMC Eur., Hamburg, Germany, Sep. 2008,
pp. 1–6.
710 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 4, APRIL 2011
[4] J. F. Witte, J. H. Huijsing, and K. A. A. Makinwa, “A current-feed-
back instrumentation amplifier with 5 V offset for bidirectional high-
side current-sensing,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
2769–2775, Dec. 2008.
[5] M. Rahal and A. Demosthenous, “A synchronous chopping demod-
ulator and implementation for high-frequency inductive position sen-
sors,” IEEE Trans. Instrum. Meas., vol. 58, no. 10, pp. 3693–3701, Oct.
2009.
[6] M. S. J. Steyaert, W. M. C. Sansen, and C. Zhongyuan, “A micropower
low-noise monolithic instrumentation amplifier for medical purposes,”
IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 1163–1168, Dec.
1987.
[7] R. Martins, S. Selberherr, and F. A. Vaz, “A CMOS IC for portable
EEG acquisition systems,” IEEE Trans. Instrum. Meas., vol. 47, no. 5,
pp. 1191–1196, Oct. 1998.
[8] C.-J. Yen, W.-Y. Chung, and M. C. Chi, “Micro-power low-offset in-
strumentation amplifier IC design for biomedical system applications,”
IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 4, pp. 691–699,
Apr. 2004.
[9] K. A. Ng and P. K. Chan, “A CMOS analog front-end IC for portable
EEG/ECG monitoring applications,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 52, no. 11, pp. 2335–2347, Nov. 2005.
[10] R. F. Yazicioglu, P. Merken, R. Puers, and C. V. Hoof, “A 60 W 60
nV Hz readout front-end for portable biopotential acquisition sys-
tems,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1100–1110, May
2007.
[11] C.-C. Wang, C.-C. Huang, J.-S. Liou, Y.-J. Ciou, I-Y. Huang, C.-P.
Li, Y.-C. Lee, and W.-J.Wu, “A mini-invasive long-term bladder urine
pressure measurement ASIC and system,” IEEE Trans. Biomed. Cir-
cuits Syst., vol. 2, no. 1, pp. 44–49, Mar. 2008.
[12] H. Hong, M. Rahal, A. Demosthenous, and R. Bayford, “Comparison
of a new integrated current source with the modified Howland circuit
for EIT applications,” Physiol. Meas., vol. 30, no. 10, pp. 999–1007,
Oct. 2009.
[13] M. Rahal, A. Demosthenous, and R. Bayford, “An integrated common-
mode feedback topology for multi-frequency bioimpedance imaging,”
in Proc. 35th Eur. Solid-State Circuits Conf. (ESSCIRC’09), Athens,
Greece, pp. 416–419.
[14] R. Bayford, “Bioimpedance tomography (electrical impedance tomog-
raphy),” Annu. Rev. Biomed. Eng., vol. 8, pp. 63–91, Aug. 2006.
[15] S. Grimns and Ø. G. Martinsen, Bioimpedance & Bioelectricity Ba-
sics. London, U.K.: Academic, 2000.
[16] J. Rosell and R. Riu, “Common-mode feedback in electrical impedance
tomography,” Clin. Phys. Physiol. Meas., vol. 13, pp. 11–14, 1992.
[17] J. Zhou and J. Liu, “On the measurement of common-mode rejection
ratio,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 1, pp.
49–53, Jan. 2005.
[18] AD8221 Data Sheet Analog Devices Inc. Norwood, MA, 2007.
[19] AD8129/AD8130 Data Sheet Analog Devices Inc. Norwood, MA,
2007.
[20] Analogue IC Design: The Current-Mode Approach, C. Toumazou, F. J.
Lidgey, and D. G. Haigh, Eds. London, U.K.: Peter Peregrinus Ltd.,
1990, ch. 16, pp. 569–595.
[21] B. J. van den Dool and J. H. Huijsing, “Indirect current feedback instru-
mentation amplifier with a common-mode input range that includes the
negative rail,” IEEE J. Solid-State Circuits, vol. 28, no. 7, pp. 743–749,
Jul. 1993.
[22] A. P. Brokaw and M. P. Timko, “An improved monolithic instrumen-
tation amplifier,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, pp.
417–423, Dec. 1975.
[23] R. F. Yazicioglu, P. Merken, and C. Van Hoof, “Effect of electrode
offset on the CMRR of the current balancing instrumentation ampli-
fiers,” in Proc. IEEE PRIME’05, Leuven, Belgium, vol. 1, pp. 35–38.
[24] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits, 4th ed. Hoboken, NJ: Wiley,
2002, ch. 9.
[25] J. A. Mataya, G. W. Haines, and S. B. Marshall, “IF amplifier using
-compensated transistors,” IEEE J. Solid-State Circuits, vol. 3, no.
SC-12, pp. 401–407, Dec. 1968.
[26] A. B. Grebene, Bipolar and MOS Analog Integrated Circuit Design.
New York: Wiley, 1983, pp. 415–417.
[27] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects
of op-amp imperfections: Auto-zeroing, correlated double sampling,
and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614,
Nov. 1996.
[28] C35 CMOS Process Technology Austriamicrosystems AG, Austria
[Online]. Available: http://asic.austriamicrosystems.com
[29] T. Tille, J. Sauerbrey, M. Mauthe, and D. S.-Landsiedel, “Design of
low-voltage MOSFET-only modulators in standard digital CMOS
technology,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1,
pp. 96–109, Jan. 2004.
Apisak Worapishet (M’00–SM’10) received
the B.Eng. degree (first-class honors) from King
Mongkut’s Institute of Technology, Ladkrabang,
Bangkok, Thailand, in 1990 and the M.Eng.Sc.
degree from the University of New South Wales,
Australia, in 1995, both in electrical engineering,
and the Ph.D. degree in electrical engineering from
Imperial College, London, U.K., in 2000.
Since 1990, he has been with Mahanakorn Uni-
versity of Technology, Bangkok, Thailand, where
he currently serves as the director of Mahanakorn
Microelectronics Research Center (MMRC) and an Associate Professor at
the Telecommunication Department. His current research interest includes
mixed-signal CMOS analogue integrated circuits, wirelined and wireless
CMOS circuits, microwave circuits, and reconfigurable communication
systems.
Dr. Worapishet is a member of the Analog Signal Processing Technical Com-
mittee (ASPTC) of the IEEE Circuit and System Society (CASS), and also a
member of the IEICE.
Andreas Demosthenous (S’94-M’99-SM’05) was
born in Nicosia, Cyprus, in 1969. He received the
B.Eng. degree in electrical and electronic engi-
neering from the University of Leicester, Leicester,
U.K., in 1992, the M.Sc. degree in telecom-
munications technology from Aston University,
Birmingham, U.K., in 1994, and the Ph.D. degree in
electronic and electrical engineering from University
College London (UCL), London, U.K., in 1998.
From 1998 to 2000, he held a Postdoctoral Re-
search Fellow position with the Department of Elec-
tronic and Electrical Engineering, UCL. In 2000, he was appointed to the aca-
demic faculty of the same department, where he is currently a Professor and
leads the Analog and Biomedical Electronics Research Group. His main area
of research is analog and mixed-signal integrated circuits for biomedical, com-
munication, sensor and signal processing applications. He has numerous col-
laborations for interdisciplinary research and has published over 150 articles in
journals and international conference proceedings.
Dr. Demosthenous is a member of the Analog Signal Processing Technical
Committee (ASPTC) and the Biomedical Circuits and Systems (BioCAS)
Technical Committee of the IEEE Circuits and Systems Society (CASS). He
is also a member of the U.K. Engineering and Physical Sciences Research
Council (EPSRC) Peer Review College. He is an Associate Editor for the
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS and an
Associate Editor for the IEEE CASS Newsletter. He is on the International
Advisory Board for Physiological Measurement, Institute of Physics. In
2006 and 2007, he was an Associate Editor for the IEEE TRANSACTIONS ON
CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS. He is a member of the Technical
Programme Committee of various IEEE conferences including ESSCIRC,
BioCAS, and ECCTD.
Xiao Liu (S’05–M’09) was born in Chengdu, China,
in 1981. He received the B.Eng. degree in informa-
tion engineering from Xi’an Jiaotong University,
China, in 2003, the M.Sc. degree in microelectronics
systems design from University of Southampton,
U.K., in 2004, and the Ph.D. degree from University
College London (UCL), U.K., in 2009.
From 2006 to 2008, he was a Research Assistant
in the Department of Electronic and Electrical
Engineering, UCL. Since 2009, he has been a
Research Associate in the Analogue and Biomedical
Electronics Group, UCL. His main research interests include analog and
mixed-signal integrated circuit design for biomedical applications, neuropros-
theses and microelectronic sensor design.