課程名稱: 數位邏輯設計

P-1/74 2019/5/9

Textbook: Digital Design, 6th. Edition

M. Morris Mano and Michael D. Ciletti
Prentice-Hall, Inc.

教 師 : 蘇 慶 龍
Instructor : Ching-Lung Su
E-mail: kevinsu@yuntech.edu.tw
Chapter 4
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Chapter 4
Combinational Logic
Outline of Chapter 4
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.1 Introduction
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.1 Introduction
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◼ Introduction to Combinational Logic

Combinational Circuit:
 Output only depends on the present
combination of inputs
 Specified by a set of Boolean Functions
Logic Circuit
Sequential Circuit:
 Output depends on the input and the state of
the storage (past inputs)
4.2 Combinational Circuits
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.2 Combinational Circuits
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◼ Block Diagram of Combinational Circuits

2n-input
Combinations
0/1
Combinational Circuits
n inputs 0/1 m outputs
Logic Gates
0/1
4.3 Analysis Procedure
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.3 Analysis Procedure
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◼ Analysis Procedure of a Combinational Circuit

1. Make sure the given circuit is a combinational

circuit
◼ Combinational Circuit without feedback paths or
memory elements
◼ Feedback paths in digital circuits define a
sequential circuit
2. Obtain the output Boolean functions or the truth
table
4.3 Analysis Procedure
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◼ Procedure to Obtain the Output Boolean

Functions from a Logic Diagram
1. Label all gate outputs that are a function of input
variables with arbitrary symbol. Determine the
Boolean functions for each gate output.
2. Label the gates that are a function of input variables
and previously labeled gates with other arbitrary
symbols. Find the Boolean functions for these gates.
3. Repeat the process outline in step 2 until the outputs
of the circuits are obtained
4. By repeated substitution of previously defined
functions, obtain the output Boolean function in
terms of input variables.
4.3 Analysis Procedure
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◼ Procedure Example

A T2
B F1
C
A T1
B T3
C
F2'
A
B
A
C F2
B
C
4.3 Analysis Procedure
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◼ Procedure Example

F2 = AB + AC + BC
Step 1: T1 = A + B + C
T2 = ABC

T3 = F2’T1
Step 2:
F1 = T3 + T2

F1 = T3 + T2 = F2’T1 + ABC
Step 3-4: = ( AB + AC + BC )’ ( A+B+C ) + ABC
= A’BC’ + A’B’C + AB’C’ + ABC
4.3 Analysis Procedure
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◼ Procedure to Obtain the Output Boolean

Functions from the Truth Table
1. Determine the number of input variables in the circuit.
For n inputs, form the 2n possible input combinations
and list the binary numbers from 0 to 2n-1 in a table
2. Label the output of the selected gates with arbitrary
symbols
3. Obtain the truth table for the outputs of those gates
that are a function of the input variables only
4. Proceed to obtain the truth table for the outputs of
those gates that are a function of previously defined
values until the columns for all outputs are determined
4.3 Analysis Procedure
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◼ Procedure Example
Procedure

A B C F2 F2 T1 T2 T3 F1

0 0 0 0 1 0 0 0 0
0 0 1 0 1 1 0 1 1
0 1 0 0 1 1 0 1 1
0 1 1 1 0 1 0 0 0
1 0 0 0 1 1 0 1 1
1 0 1 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1

Truth Table for Example

4.4 Design Procedure
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.4 Design Procedure
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◼ Design Procedure of Combinational Circuits

1. State the problem
2. Determine the number of available input variables
and required output variables
3. Assign letter symbols to the input and output
variables
4. Derive the truth table
5. Simplify the Boolean function
6. Draw the logic diagram
4.4 Design Procedure
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◼ Design Example: BCD to Exceed-3 Code Conversion

Input BCD Output Exceed-3 Code

A B C D w x y z

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
x x x x x x x x
4.4 Design Procedure
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◼ K-Maps of BCD to Exceed-3 Code Conversion

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
00 1 1 00 1 1

01 1 1 01 1 1
B B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 X X

D D
z=D y = CD + C D

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 00

01 1 01 1 1 1
B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 1 X X

D D
x = B C + B D + BC D w = A + BC + BD
4.4 Design Procedure
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◼ Boolean Functions of BCD to Exceed-3

Code Conversion

z=D

y = CD + C D = CD + ( C+D )

x = B C + B D + BC D = B ( C+D ) + BC D
= B ( C+D ) + B ( C+D )

w = A + BC + BD = A + B ( C+D )
4.4 Design Procedure
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◼ Logic Diagram for BCD to Exceed-3 Code Conversion

D z
D CD
C y
C+D (C+D)

B x

A w
4.5 Binary Adder-Subtractor
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.5 Binary Adder-Subtractor
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◼ 4 Possible Operations for Addition of Two Binary Digits

0 0

+ 0 + 1

0 1

1 1

+ 0 + 1

1 10

Carry
4.5 Binary Adder-Subtractor
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◼ Half Adder

x S (Sum) x y C S
Half
Adder
y C (Carry) 0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
S = x y + xy
C = xy Half Adder Truth Table
4.5 Binary Adder-Subtractor
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◼ Logic Implementations of Half Adder

x
y x
S y S
x
y
x
y C C

S = x y + xy S = x+y
C = xy C = xy
4.5 Binary Adder-Subtractor
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◼ Full Adder
1. Full adders perform the arithmetic sum of three bits
2. Full adders is implemented by a 3-input 2-output
combinational circuit
3. Truth Table:
x y z C S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
4.5 Binary Adder-Subtractor
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◼ K-Maps for Full Adders

yz y=1 yz y=1
x 00 01 11 10 x 00 01 11 10
0 1 1 0 1

x=1 1 1 1 x=1 1 1 1 1

z=1 z=1
S = x y z + x yz + xyz + x y z C = xy + xz + yz
= x+y+z = xy + xy z + x yz
= xy + z(x + y)
4.5 Binary Adder-Subtractor
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◼ SOP Logic Implementations of Full Adders

x
y
z
x x
y y
z S x C
x z
y y
z z
x
y
z
4.5 Binary Adder-Subtractor
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◼ Full Adder Implementation with Two Half

Adders and an OR Gate
HA
HA
x x +y (x + y) + z
y S
xy
(x + y)z (x + y)z+xy
C
z
4.5 Binary Adder-Subtractor
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◼ Binary Adders

1. Binary adders perform the arithmetic sum of two

numbers
2. Binary adders can be constructed with full adders
connected in cascade
4.5 Binary Adder-Subtractor
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◼ 4-bits Binary Adders

Subscript (i) : 3 2 1 0

Input Carry 0 1 1 0 Ci
Augend 1 0 1 1 Ai
Addend + 0 0 1 1 Bi

Sum 1 1 1 0 Si
Output Carry 0 0 1 1 Ci+1

4-bit Addition Example

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
C4 FA FA FA FA C0

S3 S2 S1 S0
4-bit Adder
4.5 Binary Adder-Subtractor
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◼ n-bits Binary Adders

Bn-1 An-1 Bn-2 An-2 B1 A1 B0 A0

Cn-1 Cn-2 C2 C1
Cn FA FA FA FA C0

Sn-1 Sn-2 S1 S0
n-bit Adder
4.5 Binary Adder-Subtractor
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◼ Carry Propagation Delay:

N-bit adder has 2n gate carry propagation delay !!
Ai Pi
Pi + Ci
Bi Si
Gi
PiCi+Gi
Ci+1
Ci

1 full adder has 2-gate carry propagation delay

4.5 Binary Adder-Subtractor
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◼ Carry Lookahead: Reduce Carry Propagation Delay

Gi : Carry Generate
Pi : Carry Propagate

Ai Pi
Bi Si
Gi
Ci+1
Ci

Pi = Ai + Bi Si = P i + C i
Gi = AiBi Ci+1 = Gi + PiCi
4.5 Binary Adder-Subtractor
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◼ Carry Lookahead: Carry Bits

C0 = Input Carry
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1( G0 + P0C0 ) = G1+ P1G0 + P1P0C0
C3 = G2 + P2C2 = G2+ P2G1 + P2P1G0+ P2P1P0C0
4.5 Binary Adder-Subtractor
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◼ Carry Lookahead Generator

C3

P2
G2

C2
P1
G1
P0 C1
G0
C0
4.5 Binary Adder-Subtractor
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◼ 4-bit Carry Lookahead Adder

C4 C4
A3
B3 P3 P3
C3 S3
G3

Carry Lookahead Generator

A2
B2 P2 P2
C2 S2
G2

A1
B1 P1 P1
C1 S1
G1

A0
B0 P0 P0
C0 S0
G0
C0 C0
4.5 Binary Adder-Subtractor
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◼ Binary Subtractor
1. Implement subtraction with 2’s complement number
system
2. A-B = A + (-B) = A + 1’sc (B) + 1
3. Implement 1’sc with XOR gates:

B M Output

0 0 0 1'sc (Output = B) when M=0

0 1 1
1 0 1 1'sc (Output = B) when M=1
1 1 0
4.5 Binary Adder-Subtractor
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◼ 4-Bit Binary Adder/Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

M: M=0 A+B
M=1 A-B

C4 C3 C2 C1 C0
C FA FA FA FA

S3 S2 S1 S0
4.5 Binary Adder-Subtractor
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◼ Overflow: When two numbers of n digits each are

added and the sum occupies n+1 digits, we say that
an overflow occurred.
8-bit 2'sc number presents [-128, +127]

V V

Cout Cin
0 1 1 0
+70 0 1000110 -70 1 0111010
+80 0 1010000 -80 1 0110000

+150 1 0010110 -150 0 1101010

> +127 < -128
Postive Overflow Negative Overflow
4.6 Decimal Adder
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.6 Decimal Adder
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◼ BCD Sum vs. Binary Sum

Binary Sum BCD Sum Decimal

K Z8 Z4 Z2 Z1 C S8 S4 S2 S1

0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 1'sc 0 1 0 0 1 Copy 9

0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
>9
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 +6 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
4.6 Decimal Adder
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◼ BCD Adders
Addend Augend

K 4-Bit Binary Adder Carry In

Z8 Z4 Z2 Z1

+6
Output Carry

Detect>9

4-Bit Binary Adder

S8 S4 S2 S1
4.7 Binary Multiplier
P-43/74 2019/5/9

4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.7 Binary Multiplier
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◼ 2-Bit by 2-Bit Binary Multiplier

A0
B1 B0

A1
B1 B0
B1 B0
A1 A0

A0B1 A0B0
A1B1 A1B0

C3 C2 C1 C0
HA HA

C3 C2 C1 C0
4.7 Binary Multiplier
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◼ 4-Bit by 3-Bit Binary Multiplier

A0
B3 B2 B1 B0

A1
B3 B2 B1 B0 0

Addend Augend
4-Bit Adder
Sum and Carry Output
B3 B2 B1 B0

x A2 A1 A0 A2
B3 B2 B1 B0

Addend Augend
4-Bit Adder
Sum and Carry Output

C6 C5 C4 C3 C2 C1 C0
4.8 Magnitude Comparator
P-46/74 2019/5/9

4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.8 Magnitude Comparator
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◼ Magnitude Comparator

1. Comparator determines the relationship between

two inputs (A,B) is A>B, A=B, A<B
2. The truth table has 2n2n=22n entities for a n-bit
input number
3. Comparator has a well-defined algorithm for its
operation procedure
4.8 Magnitude Comparator
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◼ Algorithm for 4-bit Comparison

A= A3 A2 A1 A0
Input A, B 
B= B3 B2 B1 B0
A3=B3 and A2=B2 and A1=B1 A0>B0
If A=B  A3=B3 and A2=B2 and A1=B1 and A0=B0
A=B  x3x2x1x0

xi = AiBi + Ai Bi for i = 0, 1, 2, 3 A>B  A3B3 + x3A2B2 + x3x2A1B1 + x3x2x1A0B0

where xi=1 only if the pair of bits in position i are equal
A<B  A3B3 + x3A2B2 + x3x2A1B1 + x3x2x1A0B0
Ai
xi
Bi A3=B3 and A2=B2 A1<B1
4.8 Magnitude Comparator
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◼ 4-bit Magnitude Comparator

AB
A3
x3

B3
A2 A<B
x2

B2
A1
x1

B1
A0
x0
A>B
B0
A=B
4.9 Decoders
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.9 Decoders
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◼ Decoders

n-to-m-line decoders: n-input minterm generators

m0
m1
m2
n-to-m-line
n Inputs 2n Outputs
Decoder

m2n-1
4.9 Decoders
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◼ Truth Table of 3-to-8-line Decoder

Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
4.9 Decoders
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◼ Logic Implementation of 3-to-8-line Decoder

m0
D0= x y z
z D1= x y z

D2= x y z
y
D3= x y z

x D4= x y z

D5= x y z

D6= x y z
m7
D7= x y z
4.9 Decoders
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◼ 2-to-4-line Decoder
1. Constructed with NAND Gates
2. Economical Implementation
3. Additional Enable Input
4. Truth Table:

E A B D0 D1 D2 D3

1 x x 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
4.9 Decoders
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◼ Logic Implementation of 2-to-4-line Decoder with Enable:

Demultiplexer

D0
A D1

B D2

D3
E
4.9 Decoders
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◼ 416 Decoder Constructed with 38 Decoders

w
38
x Decoder D0 to D7
y Output
E
z 1 0 Enable

38
Decoder D8 to D15

E
Disable
4.9 Decoders
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◼ Combinational Logic Implementation with Decoders

1. Combinational Logic can be implemented with SOP

(Minterm Summation)
2. Decoders provide the combinations of the all
minterms
4.9 Decoders
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◼ Full Adder Implementation with Decoders

and OR Gates
Full Adder : Sum =  (1,2,4,7)
Carry =  (3,5,6,7)

m0
m1
x m2
m3 Sum
38
y Decoder m4
m5 Carry
z m6
m7
4.10 Encoders
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.10 Encoders
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◼ Encoders
1. Encoders perform the inverse operation of decoders
2. 2n input  n output
4.10 Encoders
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◼ Octal-to-Binary Encoders
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 x y z

1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

z = D1 + D3 + D5 + D7
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7
4.10 Encoders
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◼ Priority Encoder
The operation of the priority encoder is such that if two
or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
Example
Priority

Inputs Outputs
D0 D1 D2 D3 x y V

0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
x = D2 + D3
y = D3 + D1D2
V = D0 + D1 + D2 + D3
4.10 Encoders
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◼ K-Map of Priority Encoder

D2 D2

00 01 11 10 00 01 11 10
00 x 1 1 1 00 x 1 1

01 1 1 1 01 1 1 1
D1 D1
11 1 1 1 11 1 1 1
D0 D0
10 1 1 1 10 1 1

D3 D3

x = D2 + D3 y = D3 + D1D2
4.10 Encoders
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◼ Logic Implementation of Priority Encoder

D3
D2 y
D1
x
V
D0
4.11 Multiplexers
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits
4.11 Multiplexers
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◼ Multiplexer

1. Multiplexer selects binary information form one of

many input lines and detects it to a single output
line.
2. 2n input and n selection lines to 1 output
4.11 Multiplexers
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◼ 2-to-1-line Multiplexer

I0 If S=0 : I0=Y
Logic Diagram :
1 Y
I1
0
S 0

I0 0
Block Diagram : MUX Y
I1 1

S
4.11 Multiplexers
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◼ 4-to-1-line Multiplexer
I0 0
0

I1 0
1
Y
I2 1 S0 S1 Y
0

I3 1 0 0 I0
1
0 1 I1
1 0 I2
1 1 I3

S1 Truth Table
S0
Logic Diagram
4.11 Multiplexers
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◼ Quadruple 2-to-1-line Multiplexer

A0
Y0
A1
Y1
A2
Y2
A3
Y3
E S Output Y
B0
1 x all 0's
B1 0 0 Select A
0 1 Select B
B2

B3
S=0 S=1
S
E
4.11 Multiplexers
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◼ Combinational Circuit Implementation with

Multiplexer – Example 1
F(x,y,z)=  (1,2,6,7)

x y z F y S0

0 0 0 0 x S1
F=z
0 0 1 1
0 1 0 1 z
F=z 41 MUX F
0 1 1 0
1 0 0 0 z
1 0 1 0 F=0
0
1 1 0 1
1 1 1 1 F=1 1
4.11 Multiplexers
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◼ Combinational Circuit Implementation with

Multiplexer – Example 2
F(A,B,C,D) =  (1,3,4,11,12,13,14,15)
Selection Input Output
A B C D F
C S0
0 0 0 0 0
F=D B S1
0 0 0 1 1
0 0 1 0 0 A S2
F=D
0 0 1 1 1
0 1 0 0 1 D 0
F=D
0 1 0 1 0 1
0 1 1 0 0 81 MUX F
F=0 2
0 1 1 1 0
1 0 0 0 0 0 3
F=0 4
1 0 0 1 0
1 0 1 0 0 5
F=D
1 0 1 1 1 1 6
1 1 0 0 1 7
F=1
1 1 0 1 1
1 1 1 0 1
F=1
1 1 1 1 1
4.11 Multiplexers
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◼ Three-State Buffer (Tri-State Buffer)

Normal Input A Output Y

Control Input C

Input Output
A C Y

0 0 Hi-Z If C=1, Y=A

0 1 0 If C=0, Y=High-Impedance
1 0 Hi-Z
1 1 1
4.11 Multiplexers
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◼ Multiplexer Implementations with Three-

State Buffer
I0 Y

I1

A Y I2

I3
B
Select
0
Select 24 1
Decoder 2
Enable
3

2-to-1-line MUX 4-to-1-line MUX

4.12 HDL for Combinational Circuits
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4.1 Introduction
4.2 Combinational Circuits
4.3 Analysis Procedure
4.4 Design Procedure
4.5 Binary Adder-Subtractor
4.6 Decimal Adder
4.7 Binary Multiplier
4.8 Magnitude Comparator
4.9 Decoders
4.10 Encoders
4.11 Multiplexers
4.12 HDL for Combinational Circuits