74 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO.
1, FEBRUARY 2015
FPGA Implementation of Software Defined
Radio-Based Flight Termination System
Amiya Ranjan Panda, Student Member, IEEE, Debahuti Mishra, and Hare Krishna Ratha, Member, IEEE
Abstract—This paper proposes a field-programmable gate
array (FPGA)-based software defined radio (SDR) implemented
flight termination system (FTS). This is purely a new kind of
implementation of digital FTS in SDR platform. The applied
design procedure replaces a multiple platform-based system with
a single platform. It also guarantees reconfigurable, interoperable,
portable, and handy FTS, and maintains errorless, bug free, and
reliable implementation. Real-time flight termination operation
demands a very highly reliable and ruggedized platform. Hence,
the FTS is implemented in FPGA. In order to minimize hardware
resources and to enable future upgradation, efficient optimization
technique has been applied. LabVIEW, a high-level programming
language is used to simulate and implement the system in real
time and enables rapid prototyping. The system was validated at
subsystems level by measurements of different parameters in var-
ious intermediate stages of processing, and further was validated
as an integrated system at real-time telecommunication operation
environment.
Index Terms—Field-programmable gate array (FPGA), flight
termination system (FTS), real-time system, software defined
radio (SDR).
I. I NTRODUCTION
A NEWLY developed, flight vehicle (FV) needs rigorous
testing to satisfy all expected performance. When testing
the FV dynamically, there are lots of uncertainties regarding
the flight performance. Hence at test facility, a flight termina-
tion system (FTS) is utilized to secure the property and human
life. FTS basically involves in generation and transmission of
remote command signals to the airborne FV to execute some
operation inside the vehicle as required.
FTS is used for termination of high speed FV under test.
Termination of test vehicle is mandatory if the high speed
vehicle deviates from its preset trajectory and takes differ-
ent course due to unpredictable failures of onboard system.
In such cases, specific commands are transmitted from com-
mand transmission system (CTS) for termination of test vehicle
via remote control unit (RCU). The commands are transmitted
Manuscript received May 30, 2014; revised August 29, 2014; accepted
October 08, 2014. Date of publication October 23, 2014; date of current version
February 02, 2015. This work was supported by the Defence Research and
Development Organization, Government of India. Paper no. TII-14-0591.
A. R. Panda is with the Department of Computer Data Processing, Integrated
Test Range, Defence Research, and Development Organization, New Delhi,
India (e-mail: amiya87@gmail.com).
D. Mishra is with the Department of Computer Science and Engineering,
Siksha “O” Anusandhan University, Bhubaneshwar, India (e-mail: debahuti
mishra@soauniversity.ac.in).
H. K. Ratha is with the Integrated Test Range, Defence Research, and
Development Organization, New Delhi, India (e-mail: hk.ratha@itr.drdo.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TII.2014.2364557
1551-3203 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
when required during test. Real-time flight termination opera-
tion demands a very highly reliable and ruggedized platform.
The commands transmitted by CTS is received and decoded
by onboard command reception system (CRS) at FV and the
commanded operation is done accordingly.
The design of FTS involves real-time signal generation,
transmission, and analysis of the transmitted signal. The system
also has to ensure real-time communication with RCU with var-
ious demanded protocols. The system versatility with respect
to different modulation schemes must be ensured for future
upgradation.
A suitable software defined radio (SDR) platform has proven
itself to be very efficient platform for implementing such ver-
satile and reconfigurable system architecture [1]–[3]. SDR in
recent trend is a common term, which has been used for rapid
prototyping of different types of complex communication sys-
tem used in different fields, such as for radar design [4], global
positioning system (GPS) receiver design [5], adaptive optics
system design [6], and drive servo system design [7]. Many
real-time applications such as advanced control system design
[8], system performance measurement [9], data acquisition
[10], and processing [11] use the field-programmable gate array
(FPGA) integrated with PCI Extension for Instrumentation
(PXI) platform for implementation.
High robustness and high reliable flight termination oper-
ations are strongly desired. High degree of versatility and
reconfigurable architecture with real-time response is achiev-
able through the combination of highly reliable software with
wide range of capabilities and suitable hardware platform,
i.e., FPGA. It is necessary to have system which is flexible,
reconfigurable and dynamic to the environmental situations,
and hardware modifications. SDR based on FPGA system
could be a good option for designing intelligent and recon-
figurable CTS for operations on a single platform [12], [13],
as compared to the previously used bulky CTS, which was a
discrete component-based fixed configuration system. Different
hardware-based CTSs were used for test of different FVs. The
newly developed SDR-based FTS system in turn, solves the
problem of frequent hardware replacements and cost of design
as in SDR-based system, only software updation is required to
implement new system.
The FPGAs are broadly used nowadays for many appli-
cations [14], [15]. Because of efficient computational power,
parallel data processing, low power consumption and optimized
area, FPGAs are presently taking over legacy processor-
based applications. Current development in FPGA technolo-
gies include as many as dedicated digital signal processor
(DSP) cores to fit several order complex algorithms to be
PANDA et al.: FPGA IMPLEMENTATION OF SDR-BASED FLIGHT TERMINATION SYSTEM
Fig. 1. Block diagram of the FTS transmitting signal to FV.
implemented. Further, it is necessary to optimize the design
algorithms for optimal resource utilization.
The FTS algorithm has been implemented in FPGA, which
is optimized for DSP and memory intensive applications with
low power serial connectivity [16]. LabVIEW FPGA module of
national instruments (NI) Flex-Reconfigurable I/O (RIO) sys-
tem has been used to simulate and design the various modules
of the system. LabVIEW FPGA module enables to simulate
various modules of the system in faster way [17] and the
advantage is that the same simulation applies in real hardware
implementation. Hence, rapid prototyping is achieved using
LabVIEW software. The design has been implemented using
fixed point data type, so as to optimize the resource utilization
within the FPGA [14], [15].
The CTS consists of a real-time controller (RTC), host
computer, and SDR-based command transmission and recep-
tion unit (Fig. 1). The RTC offers a communication interface
between RCU and host computer with CTS. RCU is used for
remote operation of the CTS. Host computer is used for con-
figuration, local mode operation and analysis of intermediate
signal processing of the CTS.
The structure of this paper is as follows. Section II describes
the mathematical formulation of the problem. It continues with
the SDR-based design approach presentation and the Flex-
RIO software communication architecture for FTS operation.
Section III describes the FPGA Implementation of SDR-based
FTS. Section IV shows the laboratory setup and experimental
results. Finally, Section V concludes the paper.
II. SDR-BASED FTS A LGORITHM
A. Mathematical Formulation
The concept of FTS is depicted in Fig. 1. The RCU is
connected with the CTS through reliable serial communica-
tion links. The commands are given from the RCU to CTS.
The commands are generated and transmitted from the CTS,
received by onboard CRS through radiofrequency (RF) link,
and required operation is done accordingly.
The generated commands are a frame of binary bits. This
frame comprises n number of binary data bits, which is headed
by h number of binary header bits and trailed by s number
of stop bits. So the length of the frame is N = (n + h + s).
75
The whole frame is encoded with Manchester encoding
scheme and total number of bits in a frame becomes double,
i.e., 2N .
The frame is converted to binary data wave form d(t) with the
logic d(t) = +1 or − 1 corresponding to the binary bits 1 or 0.
Hence, the binary data waveform d(t) can be expressed as
2N
 −1
d(t) = bi P (t − i. Tb ) (1)
i=0
where bi is the ith number of bit of the frame. The bit bi
takes on value 1 and −1 for binary bit 1 and 0, respectively.
P (t) is a rectangular pulse which can be represented as P (t) =
rect(t/Tb ), where Tb is bit duration.
This binary data waveform d(t) modulates a carrier sig-
nal using binary frequency shift keying (BFSK) modulation
scheme. In this scheme, sinusoidal signal with higher fre-
quency (ωH ) and lower frequency (ωL ) are generated for bit
1 and 0, respectively. Thus, the BFSK modulated signal can be
represented as
BFSK(t) = A cos {ω0 t + d(t) · Ω × t} (2)
where Ω is a constant offset from the carrier frequency (ω0 ).
Equation (2) can be written as
BFSK(t) = A cos [{{ω0 + d(t)} Ω · t}] = m(t) (3)
where for bit 1, d(t) = +1 and its corresponding higher fre-
quency (ωH = ω0 + Ω) and for bit 0, d(t) = −1 and its
corresponding lower frequency (ωL = ω0 − Ω).
This BFSK modulation is done in very low frequency, i.e., in
very-low frequency band. This signal is finally up-converted to
ultra-high frequency (UHF) band using frequency modulation
(FM) scheme. The basic principle behind FM is to vary the car-
rier frequency in proportion to the modulating signal m(t). This
means instantaneous frequency (ωi ) of the carrier is changing
in proportion to m(t). This can be written as
dθ(t)
ωi (t) = ωc + Kf · m(t) = (4)
dt
76 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 1, FEBRUARY 2015

where ωc is career frequency, kf is a constant, and θ(t) is a

generalized angle. Equation (4) can be written as
t
θ(t) = {ωc + Kf · m (α)} dα. (5)
−∞

Equation (5) follows to

t
θ(t) = ωc t + Kf m (α) dα. (6)
−∞

So the corresponding FM signal can be written as

⎧ ⎫
⎨ t ⎬
FM(t) = Ac cos ωc t + Kf m (α) dα (7)
⎩ ⎭
−∞

where Ac is amplitude of the career signal and modulating

signal m(t) is BFSK modulated signal BFSK(t).
In the receiving side, FM signal FM(t) can be demodulated
by applying the signal to the differentiator. The output of the
differentiator is
⎡ ⎧ ⎫⎤
⎨ t ⎬
d ⎣
FṀ(t) = Ac cos ωc t + Kf m (α) dα ⎦. (8)
dt ⎩ ⎭
−∞

Equation (8) follows to

⎧ ⎫
⎨ t ⎬
FṀ(t) = Ac {ωc + Kf . m(t)} sin ωc t + Kf m (α) dα .
⎩ ⎭
−∞
(9)

This signal is both amplitude and frequency modulated.

If ωc + kf · m(t) > 0, for all t, m(t) can be recovered by
envelope detection of FM(t).
Next step is to demodulate the BFSK signal for recovering
the command frame. The BFSK signal is demodulated by a
square law detection method [18].

B. SDR-Based Design Approach

For a conventional discrete component-based design, it is
not possible to vary the functionality of the system beyond
certain range of specification. But an SDR based on FPGA
enhances the capability of the platform so as to design a sys-
tem with reconfigurability and flexibility. The main philosophy
behind SDR is that it can flexibly alter the radio waveforms by
changing software and without changing the SDR platform. As
in SDR, large part of the waveforms are defined in software,
it allows us to flexibly change the waveforms within certain
bounds by implementing the appropriate software modules
[2], [3].
SDR can be implemented in different platforms [19]–[23]. Fig. 2. Block diagram of the proposed algorithm for the FPGA implementa-
An SDR-based FTS including its main elements implemented tion of FTS. (a) Broad software implementation scheme of FTS. (b) Details
software communication scheme of FTS. (c) Data flow diagram of transmis-
in FPGA is depicted in Fig. 2(b). The heart of the system is sion module implemented in FPGA. (d) Data flow diagram of reception module
real-time operating system. The waveforms and their portabil- implemented in FPGA. (e) Data transfer methods used for transferring data in
ity which includes the middleware are realized through basic FPGA, real-time (RT), and host VI.
PANDA et al.: FPGA IMPLEMENTATION OF SDR-BASED FLIGHT TERMINATION SYSTEM
functions and libraries provided by the software framework.
The combination of software communication architecture [24],
[25] and common object request broker architecture (CORBA)
[26] forms the software framework.
C. LabVIEW FLEXRIO Software Communication Architecture
In LabVIEW Flex-RIO Software Communication Archi-
tecture [3], a host VI runs on a Windows PC, a real-time VI runs
on RTC, and FPGA get programmed through a bit file generated
according to the FPGA VI.
The architecture supports quick development of various com-
plex systems [27], [28]. Here program loops which are to be
executed concurrently and are highly time critical (inline signal
processing, custom timing synchronization, and digital commu-
nication) are implemented on the FPGA. Due to simultaneous
running of the program loops, a very high loop rate can be
achieved. Floating point operations which are less time critical
can be run on the LabVIEW real-time module.
FPGAs support operations in parallel mode, compared to
common processors [29], which compute in sequential mode.
FPGA thus help us to achieve very time critical task. Their only
limitation is in the availability of space which is related to the
number of gates supported per FPGA [30].
III. FPGA I MPLEMENTATION OF SDR-BASED FTS
A. Realization of Signal Generation in LabVIEW FPGA
In the presented application, the SDR-based telecommunica-
tion operation is realized in FPGA, using high-level program-
ming language (LabVIEW). The command codes generation
and encoding are done easily.
The essential problem during the implementation of SDR-
based telecommunication operation is realization of signal
generation for modulation, digital up conversion (DUC), digi-
tal down conversion (DDC), demodulation, and signal filtering.
For this purpose, the signal is generated in LabVIEW FPGA
using a technique called direct digital synthesis (DDS) [31].
In DDS, a time varying signal is generated in digital form
and then digital to analog conversion is performed to obtain an
analog waveform usually a sine wave.
In LabVIEW 2013, the Xilinx DDS Compiler Logi CORE
4.0 IP provides direct digital synthesizer. In this project, 16 bits
output sample precision is used. DDS Compiler core IP can
generate frequencies from less than 1 Hz up to 40 MHz (based
on a 100-MHz clock) [31].
B. LabVIEW Code Realization for FPGA
Optimization exists in the coding of FPGA and timing in var-
ious ways. In this project, the fixed point notation is used, which
helps in achieving hardware resources utilization [15], [16].
The single cycle timed loop is a special use of the LabVIEW
timed loop structure enabling optimization of program. This
loop executes all functions inside it within one tick of the FPGA
clock in FPGA target. It can be used with derived clocks to
operate the loop at a different rate and can be used with faster
global clock (80 MHz or above). Use of shift register and feed-
back nodes in it enables us to implement parallel execution of
77
logic and passing of data between subsequent iterations. The
appropriate use of state machine for implementing different
parts of the application in it provides speed and efficiency of
the application.
The efficiency of the algorithm can be enhanced through
appropriate use of pipelining technique. In this scheme, the
algorithm is broken into smaller parts and those parts which
can be executed independently are identified. Next, they are
executed in parallel manner. The length of code executed in
each iteration is reduced and the total time for implementing
the whole application becomes less [16], [36].
During this implementation two very important factors con-
sidered are balancing of pipeline stages and minimization of
memory transfer.
Effective compilation of the program in the target application
may not be certain by applying these methods while realizing
the SDR-based FTS. For surmounting this problem, a special
program as depicted in Fig. 2, has been developed.
The algorithm comprises two parts: the main program and
the subprograms [Fig. 2(a)]. The SDR-based command trans-
mission chain and command reception chain (CTS) are realized
in the main part of the program. The encoding (Manchester
Encoding), decoding, modulation (FM followed by BFSK mod-
ulation), demodulation (noncoherent BFSK demodulation fol-
lowed by FM demodulation), DUC, and DDC are implemented
in two FPGAs and are executed from the main program through
bit file of respective program. Modulation, demodulation, DUC,
and DDC are implemented as subprograms in FPGA VI, which
allow the program to optimally use the logic elements.
During the data processing in each chain (transmission chain
and receiving chain), the main program transfers control to sub-
programs, where output values are calculated simultaneously
by the sub-VIs.
It should be noted that the application startup time of the
system is very fast as the application is deployed in RTC.
The change of any parameter setting can be done at real
time, which is very easy and fast as the data transfer between
RTC and host occurs through Transmission Control Protocol/
Internet Protocol (TCP/IP) and between RT and FPGA through
first-in-first-out (FIFO) and memory element.
Block diagram of broad software implementation of FTS is
presented in Fig. 2(a). Other parts of the FTS, implemented in
RT and FPGA, are shown in Fig. 2(b) and the detailed FPGA
implemented parts are shown in Fig. 2(c) and (d), respectively.
Fig. 2(e) shows the data transfer methods used for transfer-
ring data within important modules of FPGA VI, RT VI, and
Host VI. However, within the modules (among the loops), data
transfer occurs through FIFO and memory elements.
C. Hardware Realization of SDR-Based FTS
The program for the Flex-RIO RTC, realized for performing
the command transmission and command reception operation,
has two levels comprising the one portion related with the
FPGA and other portion related with the RTC. The RCU is
connected to the RTC through serial communication link, used
to send trigger for command generation and transmission. The
host portion of the controller takes the responsibility for provid-
ing the transmission and reception analyzed signal and setting
78
Fig. 3. FPGA-based FTS connected with host computer and RCU.
the parameters for the total system. Direct memory access
enables synchronization of both of the controller parts, and
at the same time safeguards the efficiency and speed of data
transfer. Optimization of data transmission is obtained by this
technique, which takes place between Flex-RIO components
and at the same time between the code parts through the RAM
and the FIFO queues.
In this scheme, the transmitted commands from the RCU
are stored in the ROM of the Flex-RIO Controller and to
be conveyed to the SDR-based CTS implemented in FPGA.
For making the transmission and reception of commands
reconfigurable, the programs are implemented in FPGAs. In
transmission chain, DUC is implemented in the FPGA pro-
grammatically using interpolation filter, DDS and mixer [33].
The digital mixer and DDS translate baseband samples up to
the intermediate frequency (IF). The mixer generates one out-
put sample for each of its two input samples. To improve the
sampling frequency of baseband signal interpolation is used.
The primary reason to interpolate is simply to increase the
sampling rate at the output of one system, so that another sys-
tem operating at a higher sampling rate can operate the signal.
In reception chain, DDC is implemented in the FPGA pro-
grammatically using DDS and low pass filter [33]. The digital
mixer and DDS translate the digital IF samples down to base-
band. The finite impulse response (FIR) low pass filter limits
the signal bandwidth and acts as a decimating low pass filter
(Fig. 3).
For parallel implementation of DUC and DDC in FPGAs,
according to the presented algorithm realized in the NI
LabVIEW FPGA module, reentrant and non-reentrant execu-
tions of the graphical code parts were used. Through this tool,
the developed algorithm can use all the features of the FPGA; so
suitable selection of the execution sequence for some portions
of the algorithm is possible.
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 1, FEBRUARY 2015
The solution presented here is adequate for implementation
of the SDR-based CTS, but more complicated task arises when
the system is used for real-time flight termination operation.
The commands are to be given from RCU, placed at remote
locations. In such cases, the RCU is connected to the RTC
via reliable serial communication link and one additional loop
is necessary for implementation. So in the described solution,
total four routines are working in the same time: first one for
host support, second one for RCU support, third one for FPGA
implemented SDR-based CTS, fourth one for FPGA imple-
mented SDR-based CRS. These four subroutines have different
time for calculation. Correct operation of the FTS is guaran-
teed through disciplined data transfer between them. LabVIEW
supports few tools for synchronization and the most important
areas covered are occurrences, interrupts and loops executed in
sequential manner. With the help of these tools, we can inhibit
some part of the code while realizing the other parts. In addi-
tion, it facilitates enabling an order of the data transfer while
executing loops.
An algorithm capable of measuring the transmitted signal
and next received signal from the air is very much required
to carry out the test. The transmitted signal is received from
air through receiving antenna and fed to pre amplifier. Then the
signal is down converted and processed through FPGA received
chain (Fig. 3).
Several commands are sent to the transmission line of CTS
from RCU through RTC for transmission, and further, the
commands are received through reception line of CTS. The
maximum usable clock frequency of the FPGA is 100 MHz.
However the baseband level implementation is done at 10 MHz
clock and IF level processing is done at 80 and 100 MHz
clock. Whole application needs 86.4% of SLICEs from hard-
ware resources. Complete resource utilization is summarized in
Table I.
PANDA et al.: FPGA IMPLEMENTATION OF SDR-BASED FLIGHT TERMINATION SYSTEM 79

TABLE I
H ARDWARE R ESOURCES U TILIZATION IN FTS A PPLICATION

Fig. 5. Block diagram of online test setup.

Fig. 4. Block diagram of laboratory setup.

Fig. 6. Laboratory setup.

IV. E XPERIMENTAL S ETUP
A. Laboratory Setup TABLE II
SDR-BASED FTS PARAMETERS S ETTING
The SDR-based FTS includes FPGA, real-time operating
system (RTOS), and general processor units (GPUs). The com-
munication algorithms, DDC and DUC are implemented in
FPGAs [32]. The analog to digital conversion, digital to ana-
log conversion, RF up conversion, and RF down conversions
are implemented in high speed PXIe cards. The remote com-
mand interface is implemented in GPU connected to RTOS via
reliable communication links. The SDR-based FTS algorithms
were implemented using high-level programming language
(LabVIEW) and were realized by NI PXI-7966R with Xilinx
Virtex 5, SXT, FPGA [34], [35].
The experiment was done in two phases. Offline: The
onboard receiver with decoder (nominal power of 12 V dc) is receiver with decoder is kept in laboratory and the received sig-
kept in laboratory (Fig. 4). The onboard receiver with decoder nal status information is fed to host computer through ethernet
is kept inside helicopter and received the status through ground link for analysis.
telemetry stations (Fig. 5).
The laboratory setup (Fig. 6) is composed of one onboard
receiver and decoder with receiving antenna. Initially, different B. Experimental Results
command codes and frequency of operation are set in the on In both of the testing procedure, the commands are transmit-
board receiver. Then, the commands are transmitted from FTS ted at different frequency bands such as HF, VHF, and UHF and
with the same command codes and frequency set in onboard the signal characteristics were analyzed. The system parameters
receiver. The delay between transmission and reception of com- setting were depicted in Table II.
mand codes are observed and analyzed by taking feedback from The overall performance of the system which includes trans-
the onboard decoder to the host computer. mission, reception, and medium has been validated using bit
In online experimental setup, the onboard receiver with error rate (BER) performance. The radio communication sys-
decoder is kept inside helicopter and received the status through tems and the radio links are generally identified with parameters
ground telemetry stations and the same is fed to the host com- like signal to noise ratio and Eb /N0 , which signifies the
puter for analysis. In offline experimental setup, the onboard capability of the facilities. BER is generally defined in terms of
80
Fig. 7. (a) Plot between BER and Eb /N0 (theoretical vs. observed). Linearity measurement w.r.t. (b) gain and (c) noise figure.
Fig. 8. IF spectrum observed in spectrum analyzer at (a) 25 MHz at transmitter side, (b) 15 MHz at receiver side, and (c) transmitted and received IF frequency
observed in oscilloscope, simultaneously.
probability of error (POE). The POE function for noncoherent
BFSK is represented by
1 −Eb /2N0
Pe = e .
2
The BER performance [37] of the transmitted signal is ana-
lyzed and observed to be similar with the theoretical BER
performance of noncoherent BFSK modulated signal, which is
shown in Fig. 7(a).
At receiver chain, the RF signal conditioning is done by NI
PXI 5690 module which includes low noise/high gain ampli-
fier and programmable attenuators. It is a 100 kHz to 3 GHz,
two-channel programmable amplifier and attenuator with one
fixed gain path and one programmable gain/attenuation path. In
this project, the fixed gain path is used with a typical gain of
30 dB across all frequencies. The channel offers a low noise
figure and flat frequency response as shown in Fig. 7(b). The
linearity of gain with frequency is shown in Fig. 7(c).
For proper validation of the performance of the FTS, inter-
mediate signal for each transmission data and reception data
are captured and analyzed. After verification of baseband
signal through a baseband decoder then only further mod-
ulation and up-conversion operation are carried out. The
time synchronization criticality has verified by capturing the
encoded data waveform and measuring the widths of the pulses.
The stability of the frequency generated by the DDS algorithm
through the hardware is measured and expected results were
obtained. The FM and demodulation are implemented using
intermediate frequencies (IFs) at 25 and 15 MHz, respectively
[Fig. 8(a) and (b)]. Fig. 8(c) shows frequency spectrum for
transmit IF and receive IF. Fig. 9 shows the measurement of
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 1, FEBRUARY 2015
(10)
Fig. 9. Measurement of time duration of one cycle at 25 MHz in oscilloscope.
the time duration of one cycle duration when modulation was
switched OFF. Time duration of 40 ns corresponds to 25 MHz
IF signal.
For practical transmission purpose, transmit IF signal is up-
converted at different frequencies and transmitted in the air.
(Fig. 10 shows spectrum at 1.5 GHz, 1 GHz, and 500 MHz.)
Various tests have been carried out to test and validate the
FTS. For a reliable operation of high power amplifier, the out-
put power linearity is very crucial for the transmitter over the
interest frequency of operation. It has been experienced that
the output power and frequency are very much linear in the
specified frequency range [Fig. 11(a) and (b)].
For a good transmitter design, designer must consider that the
harmonics must be eliminated, so that it shall not hamper other
communication system. When power amplified and transmitted
in air, by using a proper filter at the IF level, harmonics are
eliminated [Fig. 12(a)]. For faithfully transmission purpose, the
channel power also has been measured and 99% channel power
resides in 262 kHz of bandwidth [Fig. 12(b)].
PANDA et al.: FPGA IMPLEMENTATION OF SDR-BASED FLIGHT TERMINATION SYSTEM 81

Fig. 10. RF spectrum observed in spectrum analyzer at (a) 1.5 GHz, (b) 1 GHz, and (c) 300 MHz.

Fig. 11. Linearity measurement w.r.t. (a) power (plot between input frequency and observed power) and (b) frequency (plot between input frequency and output
frequency).

Fig. 12. (a) Frequency spectrum at 300 MHz showing zero harmonics at 600 and 900 MHz. (b) Measurement of bandwidth for 99% channel power.

V. C ONCLUSION In future, code division multiple access (CDMA)-based FTS

In this paper, an SDR-based FTS, a transceiver system imple-
mentation is presented. The system has been implemented
using NI-Flex RIO configuration. Xilinx FPGA integrated into
the Flex RIO module has given a very highly flexible platform
for complex algorithms for FTS system designing. The system
has been designed using LabVIEW FPGA module software
and deployed through LabVIEW RT running into the controller
chassis. The RT LabVIEW provides a very reliable and fast
communication between the RCU and FTS transceiver system.
Suitable algorithms for signal generation, encoding, base-
band, and pass band modulation, DUC and down conversion,
filter design have been chosen and implemented to ensure
optimized uses of hardware.
The performance of the system is analyzed through study of
the intermediate signal processing. Analysis is done at both IF
and RF stages of transceiver and the system is validated by lin-
earity response at different frequencies and BER measurement.
system can be implemented using developed SDR-based frame-
work for control of multiple flight object simultaneously.
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Amiya Ranjan Panda (S’14) was born in Odisha,
India, on July 15, 1987. He received the B.Tech.
degree in information technology from Biju Patnaik
University of Technology, Rourkela, India, in
2009, and the M.Tech. degree in computer sci-
ence and engineering from the Kalinga Institute of
Industrial Technology, Bhubaneshwar, India, in 2012.
Currently, he is pursuing the Ph.D. degree at Siksha
“O” Anusandhan University, Bhubaneshwar, India.
Currently, he is a Senior Research Fellow with
the Integrated Test Range, Defence Research, and
Development Organization (DRDO), New Delhi, India, and worked as a Junior
Research Fellow from 2010 to 2012 with DRDO. His research interests include
real-time data acquisition, communication, software defined radio, and flight
termination system.
Debahuti Mishra received the B.Tech. degree
in computer science and engineering from Utkal
University, Bhubaneshwar, India, in 1994; the
M.Tech. degree in computer science and engineering
from the Kalinga Institute of Industrial Technology
Deemed University, Bhubaneshwar, in 2006; and
the Ph.D. degree in computer science and engi-
neering from Siksha “O” Anusandhan University,
Bhubaneshwar, in 2011.
She is an Associate Professor with the Department
of Computer Science and Engineering, Institute of
Technical Education and Research (ITER), Siksha “O” Anusandhan University.
Her research interests include data mining, data acquisition, bioinformatics,
software engineering, soft computing, and machine learning. She has con-
tributed three books and more than 65 research level papers to many national
and international journals and conferences.
Hare Krishna Ratha (M’14) received the B.Tech.
degree in electronics and telecommunication engi-
neering, and the M.Tech. degree in telecommunica-
tions system engineering from Sambalpur University,
Sambalpur, India, and the Indian Institute of
Technology (IIT) Kharagpur, Kharagpur, India, in
1988 and 1996, respectively.
He had been working as a Scientist with Defence
Research and Development Organization, New Delhi,
India, for the last 25 years in various capacities.
Currently, he is an Additional Director with the
Integrated Test Range, Defence Research, and Development Organization, New
Delhi, India. His research interests include various range technologies like
real-time data acquisition, communication, computing, and flight termination
system.