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Published in IET Power Electronics
Received on 12th September 2013
Revised on 9th January 2014
Accepted on 20th January 2014
doi: 10.1049/iet-pel.2013.0704

ISSN 1755-4535

Cascaded three-phase pulse-width modulated

switched voltage source inverter
Charles I. Odeh1, Vincent N. Agu2, Nentawe Goshwe3
1
Department of Electrical Engineering, University of Nigeria, Nsukka, Nigeria
2
Department of Electrical Engineering, Nnamdi Azikiwe University, Akwa, Nigeria
3
Department of Electrical and Electronic Engineering, Federal University of Agriculture, Makurdi, Nigeria
E-mail: charles.odeh@unn.edu.ng

Abstract: A cascaded three-phase pulse-width modulated (PWM) switched voltage source inverter topology is proposed. Each of
the two cascaded units in a phase-leg is an H-bridge, whose switch legs are separated by a switched capacitor and a diode. Three
upper H-bridges in this inverter configuration have separate dc inputs; whereas the lower three H-bridges share a common dc
input. A single-carrier, multilevel PWM scheme is employed to generate the gating signals for the power switches. The
implemented modulation scheme is hybridised to enable the output voltage of the proposed inverter configuration inherit the
features of switching-loss reduction from fundamental PWM, and good harmonic performance from multiple sinusoidal
PWM. A sequential switching scheme is embedded with the already employed hybrid modulation in order to overcome
unequal switching losses. Furthermore, a simple base PWM circulation scheme is also introduced to get a resultant sequential
switching hybrid PWM circulation that balances power dissipation among the two cascaded power modules. The proposed
inverter configuration was subjected to an R–L load. Fast Fourier transform analyses of the output voltage waveforms gave
total harmonic distortion value of 12.64%. Simulations and experiments are carried out on a 4.89 kW rated prototype of the
proposed inverter.

1 Introduction switching devices; many isolated DC sources and link

Nowadays, the multilevel inverters have received more
attention for their ability on high power and medium
voltage applications. This type of inverters has several
advantages such as high power quality, lower order
harmonics, lower switching losses and better
electromagnetic interference.
The concept of multilevel converters has been introduced
since 1975 [1]. The term multilevel began with the
three-level converter [2]. Subsequently, several multilevel
converter topologies have been developed [3–10]. However,
the elementary concept of a multilevel converter to achieve
higher power is to use a series of power semiconductor
switches with several lower voltage dc sources to perform
the power conversion by synthesising a staircase voltage
waveform. Bank of capacitors, batteries and renewable
energy voltage sources can be used as the multiple dc
voltage sources. The commutation of the power switches
aggregate these multiple dc sources in order to achieve high
voltage at the output; however, the rated voltage of
the power semiconductor switches depends only upon the
rating of the dc voltage sources to which they are
connected. The conventional multilevel inverter topologies
have some undesirable features such as fluctuation of the
neutral point voltage due to difference in the switching
characteristics; over-voltage problems across the inner
voltage controllers, and so on.
To mitigate these drawbacks of conventional multilevel
inverters configurations, a three-level pulse-width
modulated (PWM) switched voltage source (SVS) inverter
was proposed in [11]. Each phase leg is composed of a
main inverter stage and a SVS stage, which includes two
switches, one flying capacitor and one diode. It is capable
of providing three-level output across the load, that is: van =
VS, 0 or –VS. Therefore, the peak value of the phase voltage
is VS, and the peak value of the line-to-line voltage is 2VS.
The phase voltage of the SVS inverter is twice as high as
that of the conventional neutral point clamped inverter and
in addition, it does not have the voltage imbalance problem
[12], which often occurs in conventional three-level
inverters with a divided input source. However, in [11], the
synthesised output line voltage waveforms have high total
harmonic distortion (THD) value of 38.58%. Besides, there
is imbalance/unequal distribution of the switching losses
among the constituting semiconductor switches, which is
the consequence of firing the switches, averagely, with
different sequences of gate signals. Hence, the efficiency
and reliability of this inverter topology are grossly affected
by these two limiting factors for the intended high-power
applications.
In recent years, several topologies with various control
techniques have been presented for single- and three-phase

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cascaded multilevel inverters [13–23]. In all, the driving
objective is to obtain a high level of stepped output voltage
waveforms, which result in low THD, with fewer power
circuit components and/or minimum number of input dc
sources, for high-power applications.
Under these technical backgrounds, this paper presents a
cascaded three-phase PWM SVS inverter configuration,
wherein two of the aforementioned three-level PWM SVS
inverters are connected in series; providing nine voltage
levels per cycle at the inverter line-to-line output terminals.
This is very much similar to the traditional cascaded
H-bridge (CHB) inverter configuration only that in this
proposed topology, the input dc sources have been greatly
reduced when compared with the conventional CHB
inverter, for the same output voltage level. Moreover, this
inverter configuration redresses the limiting factors inherent
in the circuit topology proposed in [11]. The operational
principles and switching functions are analysed. The
simulation and experimental results are presented to verify
the validity of the proposed inverter.
2 Operational principles
2.1 Circuit configuration and operation
The proposed cascaded three-phase PWM SVS inverter,
shown in Fig. 1, is a hybrid of the three-level SVS inverter
in [12] and cascaded multilevel inverter in [24, 25]. The
H-bridge modules in the upper SVS inverter have separate
dc sources; whereas the lower three modules share a
common dc source.
With this arrangement, proper switching of any of the
H-bridge inverter module can produce three output-voltage
levels: Vs, 0, −Vs. It then follows that in each phase leg, a
maximum of five output-voltage levels can be synthesised:
Vs, 2Vs, 0, −Vs and −2Vs. In effect, the line-to-line output
voltage waveforms of nine levels are generated at the load
terminals.
Each module can be independently operated with a single
input source. Considering the upper module in phase ‘a’
leg, the basic operational modes in each of the
constituting H-bridge modules of the SVS inverter are
shown in Fig. 2. Because of the hybrid modulation
technique employed in the switching scheme, two
Fig. 1 Power circuit of the proposed cascaded three-phase PWM SVS inverter
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switching states are used to generate 0 V in the first and
second periods of the output voltages. For this upper
H-bridge module in phase ‘a’ leg in Fig. 2, the
synthesised output voltages and the corresponding
switching states of the active power semiconductor
switches are summarised in Table 1. Table 2 gives a
comparison between the proposed inverter and the
well-known five-level conventional inverter topologies.
Precisely, it can be seen from Table 2 that the proposed
cascaded multilevel inverter structure is a hybrid of the
three basic multilevel inverter configurations; inheriting
improved features from these fundamental topologies. In the
proposed inverter structure, there is: one-third saving in the
number of separate DC sources required for CHB multilevel
inverter; two-third saving in the number of clamping diodes
requirements in diode-clamped multilevel inverter; and
two-third saving in the number of clamping capacitors
required in flying-capacitor multilevel inverter
configuration. This power source reduction leads to
simplified system controllers and minimised charging units
in the case of operating from renewable energy sources. It
should be noted that each of the modules of the SVS
inverter is derived from the basic H-bridge inverter
topology. Consequently, each of the main switching devices
has to withstand the single dc input voltage; and hence,
rated accordingly.
2.2 Modulation scheme
Single-carrier sinusoidal PWM (SCSPWM) scheme is
employed in the generation of the gating signals. The basic
principle of the proposed switching strategy is to generate
gating signals by comparing rectified sinusoidal modulating/
reference signals, at the fundamental frequency, with only
one triangular carrier at the desired switching frequency and
whose peak-to-peak amplitude is Ac. For n-level SCSPWM,
k numbers of rectified sinusoidal modulating signals have
the same fundamental frequency, fm, and amplitude, Am,
with dc bias of Ac as a difference between these signals [26,
27]. The switching/modulation scheme adopted in the
proposed cascaded multilevel inverter is illustrated in
Fig. 3, for phase ‘a’.
Hybrid modulation is the combination of fundamental
frequency pulse-width modulation (FPWM) and
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Fig. 2 Operational modes of the three-level, three-phase SVS inverter

a V1 = VS
b V1 = 0
c V1 = −VS
d V1 = 0

Table 1 Definition of switching states for the proposed SVS inverter

Phase voltage, V1 Switching states

First period Second period

S1aU S2aU S3aU S4aU S1aU S2aU S3aU S4aU

VS on off on off on off on off

0 off off on on on on off off
−VS off on off on off on off on

Table 2 Comparison of the proposed five-level inverter with the well-known five-level inverter topologies on the basis of power circuit
component requirements

Inverter type Proposed inverter Diode-clamped Flying capacitors Cascade H-bridge

main switching device 24 24 24 24

main diodes 6 18 0 0
DC bus 4 1 1 6
balancing capacitor 6 0 18 0

multi-sinusoidal PWM (MSPWM) for each H-bridge module
operation, so that the output inherits the features of
switching-loss reduction from FPWM, and good harmonic
performance from MSPWM. In this modulation technique,
the four switches of each H-bridge cell are operated at two
different frequencies; two being commutated at FPWM,
while the other two switches are modulated at MSPWM;
therefore the resultant switching patterns are the same as
those obtained with MSPWM. The logic signals A and B,
at the fundamental frequency fm, in Fig. 3 are used to
hybridise the modulation process herein.
For long operating-time expectancy and also to modularise
the inverter system, it is important to share the power loss to
every power device in a cell/unit, and furthermore, among all
the cascaded modules. This is one of the key issues the
employed modulation scheme in Fig. 3 covers. A sequential
switching scheme is embedded with the already employed
hybrid modulation in order to overcome unequal switching
losses, and therefore, differential heating among the power
devices in each of the inverter H-bridges. To equalise the
switching losses in these H-bridges, the logic signals C and
D in Fig. 3 are used; whose frequency is half of the
fundamental ( fm/2). These logic signals sequentially make
every power switch, in each H-bridge cell, operating at
MSPWM and FPWM to have equal power loss.
Furthermore, a simple base PWM circulation scheme is also
introduced here to obtain a resultant sequential switching
hybrid PWM (SSHPWM) circulation that balances power

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Fig. 3 Switching pattern for phase ‘a’ of the proposed cascaded three-phase PWM SVS inverter
dissipation among the two cascaded power modules in all the
three phase legs. The square waves E and F at a frequency of
( fm/4) in Fig. 3 are used to achieve this power loss circulation
scheme for phase ‘a’.
It can be observed from the proposed switching waveforms
in Fig. 3 that the concept and implementation of SSHPWM
make the average switching waveform of each switch in a
particular H-bridge cell to be the same. Also, the
implementation of SSHPWM circulation scheme in a
particular phase leg makes the average switching
waveforms of all the switches in the two H-bridge modules
to be the same; while at the same time ensuring equal
average switching waveforms in the level-scaled two
cascaded inverters. As a result, the two cascaded inverter
cells operate in a balanced condition with the same
power-handling capability and switching losses. Moreover,
it is interesting that at the elapse of every two fundamental
periods, the order of output voltage syntheses in the two
cascaded inverter modules, in a particular phase-leg, is
swapped; yet, the overall cascaded inverter output phase
voltage waveform remains the same. In other words, their
respective synthesised output voltage waveforms are
dynamically exchanging positions periodically, so that at
the elapse of every two fundamental periods, first module
becomes the second module, the second becomes the first
as seen from the output voltage waveforms in Fig. 3.
The frequency and amplitude modulation indices
expressions for multilevel inverters [28] still hold for the
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proposed cascaded three-phase PWM SVS inverter
configuration. They are given, respectively, as
fc
Mf = (1)
fm
Am
Ma = (2)
Ac (k − 1)
where fc and Ac are the frequency and peak-to-peak value of
the triangular carrier signal, respectively. fm and Am are the
same defined variables corresponding to the modulating
signals. k is the number of voltage level synthesised in each
phase, per half-cycle; in this case, k = 3. The basic principle
in generating the gate signals begins from the comparison
of the respective modulating signals with the carrier wave.
The actual gate signals are produced by the logical
combinations of the results of such comparisons and the
synchronised base square waveforms, having frequencies of
fm, ( fm/2) and ( fm/4). Note that the first square wave at the
fundamental frequency can be obtained from normal
sinusoidal logic signal. The second square wave at a
frequency of ( fm/2) can be easily obtained from basic J-K
flip-flops configured in toggle mode and clocked at the
fundamental frequency. The last square wave having
frequency of ( fm/4) can be synthesised in a similar way, but
clocked at a frequency of ( fm/2).
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Considering phase ‘a’, the gating signals are then given by the much concerned voltage imbalance problem, which is the
the use of basic logical AND, OR and NOT gates. bane of diode-clamped and flying capacitor multilevel inverter
structure. Consequently, the controller design for the proposed
⎧
     ⎫ multilevel inverter configuration is drastically simplified.
⎪
⎪ T . Rec1 · B + A · C ⎪
⎪
⎪
⎪ ⎪
⎪ Recent work in the literature aimed at improving the
⎪
⎪       ⎪
⎪
⎪
⎪ + . · + · · ⎪
⎪ performance of CHB [29] achieved equal switching loss
⎪
⎨ T Rec1 A B D E ⎪
⎬ dissipation among the power switches within a particular
g1aU = +
 (3) H-bridge module, but not in all the constituting power
⎪
⎪     ⎪
⎪
⎪
⎪ T . Rec2 · B + A · C ⎪
⎪ switches in all the CHB modules. This means that different
⎪
⎪ ⎪
⎪
⎪
⎪         ⎪
⎪ powers are drawn from respective dc power sources and
⎪
⎩+ ⎪
T . Rec2 · A + B · D · F ⎭ also result in unequal rating of power circuit switches. But
the implemented modulation scheme herein results in equal
⎧
 ⎫ switching loss dissipation and equal power sharing in the
    cascaded SVS multilevel inverter modules per phase; and
⎪
⎪ T . Rec1 · A + B · C ⎪
⎪
⎪
⎪ ⎪
⎪ therefore technically modularises the cascaded SVS inverter
⎪
⎪       ⎪
⎪
⎪
⎪ + . · + · · ⎪
⎪ system.
⎪
⎨ T Rec1 B A D E ⎪
⎬
g2aU = +
 (4)
⎪
⎪     ⎪
⎪ 2.3 Analysis of the SVS inverter module
⎪
⎪ T . Rec2 · A + B · C ⎪
⎪
⎪
⎪ ⎪
⎪
⎪
⎪         ⎪
⎪
⎪
⎩+ ⎪ In Section 2.1, it was assumed that the capacitor C is charged
T . Rec2 · B + A · D · F ⎭ to a constant input voltage value, VS; and hence regarded as a
constant voltage source. But in real-time operation, there is a
slight difference between the actual capacitor voltage, VC and
g3aU = g2aU (5)
the input voltage, VS. This slight difference may cause an
inrush current on the switch S1aU and the diode when the
g4aU = g1aU (6) switch S1aU turns on. This possible occurrence is avoided
by placing a very small snubber inductor L between the
⎧
     ⎫ diode and capacitor C. However, this small snubber
⎪
⎪ T . Rec · B + A · C ⎪
⎪ inductor does not affect the operation of the proposed SVS
⎪
⎪ 2 ⎪
⎪
⎪
⎪      ⎪
⎪ inverter.
⎪
⎪ + . · + · · ⎪
⎪
⎪
⎨ T Rec 2 A B D E ⎪
⎬ Fig. 4 shows one of the switching circuits of the SVS
g1aD = + (7) (given in Fig. 2) of the SVS inverter module depicting buck
⎪
     ⎪
⎪
⎪ ⎪
⎪ converter operation. The snubber inductor L is quite small
⎪
⎪ T . Rec1 · B + A · C ⎪
⎪
⎪
⎪   ⎪
⎪ and the buck converter circuits in Figs. 4a and b operate in
⎪ 
⎪    ⎪
⎪ discontinuous conduction mode. In this mode of operation,
⎩+ T . Rec1 · A + B · D · F ⎭ its voltage conversion ratio, M, is expressed as
⎧
     ⎫
⎪
⎪ T . Rec · A + B · C ⎪
⎪ vo 2
⎪
⎪ 2 ⎪
⎪ =M = 
  (11)
⎪
⎪        ⎪
⎪ VS
⎪
⎪ ⎪
⎪ 1 + 1 + (8tL /D2 )
⎪
⎨ + T . Rec 2 · B + A · D · E ⎪
⎬
g2aD = +
(8)
⎪ ⎪ where tL = (L/RTS); TS = switching period; R = load
⎪ T . Rec  · A + B · C 
⎪
⎪
⎪
⎪
⎪
⎪
⎪ 1 ⎪
⎪ resistance; D = duty ratio.
⎪
⎪        ⎪
⎪
⎪
⎩+ ⎪ From (11), the design equation of L can be expressed as
T . Rec1 · B + A · D · F ⎭
 2 
g3aD = g2aD (9) D2 2
L = RTS − 1 −1
8 M
g4aD = g1aD (10)
 2  2  (12)
VC 1 − Ma 2
Deducing from the presented control/modulation strategy, the = T − 1 −1
IL S 8 M
proposed cascaded multilevel configuration does not have

Fig. 4 Operation of the SVS inverter module depicting buck converter

a Half-bridge leg of phase ‘a’
b Powering mode
c Freewheeling mode

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Fig. 5 Simulated phase voltage waveforms

Fig. 6 Simulated line voltage and current waveforms

Fig. 7 Phase ‘a’ upper inverter module capacitor and switches voltages and currents

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Fig. 8 FFT analyses of the synthesised output line voltage
Fig. 9 Power profile of the cascaded inverter system
3 Simulation and experimental results
3.1 Simulation results
The operational principles and the switching scheme of the
cascaded three-phase PWM SVS inverter shown in Fig. 3
and Table 1 have been investigated by MATLAB
SIMULINK simulation. A balanced three-phase star
connected R–L load with 30 Ω resistance and 96 mH
inductance per phase were used.
Figs. 5 and 6 show the simulated inverter output voltage
and current waveforms at carrier frequency of 3 kHz and
input voltage of 200 V. The phase voltage waveforms
exhibit five levels: 2VS, VS, 0, −VS, −2VS; whereas the
line-to-line voltage waveforms show nine levels: 4VS, 3VS,
2VS, VS, 0, −VS, −2VS, −3V, −4V as earlier predicted. For
the upper inverter module in phase ‘a’ leg, the switches and
capacitor voltages and currents waveforms are shown in
Fig. 7. This figure depicts equal peak current handling
capability in the power switches.
The performance index, namely THD is chosen to assess
the quality of the synthesised inverter output waveforms.
Spectral analysis of one of the inverter line voltage
waveforms in Fig. 6 is carried out. The spectral results are
displayed in Fig. 8, wherein a THD value of 12.64% is
achieved in the line voltage waveform. Fig. 9 shows the
power profile of the cascaded SVS inverter modules of
phase ‘a’. Obviously, this figure depicts equal power
handling capability among the cascaded SVS inverter
modules.
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3.2 Experimental results
A scaled laboratory prototype has been built for verification
of cascaded three-phase PWM SVS inverter. Four 200 V
stiff dc power source are employed as the dc supplies for
the input voltages. A 96 mH inductor in series with a 30 Ω
resistor are connected at the output terminal of each phase.
The aforementioned modulation scheme is implemented by
using basic CMOS logic gates and TL 084 IC and hence,
the 24 gating pulses were generated. The prototype
specifications are given in Table 3.
Fig. 10 shows experimentally obtained gating signals and
output voltages of phase ‘a’ leg. Fig. 11 shows the
experimental waveforms of the inverter output phase and
line voltages. For the specified loading condition in
Table 3, the line voltage and current waveforms are shown
in Fig. 12.
For the specified operating condition, Table 4 gives the
measured parameters of the implemented prototype.
For a cycle, the phase and line voltage waveforms exhibit
five and nine levels, respectively, as earlier proposed for
these output voltages.
Table 3 Prototype specification
power switches: IXYS FII 40-06D
fast switching diodes: STTH12012TVL
Rload = 30 Ω, Lload = 96 mH
C = 3900 μF, 400 V
L = 0.25 μH
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Fig. 10 Experimental gate signals and output voltages for phase a

a g1aU (channel 1), g2aU (channel 2), g1aD (channel 3), g2aD (channel 4)
b V1 (channel 3), V2 (channel 4), Vag (MATH)

Fig. 11 Experimental output voltages

a Phase voltages
b Line voltages

Fig. 12 Experimental output voltages and currents

a Line voltages and currents
b Line currents

4 Conclusions
Table 4 Parameters of the implemented prototype
A three-phase multilevel inverter configuration with reduced
output line voltage (rms): 565.7 V
load current (rms): 7.07 A
number of input dc sources for medium and high-power
measured output power: 4.89 kW applications has been presented. The proposed inverter
generates five-level output phase voltages with only four dc

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input sources for a three-phase system. The operational
principles and switching functions generation have been
discussed in detail. It has been shown that the modulation
method adopted enables the proposed inverter output
voltage to inherit the features of switching-loss reduction
from FPWM, and good harmonic performance from
MSPWM. Moreover, equalising the switching losses among
the power semiconductor switches has been achieved.
Consequently, the proposed cascaded multilevel inverter
topology has been modularised. The synthesised output line
voltage of the proposed inverter achieved a better harmonic
profile of 12.64% THD. The performance of the proposed
inverter topology has been presented through simulations
and experiments on a 4.89 kW rated prototype of the
proposed inverter for an R–L load. The results have been
adequately presented.
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