Design and Implementation of a Low-Power

Intensity Pulsed-Ultrasound Generator for

Dental Tissue Regeneration
Woon Tiong Ang, Cristian Scurtescu, Wing Hoy, Tarek El-Bialy, Ying Tsui and Jie Chen
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada

orthodontists. Previous finding of LIPUS‘s ability to enhance healing

Abstract— This paper presents the design and
implementation of a Low-Intensity Pulsed Ultrasound (LIPUS)
generator for dental tissue regeneration. It consists of a power
supply subsystem, an ultrasonic transducer, an
impedance-matching circuit and an integrated circuit consisting of
digital controller circuitry and driver circuit. The integrated
circuit was designed and fabricated using 0.8m High-Voltage
Technology from Dalsa Semiconductor Inc. The power supply
sub-system and impedance matching network are implemented
using discrete components. Upon construction, the LIPUS
generator was verified to function correctly and is capable of
producing LIPUS power upwards of 100mW in the vicinity of the
transducer’s resonance frequency. Power efficiency of the
circuitry, excluding the power supply sub-system, is estimated at
70%.
Index Terms—Low Intensity Pulsed Ultrasound (LIPUS),
Ultrasonic Generator, Dental Tissue Regeneration.
I. INTRODUCTION
of various types of traumatized connective tissues and stimulate dental
tissue formation has led El-bialy et. al [6] to study the effect of LIPUS
on root resorption. The study showed healing of the resorbed root
surface and confirmed the effectiveness of LIPUS in providing a
non-invasive method for reducing root resorption in humans [6].
However, commercial LIPUS generators are generally bulky devices
which do not lend themselves viable for embedded or wearable
applications. In this paper, the design and implementation of a portable
LIPUS generator is presented. Although not fully-integrated, this
design requires minimal off-chip components and thus makes
miniature system-in-package (SIP) solution possible.
II. LIPUS SYSTEM DESIGN
The design goal for the generator is to produce LIPUS signal of the
following specifications (as used in [6]):
1. Intensity= 30mW / cm2
2. Ultrasonic frequency=1.5MHz
3. Pulse Repetition Rate=1kHz
4. Pulse Duty Cycle=20%

U ltrasound has been widely used in biomedical application. Positive

Voltage
Applications of ultrasound for medical purposes include both Regulator Vpp
low intensities and high intensities. In ultrasonography [1], i.e.
ultrasound-based diagnostic medical imaging, the principles of
non-destructive testing are used to visualize internal organs and tissues Dual Stepped-up
Rail Power AC Signal
within. An ultrasound generator consisting of phased arrays sweeps an Voltage Signal Signal
Output
Impedance
Transform
ultrasonic beam over the region of investigation. The reflected Supply Generator Amplifier Network
Stage
ultrasound is used to construct the image. It is frequently used to detect
0V
anomalies in human body and during pregnancy to visualize the
development of fetus.
Many therapeutic applications of ultrasound are also known. Negative
Voltage 0V
Therapeutic ultrasound is being used to treat various soreness and Regulator -Vpp
injuries in athletes. It is used after injections to disperse the injected Legend:
fluids [2]. It has been used effectively for treatment of rheumatic On-chip
diseases [2]. Due to its heating effect, ultrasound is also used for the Components
treatment of hypothermia. Ultrasound-enhanced delivery of
therapeutic agents such as genetic materials, proteins and Off-chip
chemotherapeutic agents is another ever-increasingly important Components
application of ultrasound [3]. High-Intensity Focused Ultrasound Figure 1: Proposed architecture for LIPUS generator showing the
(HIFU) is used in the treatment of tumors by rapidly heating and scope of chip-level integration
destroying pathogenic tissues. HIFU treatment for uterine fibroids was
approved by the Food and Drug Administration (FDA) in October To achieve this objective, an architecture is proposed as shown in
2004 [4]. It has also been successfully applied to the treatment of Figure 1. In an effort to increase the portability of the LIPUS
various types of cancers [5]. generator, the signal generator, signal amplifier and power output
Another form of ultrasound known for its therapeutic effect stage are integrated on chip. The voltage regulators block, though
is Low-Intensity Pulsed Ultrasound (LIPUS). Recently, published capable of on-chip implementation in principle, requires relatively
results have shown that Low-Intensity Pulsed Ultrasound (LIPUS) has large capacitors which take up significant chip area. It is deemed
the potential for treating orthodontically-induced tooth-root resorption sufficient in this project that this block be left off-chip. Similarly, the
[6]. Root resorption is an adverse consequence of orthodontic tooth impedance transform network is implemented using discrete
movement and has led to increased malpractice litigation against components because the large values of inductance and capacitance

978-1-4244-3828-0/09/$25.00 ©2009 IEEE 2421

require rather large on-chip components. The scope of integration of
the proposed architecture is shown in Figure 1.
III. IMPEDANCE TRANSFORM NETWORK
Different circuit topologies can be used as an impedance transform
network using only inductors and capacitors. An L-match circuit (see
Figure 2) is deployed in the LIPUS generator circuit because of its
simple implementation. By transforming impedance of the load RL ,
the impedance transform network consisting of LIT and CIT can
effectively amplify input voltage signal by a factor of n for driving the
load. The inductance LIT and capacitance CIT values depend on the
voltage amplification factor n desired, and also on the load
resistance RL . For the values shown in Figure 2, a gain of 3 is
achieved.
00100101100 produces the pulse with a duration of 300 clock cycles
and a null with a duration of 1200 clock cycles. This is designated as
such because binaries 10010110000 and 00100101100 are
equivalent to 1200 and 300 respectively in decimal number system.
Instead of assigning 24 input pins on the integrated circuit for the input
of the pulse configuration pattern ―p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11
p12‖ and ―n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12‖, it was decided
that the configuration pattern would be clocked into the integrated
circuit serially to conserve the number of external connection pins. To
accomplish this, a serial-to-parallel register is used (refer to Figure 3)
which has two input pins (Pulse_setting and Program_CLK) and 24
output nodes connecting to ―p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12‖
and ―n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12‖ nodes on the tristate
buffer. The ‗Program_CLK‘ signal and the ‗Pulse_setting‘ data are to
be supplied by external hardware during the ‗programming‘ or
‗start-up‘ phase of circuit operation.
Vhigh

LIT  1 H Modulator
Voutf
Level-Shifter
Transducer
Vp Vn Ext_CLK CLK_SEL CLK

CIT  9nF
CLK Vdd
MUX J
Ring VCO K
JK-Flip Flop
Q
(Pulse-Triggered)

Delay
Reset_b Delay
System_reset_b

Figure 2: L-match circuit for voltage gain of three

a1 b1 Q1 EN
Reset_b Q2
n1
a2 b2 n2
a3 b3 Q3
n3
IV. PULSE-MODULATED SIGNAL GENERATOR a4 b4 Q4

Comparator
Q5 n4
a5 b5

Register
Counter

n5

Tristate
Buffer
a6 b6 Q6
n6
INTEGRATED CIRCUIT a7
a8
a9
b7
b8
b9
Q7
Q8
Q9
n7
n8
n9
a10 b10 Q10
a11 b11 Q11 n10
The design goal of the targeted integrated circuit is to produce CLK
a12
Equal
b12 Q12
n11
n12

pulse-modulated signal of sufficient amplitude to drive a piezoelectric EN p1 p1 n1

CLK
transducer through the impedance transform network designed in the p2 p2 n2

Serial-to-Parallel
p3 p3 n3
p4 p4 n4
p5
previous section. A means of varying signal frequency and pulse duty
p5 n5

Tristate
Buffer
p6 p6 n6
p7 p7 n7
p8 p8 n8
cycle is to be provided. Our preliminary investigation showed that p9
p10
p9
p10
n9
n10
p11 p11 n11
7.6V voltage amplitude is required to generate sufficient acoustic p12 p12 n12

power intensity and given that the impedance transform network

provides a gain of three at resonance, a sinusoidal voltage of amplitude

2.53V (peak-to-peak magnitude of 5.06V) needs to be generated, in
principle, by the integrated circuit. This voltage requirement is beyond
the normal operating regime of most mainstream fabrication
technologies. In order to guarantee the generation of at least the
above-mentioned voltage, the 0.8µm CMOS/DMOS technology
available at Dalsa Semiconductor Inc. was selected for this project.
This technology enables the use of both low-voltage CMOS and high
voltage DMOS processes capable of high voltages up to and beyond
100V. Thus, it was expected to offer a solution for integrating
low-voltage digital controller and high-voltage driver on a chip.
Circuit Design and Implementation
A detailed RTL-level realization of the architecture proposed is
presented in Figure 3. The functionality and implementation of
selected modules are described in the following:
A. Signal Generator
The signal generator is realized using a ring voltage-controlled
oscillator (VCO), which also is used to generate the clock signals
(CLK) for the entire digital circuit. The circuit implementation of the
ring VCO is based on [7].
B. Pulse Generator
The pulse generator is realized using a counter, a comparator, two
tristate buffers and a JK-Flip Flop arranged as shown in Figure 3. The
pulse repetition rate and duty cycle of the resulting signal are
controlled via the nodes ―p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12‖
and ―n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12‖ respectively. For
example, setting ―null width‖ to 10010110000 and ―pulse width‖ to
Pulse-setting data
Program-CLK
Equal
System_reset_b
Figure 3: Pulse-modulated Signal Generator Integrated Circuit
Signal Amplifier and Power Output Stage
In order to amplify low-voltage digital control signal to high-voltage
driving signal, a level-shifter is used. In this capacity, the level-shifter
can realize the functions of both the voltage amplifier and the power
output stage. Level-shifting techniques have been studied in [8], [9],
[10] and applied to CMOS/DMOS technology for generating high
voltages in [11]. The design described here is directly adapted from
[11]. As shown in Figure 4, the level-shifter is symbolically realized
using two p-channel DMOS transistors (A and C) and two n-channel
DMOS transistors (B and D). Transistors A and B are responsible for
generating suitable driving voltage to turn on and off transistor C. The
operation of transistor D is directly controlled by the digital input to
the level-shifter through an inverter. Transistors C and D drive the
piezoelectric load through an impedance transform network.
V. CHIP LAYOUT
The finished layout of the pulsed signal generator circuit is shown in
Figure 5. The circuit is implemented using 0.8m high-voltage
technology from Dalsa Semiconductor.

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 Vhigh Vhigh LM317
9V Positive +4V
Voltage
Power output stage Regulator
Internal
driver C
A Vhigh 9V
Vlow Vdd Vpp
Voutf LM317
Positive
B D Voltage
Regulator
Vn

Vss Vss Vp
-4V Pulsed LIT  1 H
Vss Vss Carrier
Voutf
Integrated
Circuit
CLK_sel
LM317 CIT  9 nH
Positive Vss
Figure 4: Level-shifter Circuit Voltage
Regulator
9V

-4V
System_reset_b Pulse_setting Program_CLK

LM337
Negative
-9V Voltage -4V PB0 PB2 PB3
Regulator

AVR Butterfly
Board

Gnd Vdd

Figure 6: Circuit diagram of board-level circuit

Figure 5: Pulse-modulated signal generator integrated circuit

layout

VI. BOARD-LEVEL INTEGRATION

The pulse-modulated signal generator chip is integrated on a
breadboard for testing. The circuit diagram of the testing circuitry is
shown in Figure 6. An AVR Butterfly board (containing an Atmel
Mega169PV microcontroller) is used to generate the pulse-setting
serial stream and a corresponding programming clock for the Figure 7: Voltage waveform at the Voutf pin of the pulse-modulated
fabricated integrated circuit. During initialization, 100101100002 signal integrated circuit
(300 in decimal number system) and 001001011002 (1200 in
decimal number system) are clocked into the pulse-setting module of
the integrated circuit serially every time the Atmel Mega169PV
microcontroller is powered up. Thus, the fabricated pulse-modulated
signal generator chip is programmed to output a pulsed-modulated
ultrasonic signal of 20% duty cycle (i.e. 300 clock cycles of
oscillation, and 1200 clock cycles of ‗null period‘).

VII. CIRCUIT TEST AND MEASUREMENTS

Upon power up and completion of the initialization routine in the
AVR Butterfly board, the voltage across the transducer is probed and
displayed on an oscilloscope. After some tuning of the controlling
voltage on the voltage-controlled oscillator (VCO), an ultrasonic
signal frequency of 1.5MHz is generated by the CLK pin of the chip
(see Figure 7). The pulse duty cycle measured at the Voutf pin is 20%
as expected. The pulse waveforms of both current and voltage are
shown in Figure 8. Figure 8: Voltage(A) overlayed with current (B) pulses with 200  s
pulse width and 800  s null width

2423

Finally, an ultrasound power meter is used to measure the
acoustic power of the LIPUS generated. With the pulse duty cycle and
supply voltage fixed, acoustic power measurement is performed for the
following signal frequencies: 1.46MHz, 1.48MHz, 1.52MHz and
1.55MHz. The measurement results are summarized in Table 1.
Signal Frequency (MHz) Acoustic Power (mW)
1.46 72
1.48 86
1.50 116
1.52 118
1.55 110
Table 1: Acoustic power measured at 20% duty cycle for different
ultrasonic frequencies
It is observed from the measurement that maximum power
(118mW) is generated at 1.52MHz. This translates to an intensity of
66.7 mW / cm2 which more than satisfies the required minimum
intensity. Other power levels can be easily obtained by adjusting the
voltage regulators to supply a different DC supply voltage. The
average power delivered to the ultrasound generator (excluding that of
the voltage regulators) is estimated at 800mW. This gives an overall
efficiency of overall  14% . Transducer efficiency transducer at
1.5MHz is determined experimentally to be approximately 20%.
Therefore, the power efficiency of the ultrasound generator circuitry
(excluding the transducer) works out to be approximately 70%.
VIII. PRELIMINARY BIOLOGICAL RESULTS
In our previous study [6], we discovered that LIPUS can enhance
dental tissue formation. We hypothesize that local stem cell expansion
and/or differentiation attribute to dental tissue formation. To test this
hypothesis, a LIPUS device with characteristics similar to [6] was
applied to bone marrow stem cells (BMSCs) for 20, 40 and 60 minutes
per day. Our preliminary results showed that daily application of
LIPUS to BMSCs increased cell count (Figure 9) and alkaline
phosphatase (ALP) activity (Figure 10). ALP is an early ossification
marker and usually indicates early differentiation of osteogenic [bone
forming cells]/cementogenic [cementum forming cells] phenoltyping.
Figure 9: Cell count of BMSCs after 20, 40 and 60 minute after
LIPUS application for two weeks. We can see that there is a
consistent increase in cell count of BMSCs with LIPUS application.
Note the cell count is different for each control sampe.
Figure 10: Increased ALP activity with LIPUS either with basic
medium (BM [DMEM + 10% FBS + 1% pen-strep fungizone]) or with
osteogenic medium (Osteo)[Basic medium + 50ug/ml ascorbic acid +
2-phosphate + 10 nm dexamethazone + 7mM + 1 μg/ml BMP-2]].
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IX. CONCLUSION
A LIPUS generator has been designed and implemented. It is made up
of an integrated circuit capable of pulse-modulated signal generation, a
power supply sub-system, an impedance matching network, and a
piezoelectric transducer. The integrated circuit was fabricated using
0.8m High-Voltage Technology from Dalsa Semiconductor Inc. The
power supply sub-system and impedance matching network are
implemented using discrete components. An L-match circuit is used to
realize the impedance matching network and it allows for accurate
delivery of power to the transducer for LIPUS generation. The LIPUS
generator was verified to function correctly. Even though the LIPUS
generator was designed for 1.5MHz pulsed-ultrasound with 1kHz
pulse repetition rate an 20% pulse duty cycle, it could be
reprogrammed using external hardware. At the designated operating
state, the generator produced LIPUS of up to 116mW. In addition, the
power efficiency of the circuit (excluding the power supply
sub-system) is estimated at 70%. The biological test results show that
the LIPUS device stimulates both osteogenic and cementogenic cell
formation and results in new dental tissue formation.
ACKNOWLEDGEMENT
The authors would like to acknowledge Ms. Bernadette Oreski for
her valuable feedbacks in the project. We also would like to
acknowledge NSERC Idea to Innovation grant and Alberta Heritage
for Medical Research (AHFMR) forefront grant for supporting this
project.
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[5] www.hifu.ca
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