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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
A Doherty Power Amplifier Design Method for
Improved Efficiency and Linearity
William Hallberg, Student Member, IEEE, Mustafa Özen, Member, IEEE, David Gustafsson,
Koen Buisman, Member, IEEE, and Christian Fager, Senior Member, IEEE
Abstract— A novel Doherty power amplifier (PA) design
method enabling high efficiency and high linearity simultaneously
is proposed. The output combiner network is treated as a black
box, and its parameters, together with the input phase delay,
are solved based on given transistor characteristics and design
requirements. This opens for new PA solutions with noncon-
ventional Doherty behavior. The increased design space enables
new tradeoffs in Doherty PA designs, including solutions with
both high efficiency and high linearity simultaneously. A method
utilizing the new design space is developed. For verification,
a 20-W 2.14-GHz symmetrical gallium nitride high electron
mobility transistors Doherty PA is fabricated and measured.
The PA obtains an average power added efficiency of 40%
and an adjacent power leakage ratio of −41 dBc without any
linearization for an 8.6-dB peak to average power ratio
10-MHz-long term evolution signal, at an average output power
of 35.5 dBm.
Index Terms— AM/AM, AM/PM, Doherty power ampli-
fier (DPA), energy efficiency, gallium nitride (GaN), high
electron mobility transistors, long term evolution (LTE), power
amplifier (PA).
I. I NTRODUCTION
M AINTAINING high efficiency over a large output
power range is a required attribute for power ampli-
fiers (PAs) transmitting signals with high peak to average
power ratios (PAPRs). High efficiency at both maximum
and backed-off power levels can be achieved by dynamically
modulating the load impedance of the transistor. The Doherty
PA is a common architecture based on this principle [1]–[3].
Modulating the load for a single transistor will cause a
nonlinear gain response. However, this is not a problem for the
Manuscript received June 29, 2016; revised September 22, 2016; accepted
October 8, 2016. This work was carried out under the Energy Efficient Milime-
ter Wave Transmitters (EMIL) project financed by the Swedish Governmental
Agency of Innovation Systems (VINNOVA), Ericsson AB, and the Chalmers
University of Technology. An earlier version of this paper was presented at the
IEEE MTT-S International Microwave Symposium, San Francisco, CA, USA,
May 22–27, 2016.
W. Hallberg, K. Buisman, and C. Fager are with the Department of
Microtechnology and Nanoscience, Chalmers University of Technology,
SE-412 96 Gothenburg, Sweden (e-mail: wilhal@chalmers.se; buisman@
chalmers.se; christian.fager@chalmers.se).
M. Özen is with the Department of Microtechnology and Nanoscience,
Chalmers University of Technology, SE-412 96 Gothenburg, Sweden,
and also with the Department of Electrical and Computer Engineering,
University of California at San Diego, San Diego, CA 92093 USA
(e-mail: mustafa.ozen@chalmers.se).
D. Gustafsson is with Ericsson AB, SE-417 56 Gothenburg, Sweden (e-mail:
david.a.gustafsson@ericsson.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2016.2617882
0018-9480 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
ideal Doherty PA. The Doherty PA consists of two transistors,
where both the transistors mutually modulate each other to
obtain the maximum efficiency at the maximum power, and at
a γ dB backed-off power level. Consequently, the individual
transistors’ gain response will be nonlinear. However, when
the outputs of the two transistors are combined, the over-
all Doherty PA circuit will, for ideal transistors, present a
completely linear gain response. However, in practice, it is
difficult to achieve an ideal gain response due to transistor
nonlinearities and parasitics. The nonlinearities and parasitics
of real transistors will also cause phase distortion in the
Doherty PA. In the low power region, where only the main
transistor is conducting, the phase distortion of the Doherty
PA follows the phase distortion of a single-ended PA. In the
high power region, where both transistors are conducting, the
Doherty PA will present severe phase distortion. In this region,
the load modulation will cause a dominating phase distortion
due to the Miller effect [4]–[6].
Nonlinear gain and phase responses result in unwanted
spectral regrowth and in-band distortion for modulated signals.
One method of addressing this problem is to cancel intermod-
ulation products by having the intermodulation products from
the main transistor add up with the intermodulation products
from the auxiliary transistor at the load destructively [7]–[9].
Third- and fifth-order intermodulation (IM3 and IM5) can-
cellation at the load of the Doherty PA can be achieved by
optimizing the biases of the main and auxiliary transistors.
The optimum bias levels for intermodulation cancellation
at the load do not necessarily coincide with the best bias
levels for efficiency. Therefore, it has been demonstrated that
intermodulation cancellation at the load can be accomplished
in an N-way Doherty PA, where the extra auxiliary transistors
increase the design space [10], [11]. An N-way Doherty PA
does, however, increase both the complexity and circuit size.
Intermodulation distortion can also, to some extent, be reduced
by optimizing the baseband terminations for a single transis-
tor [12], [13], and therefore possibly also for a Doherty PA.
Another method of reducing spectral regrowth is naturally
to improve the linearity of the gain and phase responses of the
Doherty PA. In [4] it was shown that the phase distortion of
the Doherty PA can be reduced by source mismatching. This
will obviously reduce the gain of the PA. Since the Doherty
PA suffers from severe gain reduction due to the input power
splitter, lowering the gain even further is unwanted.
For a conventional Doherty PA [14]–[16], the phase of
the load termination voltage is only dependent on the phase of
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2 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

the main transistor current [5]. Thus, it is not possible to adapt

the complex auxiliary transistor current to improve the Doherty
PA phase linearity. However, by modifying the Doherty PA
operation, it is possible to improve the phase linearity by
means of the auxiliary transistor. In [17] and [18], it was shown
that treating the output combiner network as a black box and
solving its parameters, together with the input phase delay,
for given boundary conditions opens up the possibility to find
new Doherty PA solutions with current profiles deviating from
the conventional design. Among these, some have a lower
maximum auxiliary transistor drain current compared to the
conventional case for a given γ . These new solutions will
hereafter be referred to as current scaled Doherty PA solutions.
Hallberg et al. [19] recently showed that these current scaled
solutions enable improved phase linearity of the Doherty PA.
It was shown that the inherent nonlinear phase response of
the current scaled Doherty PA can be utilized to counteract
the inherent nonlinear phase distortion due to the Miller effect
and transistor nonlinearities. It was also shown that a linear
gain response can be obtained simultaneously.
In this extended paper, the novel design method of finding
new current scaled Doherty PA solutions that simultane-
ously provide low AM/PM and AM/AM distortion, and high
efficiency is explained thoroughly. In particular, the theory of
current scaling is expanded by further analysis on ideal tran-
sistors. In the methodology, the different steps are presented
in a design flowchart and, in more detail, new tradeoffs are
presented. Furthermore, more experimental investigations of
the gallium nitride (GaN) transistor PA circuit prototype are
presented.
This paper is organized as follows. In Section II, the analysis
and derivation of the black-box output combiner network are
presented. In Section III, the linearity and efficiency of the
current scaled Doherty PA are studied. The novel design
method is presented on a general level in Section IV and
the method is applied on GaN transistors in Section V. The
resulting current scaled Doherty PA solution is fabricated and
the measurement results are presented in Section VI. Finally,
the conclusions of this paper are presented in Section VII.
II. O UTPUT C OMBINER N ETWORK
In this section, the method of treating the output combiner
network of the Doherty PA as a black-box combiner is
presented. Treating the output combiner as a black box vastly
increases the design space of the Doherty PA by allowing new
current ratios for a given γ . In [17] and [18], the extended
design space is explored in terms of finding the maximum
efficiency of two symmetrical transistors. In [19], another
subset of the design space was explored to find solutions with
both high efficiency and high linearity. In [19], the formulation
of the derivation of the black-box combiner parameters was
adapted to match the needs of the novel design method. The
adapted formulation is included and expanded below.
In the conventional Doherty PA design, the maximum
fundamental intrinsic auxiliary transistor drain current Ia,i,Pmax
relates to the maximum fundamental intrinsic main transistor
drain current Im,i,Pmax , according to [15], [16]
√
Ia,i,Pmax = ( γ − 1)Im,i,Pmax (1)
Fig. 1. Generalized black-box representation of the output combiner network
of the Doherty PA. The black-box combiner can be represented by a reciprocal
two-port network Z with the load termination inside (left) or a lossless and
reciprocal three-port network Ẑ with the third port terminated with a resistive
load (right).
where γ is the predetermined backed-off power level where
the second efficiency peak will occur. The black-box method
presented in [17] and [18] demonstrates that the main and
auxiliary current ratio can be completely separated from γ .
Thus,
Ia,i,Pmax = rc Im,i,Pmax (2)
where rc is an arbitrary current ratio. It is reasonable to
assume that the fundamental intrinsic drain voltage swing is
equal at maximum power for the main transistor and for the
auxiliary transistor. This makes it possible to directly transform
the current relationship in (2) into a relationship of powers.
The intrinsic power ratio can be approximated as equal to the
extrinsic power ratio
Pa,Pmax = rc Pm,Pmax . (3)
The first step in the black-box method is to represent
the output combiner of the Doherty PA as a reciprocal
two-port network with the load termination inside (see Fig. 1).
This lossy and reciprocal two-port network must have the
possibility to be converted into a lossless and reciprocal three-
port network with the third port terminated with a resistive
load. This will be discussed in more detail later in this section.
If the conventional Doherty current relationship is fulfilled, and
if output parasitics are compensated for, the solution to the
reciprocal two-port network will be the conventional quarter-
wave transformer combiner network. Ergo, the conventional
Doherty PA is a subset of the current scaled Doherty PA
continuum of solutions.
The two-port output combiner network parameters Z are
found from
Z 11 + Z 12 α1 = Z L ,m,Pmax (4)
Z 22 + Z 12 /α1 = Z L ,a,Pmax (5)
Z 11 + Z 12 α2 = Z L ,m,Pbo (6)
Z 22 + Z 12 /α2 = −Z OFF,a (7)
where Z L are the load impedances for the main (m) and
auxiliary (a) transistors at maximum output power (Pmax )
and at a predetermined output power back-off (OPBO) – Pbo .
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY
Z OFF,a is the output impedance of the auxiliary transistor when
it is turned OFF, i.e., at the power level Pbo and levels below.
Z OFF,a can be approximated as a static value and can be
obtained from S-parameters. The parameters α1 and α2 are
defined as

Ia,Pmax {Z L ,m,Pmax }Pa,Pmax − j θ
α1 = = e (8)
Im,Pmax {Z L ,a,Pmax }Pm,Pmax
Ia,Pbo Z 12
α2 = =− (9)
Im,Pbo Z OFF,a + Z 22
where Im and Ia are the fundamental output currents of
the main and auxiliary transistors, respectively; Pm and Pa
are the output powers of the main and auxiliary transistors,
respectively; and θ is the phase offset between the output
currents of the two transistors. It is important to mention
that the analysis above can be done either intrinsically or
extrinsically. Because the output combiner can be solved in
terms of extrinsic load impedances, many possible solutions
to the Doherty PA can quickly be completely evaluated directly
from load–pull data.
The conversion from a lossy and reciprocal two-port
network Z to a lossless and reciprocal three-port network Ẑ
with the third port terminated with a resistive load results in an
underdetermined system of equations where Ẑ 33 can assume
any imaginary value. The imaginary value of Ẑ 33 will only
result in a static phase difference for the voltage Vl across Rl .
In Appendix B, the remaining three-port network parameters
are derived in terms of the two-port network parameters Z,
Ẑ 33 and the load termination Rl . The conversion from
two- to three-port representation imposes the following
constraint [18]:
{Z 12 }2 = {Z 11 }{Z 22 }.
This allows the phase offset between the output currents of
the two transistors, i.e., θ , to be determined with four possible
solutions. The solutions of θ have the following form:
 network parameters (see Appendix B)
±θx
θ= (11)
±(π − θx ).
When solving the two-port combiner parameters, all the
equations above come down to three equations with three
unknowns. The two-port output combiner network parame-
ters are functions of Z L ,m,Pmax , Z L ,a,Pmax , Z L ,m,Pbo , Z OFF,a ,
Pm,Pmax and Pa,Pmax , which are all found from either measure-
ments or simulations. The solutions to the two-port network
parameters can be found in Appendix A.
Due to parasitics, a real transistor will shift the phase from
the input to the output. This phase shift will depend on the
bias, transistor size, power level, and terminations. Therefore,
the physical input phase delay ϕin must be set to fulfill
α1 = −ϕin − ϕa,Pmax + ϕm,Pmax = −θ
where ϕm and ϕa represent the main and auxiliary transistor
phase shifts, respectively.
The output combiner parameters are functions of load
impedances at two power levels. The total output power from
3
both transistors at both the power levels are related by
Pmax = γ Pbo . (13)
The auxiliary transistor should be turned OFF at the backed-off
power level, thus the equation above can be expanded to
Pm,Pmax + Pa,Pmax = γ Pm,Pbo . (14)
The input powers will be related to each other in the following
section, when the gain response is discussed.
There are many ways of realizing the lossy and reciprocal
two-port network or the equivalent lossless and reciprocal
three-port network. In [18], the realization the two-port
network mentioned above is described in detail. In [20],
one method of realizing an arbitrary three-port network is
presented. This concludes the discussion about the output
combiner and it is now possible to analyze the linearity and
efficiency of the current scaled Doherty PA.
III. L INEARITY AND E FFICIENCY OF A
C URRENT S CALED D OHERTY PA
In this section, the linearity and efficiency of a Doherty PA
with an arbitrary main and auxiliary transistor current ratio for
a given γ will be analyzed. First, the phase response will be
discussed, and after that, the gain response will be discussed.
Finally, the behavior of current scaled Doherty PAs will be
studied for ideal transistors.
The voltage across the load termination Vl of the three-port
combiner can be expressed as
Vl = Ẑ 31 Im + Ẑ 32 Ia + Ẑ 33 Il (15)
where
Vl
Il = − . (16)
(10) Rl
The three-port parameter Ẑ 33 is an arbitrary imaginary value
and can for simplicity be set to zero. The voltage across the
load termination can be expressed in terms of the two-port
  
Vl  Ẑ =0 = ± j Rl {Z 11}Im ± j Rl {Z 22 }Ia (17)
33
where the four solutions come from the four different choices
of θ in (11). This equation is significantly simplified for
a conventional Doherty PA, since Z 22 = 0 after parasitic
compensation. Thus, the phase of the load termination voltage
for a conventional Doherty PA is only dependent on the phase
main transistor current, which agrees well with [5]. For current
scaled Doherty PAs, {Z 22 } = 0 [18]. As a result, the phase
of the load termination voltage is a function of the complex
main and auxiliary transistor currents, and the output combiner
network itself. The black-box combiner synthesis is derived
from the transistor characteristics at two distinct power levels.
Thus, we define, from here on, phase distortion as the phase
(12) difference between these levels
 Vl = Vl,Pmax − Vl,Pbo . (18)
This is a suitable metric of phase distortion, since it is
between these two power levels that the loads of the tran-
sistors are modulated and thus present the most severe phase
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4 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

distortion [4]–[6]. The added complexity of the phase response

of the current scaled Doherty PA opens up the possibility of
both increasing and reducing the Doherty PA phase distortion
in the high power region compared with the conventional
case. Equation (17) suggests that this reduction or increase is
dependent on rc , θ and complex transistor load impedances.
To ensure maximum linearity, the gain of the Doherty PA
at maximum power G Pmax is set equal to the gain of the
predetermined OPBO level G Pbo giving
Pin,max = γ Pin,bo (19)
which can be expanded to
Pin,m,Pmax + Pin,a,Pmax = γ (Pin,m,Pbo + Pin,a,Pbo ). (20)
Enforcing equal gain at these power levels will reduce the
efficiency when the main and auxiliary transistor current ratio
is scaled. The reduction of efficiency is however not so
significant, as is shown below.
With (17) and the condition (20), it is now possible
to study the behavior of current scaled Doherty PAs with
ideal transistors. The behavior is calculated by solving the
output combiner parameters in the previous section, and with
equations describing the ideal transistors from [18]. Since
complex transistor load impedances affect the phase response
of current scaled Doherty PAs, the load terminations of the
main transistor are defined as
Z L ,m,Pmax = R L ,m,Pmax + j X L ,m,Pmax (21)
Z L ,m,Pbo = R L ,m,Pbo + j X L ,m,Pbo . (22)
The load termination of the auxiliary transistor is maintained
purely resistive, since a reactive part does not affect the
gain and phase responses. In order to add a reactive part Fig. 2. (a) Drain efficiency, (b) phase response, and (c) normalized gain
versus output power for the Doherty PA. The plots compare γ = 8 dB
to the main transistor load termination at maximum power, Doherty PAs consisting of two ideal transistors with different current ratios rc
the transistor must be underutilized. This gives and different utilization factors Um . Case A is a fully utilized conventional
Doherty PA. Case B maintains the conventional rc but is underutilized and
R L ,m,Pmax = Um Ropt,class−B (23) reactively terminated. Case C is fully utilized but is current scaled and
reactively terminated.
where 0 ≤ Um ≤ 1 is a utilization parameter and Ropt,class−B
is the conventional class-B optimum load termination. If the TABLE I
maximum voltage swing should be maintained, the reactive D IFFERENT C ASES FOR I DEAL D OHERTY PAs
part must be selected as

X L ,m,Pmax = Ropt,class−B 1 − Um2 . (24)
Consequently, the main transistor load termination at the
backed-off power level is selected as
R L ,m,Pbo = Um Ropt,class−B(1 + rc ) (25) phase distortion of 30°. Case C is fully utilized but is current

scaled—and reactively terminated—such that it also presents
X L ,m,Pbo = Ropt,class−B γ − (1 + rc )2 Um2 . (26)
an inherent phase distortion of 30°. The phase distortion of
In Fig. 2, the efficiency, phase, and gain responses are plotted Cases B and C will be positive or negative depending on the
versus the output power for three different cases. The cases choice of θ . The absolute value of the inherent phase distortion
are γ = 8 dB Doherty PAs consisting of two ideal transistors, is naturally dependent on how much the current ratio is scaled,
with different current ratios rc and different utilizations Um or how much the transistor is underutilized. It is also possible
summarized in Table I. to control the phase distortion by combining current scaling
For γ = 8, rc = 1.51 corresponds to the conventional cur- and underutilization.
rent ratio. Case A is a fully utilized conventional Doherty PA. In Fig. 2, it can be seen that solving the output combiner
Case B maintains the conventional rc but is underutilized— parameters for an inherent phase distortion will cause a very
and reactively terminated—such that it presents an inherent weak nonlinear behavior of the gain response. It can also be
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY 5

seen that these solutions have lower efficiency compared to

the conventional case, i.e., Case A. Underutilizing, as is done
in Case B, lowers the efficiency a bit, whereas the efficiency
reduction from current scaling, as is done in Case C, is not so
significant.
These results indicate that it may be possible to counteract
the phase distortion caused by the load modulation in the
Doherty PA with real transistors by proper choice of rc , Um , θ ,
and complex transistor load terminations, while maintaining
a linear gain response and high efficiency. In the following
section, a design method utilizing current scaling and complex
load terminations is developed to demonstrate that it is possible
to achieve high efficiency and high linearity simultaneously.

IV. D ESIGN M ETHOD

The results in Section III showed that designing a Doherty
PA according to the equations in Section II gives the possibility
to control the AM/PM in the high power region by varying
the amount of current scaling and complex load terminations.
In this section, a design method based on these findings, is
developed for a new tradeoff between high efficiency and high
linearity. The design method is explained on a general level
in this section and is demonstrated on real transistors in the
following section. The method can be utilized for any back-
off level γ , any device periphery ratio, and any input power
split ratio due to the freedom of the output combiner network
derivation described in Section II.
First, the device periphery ratio is selected. A vast number
of ratios are possible since the transistor current ratio can be
controlled by transistor utilization. After the device periphery
ratio is determined, there follows a design method summarized
in Fig. 3. Below follows a detailed explanation of each step.
Step 1: Select the total maximum output power Pmax of
the Doherty PA. If Pmax is selected as the maximum possible,
i.e., full utilization of both transistors, Z L ,m,Pmax and Z L ,a,Pmax
will have only one solution. The exact value of the maximum
possible Pmax is affected by many factors in the design
method, but a rough estimation is sufficient at this step. If Pmax
is selected slightly below the maximum possible value, both
Z L ,m,Pmax and Z L ,a,Pmax will have circles of solutions in the
Smith chart, making it possible to tune the phase distortion.
In addition, a slightly lower Pmax also leads to many different
ways of combining the maximum output powers from the main
and auxiliary transistors [see (13) and (14)]. These different
possible combinations correspond to different current ratios
[see (3)]. In sum, a slightly lower Pmax than the maximum
possible leads to a great amount of different Doherty PA
solutions, making it possible to select a tradeoff between
efficiency and phase linearity.
Step 2: Select the bias level for the main transistor. The
selection of the class-B—or class-AB—bias of the main
transistor is a tradeoff between small signal gain, gain
compression, phase linearity, and efficiency. The bias for best
gain linearity is not necessarily the same as the bias for best
phase linearity. The bias level of the main transistor is very
crucial for the linearity in the low power region, i.e., power
levels below where the auxiliary transistor is turned ON. In the
high power region, when the auxiliary transistor is conducting,
Fig. 3. Doherty PA design method enabling a good tradeoff between PAE
and linearity.
the Doherty PA linearity behavior becomes much more
complex [see (17)].
Step 3: Select the input power split ratio. The split ratio will
to some extent determine the output power ratio between the
main and auxiliary transistors, but due to gain compression of
the transistors, many power ratios are still possible. Since the
black-box combiner can be solved for any input power split
ratio, a good compromise between small signal gain loss and
flexibility of output power ratios has to be found.
Step 4: Find the main transistor back-off load impedance
Z L ,m,Pbo . The possible impedances will be on the output
power circle with a power γ backed-off from Pmax [see (14)].
Selecting this impedance will be a tradeoff between efficiency,
gain, and gain compression. The gain compression at this
backed-off power level will limit the total linearity of the
Doherty in the low power region, i.e., before the auxiliary
transistor turns ON. The load termination at this power level
will also affect the phase distortion in the high power region.
However, it will be shown later that enough degrees of freedom
exist to tune the phase distortion in the high power region
with only the load terminations at maximum power. Selecting
this impedance and choosing between the different tradeoffs
will of course be dependent on system linearity and efficiency
requirements. It is also important to mention that the power
added efficiency (PAE) at the power level Pbo , i.e., PAE Pbo ,
is very critical for the average PAE for modulated signals.
Step 5: Select the class-C bias of the auxiliary transistor.
It is selected such that the auxiliary transistor turns OFF at the
desired backed-off power level Pbo .
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6 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Step 6: Select Pm,Pmax and Pa,Pmax . In order to find the load
impedances at maximum power, a combination of Pm,Pmax and
Pa,Pmax that fulfills (14) has to be selected. Since the maximum
output power of the Doherty PA Pmax has been selected as
slightly lower than the maximum possible Pmax , many com-
binations of Pm,Pmax and Pa,Pmax are possible. The different
possible combinations of Pm,Pmax and Pa,Pmax correspond to
different current ratios [see (3)].
Step 7: Find combinations of Z L ,m,Pmax and Z L ,a,Pmax .
These two impedances will determine the PAE at Pmax ,
i.e, PAE Pmax , which is less critical for the average PAE for
modulated signals. Therefore, the combination of Z L ,m,Pmax
and Z L ,a,Pmax can be selected relative freely. Note that each
power level, e.g., Pm,Pmax , comes with a circle of impedances
in the Smith chart, resulting in many possible combinations
of Z L ,m,Pmax and Z L ,a,Pmax .
All combinations of Z L ,m,Pmax and Z L ,a,Pmax are swept
for all possible combinations of Pm,Pmax and Pa,Pmax , and
the solution with the best tradeoff is selected based on the
following.
1) PAE Pmax —the Doherty PA PAE at maximum output
power. This is dependent on the PAE of the main and
of the auxiliary transistors at their respective maximum
output powers.
2) PAE Pbo —the Doherty PAE at the backed-off power level.
This is dependent on the PAE of the main transistor at
its backed-off power level and the gain loss in the input
power splitter. It is also dependent on the power loss
in the auxiliary transistor output impedance when it is
turned OFF, which in turn is dependent on the choice of
all load impedances.
3)  Vl —the phase distortion in the high power region,
i.e., where the auxiliary transistor is conducting
[see (17) and (18)].
What is considered the best tradeoff is of course dependent
on the system requirements. If a good solution is not found, the
first option is to look at another combination of impedances
at Pmax . If still no good solution is found, the second option
is to change the combination of maximum output powers
from the main and auxiliary transistors, which opens up new
combinations of impedances. The final option is to change the
input power split ratio, which yields new maximum output
power combinations that in turn result in new impedance
combinations. When a satisfactory solution is found, the output
combiner network parameters are derived by the method
described in Section II.
In sum, the proposed design method will maximize the PA
linearity by enforcing equal gain and minimum phase differ-
ence at maximum and the backed-off power levels. At the same
time, the efficiency is high through the choice of impedances
and the analytical combiner design method employed.
V. D OHERTY PA P ROTOTYPE
The method presented above is evaluated with a γ = 8 dB
Doherty PA prototype designed for a center frequency of
2.14 GHz. The PA is implemented using two 15-W bare
die GaN high electron mobility transistors (CGH60015D)
from Cree and printed circuit boards using Rogers 4350B
substrate. The load impedances are found from load–pull sim-
ulations using the nonlinear transistor model provided by the
vendor. Many different combinations of output powers from
the main and auxiliary transistors, and many combinations
of load impedances are studied. Below follows the evalua-
tion of some of the possible combinations of output powers
and impedances. Lastly, a solution with a good compromise
between efficiency and linearity is selected.
Before the load–pull simulations are performed, the main
and auxiliary transistors are stabilized. The second harmonic
terminations at the inputs and outputs of the two transistors
are selected for a good compromise between efficiency and
transistor linearity. The second harmonics are terminated such
that they are not affected by the combiner network or the input
networks.
Below follows a brief description of Steps 1–5 of the design
method (see Fig. 3). Steps 6 and 7 will be discussed in
more detail later in this section. First, the main transistor is
biased at −3.0 V, which provides a good tradeoff between
linear amplitude and linear phase responses of the main
transistor before the auxiliary transistor turns ON. The load
impedance for the main transistor at back-off is selected as
Z L ,m,Pbo = 23.2 + j 27.3. The corresponding output power is
35.3 dBm when the input power is 18 dBm. Thus the maxi-
mum Doherty PA output power will be 43.3 dBm [see (14)],
which is reasonable for these transistors. The Doherty PA
is designed with a symmetrical input power split and con-
jugate matched inputs to maximize the gain. The load–pull
simulations at maximum power are consequently performed
at Pin,m,Pmax = Pin,a,Pmax = 26 dBm. The auxiliary transistor
is biased at −6.0 V, which makes the transistor turn OFF at
Pin,m = Pin,a = 18 dBm.
The next step is to determine a suitable power combination,
i.e., combinations of the maximum output powers from the
main and auxiliary transistors that add up to a total of
43.3 dBm [see (14)]. In the following two sections, two
different power combinations are evaluated.
A. Power Combination 1
The first evaluated combination of maximum output powers
from the main and auxiliary transistors is
Pm,Pmax = 41.9 dBm and Pa,Pmax = 37.7 dBm.
The corresponding impedances are presented in Fig. 4. The
main transistor is fully utilized and has therefore only one
corresponding impedance. The auxiliary transistor is slightly
underutilized and has a big circle of impedances that corre-
spond to the wanted output power. Eight impedances in this
circle are numbered for further evaluation.
The Doherty PA PAE at maximum output power PAE Pmax
and the phase distortion versus the numbered load impedances
of the auxiliary transistor are presented in Fig. 5. Naturally,
the PAE follows the load–pull data according to the combined
contribution from the main and auxiliary transistors. The
phase distortion seems to have a negligible dependence of the
auxiliary impedance.
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY
Fig. 4. Load impedances of (a) main transistor and (b) auxiliary transistor
that yield Power combination 1. Eight impedances in the constant power circle
for the auxiliary transistor have been numbered 1–8.
Fig. 5. Phase distortion and the Doherty PAE at the maximum output power
PAE Pmax versus the numbered load impedances of the auxiliary transistor for
Power combination 1.
The magnitude of the voltage swing at the output of the
auxiliary transistor at the backed-off power level and corre-
sponding dissipated power in Z OFF,a = 1.7 − j 66  versus
the numbered auxiliary impedances are presented in Fig. 6.
It can be seen that some solutions yield a very high voltage
swing at the output of the auxiliary transistor. If this voltage
swing is too high, the assumption of the auxiliary transistor
being turned OFF will no longer be valid. In addition, if this
voltage swing exceeds the maximum possible voltage swing,
the waveform will compress. For the worst case scenario,
i.e., auxiliary impedance Z a5 , the power loss causes a five
percentage points degradation of the back-off efficiency, while
this effect is negligible if Z a1 or Z a8 is chosen.
None of the possible impedance combinations yield a
satisfactory solution regarding PAE, phase distortion, and
power dissipation at back-off. Thus, a new power combination
shall be evaluated.
7
Fig. 6. Magnitude of the fundamental voltage |Va,Pbo | at the output of
auxiliary transistor at the power level Pbo and the corresponding dissipated
power Pdis versus the possible load impedances of the auxiliary transistor for
Power combination 1.
Fig. 7. Load impedances of (a) main transistor and (b) auxiliary transistor
that yield Power combination 2. Eight impedances in the constant power circle
for the main transistor have been numbered 1–8 and eight impedances in the
constant power circle for the auxiliary transistor have been numbered 1–8.
B. Power Combination 2
Since the main transistor was fully utilized in the previous
power combination, the only option for change is to reduce
the maximum output power from the main transistor and
to increase the maximum output power from the auxiliary
transistor. It will be shown below that reducing the maximum
output power from the main transistor by roughly 1 dB is
sufficient for finding completely new solutions.
The second evaluated combination of maximum output
powers from the main and auxiliary transistors is
Pm,Pmax = 41.0 dBm and Pa,Pmax = 39.6 dBm.
This new power combination corresponds to a new current
ratio compared to the previous combination [see (3)]. The
corresponding impedances are plotted in Fig. 7. Since the main
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 8. Phase distortion and the Doherty PAE at the maximum output
power PAE Pmax versus the possible load impedances of the main tran-
sistor Z L ,m,Pmax and possible load impedances of the auxiliary transistor
Z L ,a,Pmax .
Fig. 9. Magnitude of the fundamental voltage |Va,Pbo | at the output
of auxiliary transistor at the power level Pbo and the corresponding
dissipated power Pdis versus the possible load impedances of the main
transistor Z L ,m,Pmax and possible load impedances of the auxiliary
transistor Z L ,a,Pmax .
transistor is no longer fully utilized, a circle of impedances
now yields the wanted output power. Consequently, the auxil-
iary transistor is more utilized, resulting in a smaller circle of
impedances compared to the previous case. Eight impedances
for the main transistor (Z m1 –Z m8 ) and eight impedances for
the auxiliary transistor (Z a1–Z a8) are numbered for further
evaluation.
The Doherty PA PAE at maximum output power PAE Pmax
and the phase distortion are plotted as contours versus the
numbered load impedances of the main and auxiliary tran-
sistors in Fig. 8. Again, it is noted that the phase distortion
seems to have a very weak dependence on the auxiliary
impedance. Thus, all choices of the auxiliary load impedance
while Z L ,m,Pmax = Z m6 give low phase distortion—a low
phase distortion region—but with varying PAE Pmax .
The magnitude of the voltage swing at the output of the
auxiliary transistor at the backed-off power level and cor-
responding dissipated power in Z OFF,a versus the numbered
main and auxiliary impedances are presented in Fig. 9. The
voltage swing varies between 7 and 31 V, corresponding to
0.01–0.19 W of dissipated power in the auxiliary transistor at
back-off. In the low phase distortion region, the voltage swing
Fig. 10. Doherty PA gain, phase response, and PAE for CW simulations
with ideal input and output networks at 2.14 GHz, for Z m6 with Z a3 or Z a6 .
Vertical lines have been plotted at Pmax = 43.3 dBm and Pbo = 35.3 dBm,
i.e., 8-dB OPBO.
varies from 6 to 15 V, which means that the dissipated power
is negligible.
C. Design Evaluation
Based on PAE, phase distortion, and auxiliary transis-
tor power dissipation in back-off, two combinations of
impedances are interesting to evaluate further as follows.
1) Z m6 = 22.9 + j 10.4  with Z a3 = 13.2 + j 13.4 .
2) Z m6 = 22.9 + j 10.4  with Z a6 = 11.4 + j 29.8 .
The two combinations are evaluated with full Doherty PA
simulations in Fig. 10. Vertical lines have been plotted at
Pmax = 43.3 dBm and Pbo = 35.3 dBm (8-dB OPBO).
In these simulations, the input networks and the output com-
biner network are ideal. For both the cases, the full Doherty
PA simulations agree very well with the load–pull data. The
minor differences come from the small signal approximation
of Z a,OFF . In the region where the auxiliary transistor starts
to conduct, Z a,OFF will not be static any more. Thus, the
small signal approximation Z a,OFF will introduce errors in the
output combiner parameters. However, this does not affect
the Doherty PA performance significantly, as can be seen
in Fig. 10. The power level where the auxiliary transistor
turns ON is not only dependent on the gate bias, but also
on the leakage from the main transistor that will pass the
feedback capacitance of the auxiliary transistor to the gate
of the auxiliary transistor. How the leakage will affect the
turn ON power level is dependent on both the phase and
magnitude of that leaked current. Post-tuning the gate bias
of the auxiliary transistor could correct the Doherty behavior
at the backed-off power level, but will at the same time
introduce an error in the Doherty behavior at maximum power.
For Z a6 , the turn ON power level has been shifted such that
the auxiliary turns on at a higher power level than indented,
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY
Fig. 11. Normalized phase responses for CW simulations with ideal input
and output networks at 2.14 GHz for solutions Z m6 and Z a3 . The phases are
plotted for the fundamental drain currents of the main and auxiliary transistors,
for the voltage across the load, and for the voltage across the load when the
phase difference between the main and auxiliary currents is set to the static
value θ .
TABLE II
S ELECTED S OLUTION F ROM THE L OAD –P ULL S IMULATION D ATA
while for Z a3 , the leakage has not affected the turn ON power
level noticeably. Although the turn ON power has not shifted
for Z a3 , the auxiliary transistor is not completely off at the
indented backed-off power level (Pbo = 35.3 dBm) and draws
some dc current. This lowers the Doherty PAE at this power
level compared to the load–pull data. It can also be noted that
the two different solutions present different behavior for power
levels between Pbo and Pmax . The design method does not
predict the Doherty PA behavior between these power levels.
However, it can be seen in Fig. 10 that the Doherty behavior
at Pbo and Pmax is very close to the prediction, i.e., similar
phases and similar gain at these power levels. For both the
solutions, the simulated static AM/AM and AM/PM responses
are applied to an 8.6 dB PAPR long term evolution (LTE)
signal, resulting in an adjacent channel power ratio (ACPR) of
−41.2 dBc for Z m6 and Z a3, and −37.2 dBc for Z m6 and Z a6,
when the maximum output power is 43.3 dBm. The gain
compression at back-off is larger for Z m6 and Z a6 , than for
Z m6 and Z a3 , which results in a more prominent back-off
efficiency peak, but at the cost of linearity.
The impedance combination Z m6 and Z a3 is selected for the
Doherty PA prototype. All impedances with the corresponding
power and PAE are presented in Table II. The phase difference
that yields this performance is θ = −83°. For this selected
solution, different phase responses are plotted in Fig. 11.
Again, the input networks and the output combiner network
are ideal. Phases are plotted for the fundamental drain currents
of the main and auxiliary transistors, for the voltage across
the load, and for the voltage across the load when the phase
difference between the main and auxiliary currents is set to
the static value θ ,  Vl,comb .  Vl,comb demonstrates the phase
distortion resulting only from how the main and auxiliary
9
Fig. 12. Photograph of the fabricated PA. The transistors are soldered to a
ridge.
transistor currents are combined. In other words, the effect
from the phase responses of the transistors has been removed.
It can be seen that an inherently nonlinear phase response
resulting from current scaling and complex load terminations
is achieved, and that this inherently nonlinear response cancels
the nonlinear phase response due to the Miller effect and
transistor nonlinearities. Based on this solution, the output
combiner network parameters are derived from the equa-
tions in Section II and synthesized according to the method
described in [18]. From this, a prototype Doherty PA is
fabricated.
VI. M EASUREMENT R ESULTS
In Fig. 12, a photograph of the fabricated prototype is
presented. A corresponding schematic of the output of the
circuit can be seen in Fig. 13. The second harmonic output
terminations have been absorbed into the combiner network.
Below, measurement results are presented for continuous wave
(CW) signals and modulated signals. Lastly, the measurement
results are compared with state state-of-the-art Doherty PAs.
A. CW Measurements
In Fig. 14, the performance for a 2.14-GHz CW signal is
presented and compared with cut-ready simulations. A vendor-
model is used for the transistors while models from the
Modelithics LCR library are used to simulate the lumped
element components. All the transmission lines are EM sim-
ulated using Keysight Momentum. The transistor is biased
at VGG,m = −2.93 V, VGG,a = −5.70 V and VDD,m =
VDD,a = 28 V. In Fig. 14, vertical lines have been plotted
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10
Fig. 13. Schematic of the output network of the fabricated PA.
Fig. 14. Doherty PA gain, phase response, and PAE for CW measurements
and for cut-ready simulations at 2.14 GHz. Vertical lines have been plotted
at Pmax = 43 dBm and Pbo = 35 dBm, i.e., 8-dB OPBO.
at Pmax = 43 dBm and Pbo = 35 dBm, i.e., 8-dB OPBO.
The line at Pmax marks the indented maximum power level.
After this power level, the main transistor is severely com-
pressed and starts to draw gate current. In the simulations, the
main transistor is pushed further than the measurements. The
gain response agrees well with the simulations, except for an
offset of −3.7 dB. The measured phase response is almost as
good as in the simulations. The measured PAE is a slightly
lower than in the simulations. The input phase delay of the
prototype Doherty PA has been tuned slightly to compensate
for the perceived model inaccuracies. The measured gain
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 15. Measured and simulated S-parameters for the Doherty PA.
TABLE III
ACPR FOR D IFFERENT I NSTANTANEOUS BANDWIDTHS FOR AN 8.6-dB
PAPR LTE S IGNAL , W ITH AND W ITHOUT A 3× S IGNAL BANDWIDTH
M EMORYLESS TABLE -BASED DPD AT Pavg = 35.4 dBm
is: for small signals 10.6 dB, at the back-off power level
G Pbo = 9.2 dB, and at maximum power G Pmax = 8.5 dB.
This means that the gain of the Doherty PA is compressed
1.4 dB in the low power region and that the gain is compressed
0.7 dB in the high power region. The phase of the Doherty PA
is compressed 1.0° in the low power region and the phase is
compressed 5.2° in the high power region. The measured PA
presents PAE Pmax = 51% and PAE Pbo = 39%.
Measured and simulated S-parameters for the PA with a
slightly tuned input phase delay are presented in Fig. 15.
The measured S11 presents a good match around the center
frequency. However, the isolation of the Wilkinson splitter
prevents potential transistor mismatch to be observed at
the PA input. Simulated and measured S12 agree well. The
measured S21 follows the simulations well except for an
offset in magnitude. The measured output matching is not as
good as the simulations.
Recently, we performed load– and source–pull measure-
ments on a similar GaN transistor and observed discrepancies
between simulations and measurements [21]. More specifi-
cally, we observed that the output impedances differ slightly,
but the discrepancies between the simulated and measured
input impedances are more substantial, especially when the
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY 11

TABLE IV
C OMPARISON W ITH S IMILAR GaN D OHERTY PAs

Fig. 16. Normalized power spectral density for a 10-MHz 8.6-dB PAPR Fig. 17. AM/AM and AM/PM for a 10-MHz 8.6-dB PAPR LTE signal
LTE signal at 2.14 GHz with and without digital predistortion. at 2.14 GHz.

transistor is operating in class-C. We therefore believe that

the transistor model inaccuracies are the main cause of the
discrepancies between measurements and simulations in this
paper. It is also interesting to mention that [20] reported similar
discrepancies between measurements and simulations as in
this paper for similar GaN transistors. Despite the discrepan-
cies, the fabricated PA prototype in this paper presents good
efficiency and linearity, which is expected from the novel
methodology.
Fig. 18. Average PAE and ACPR versus average output power.
B. Modulated Measurements
The prototype PA is also evaluated with a 10-MHz
8.6-dB PAPR LTE signal at 2.14 GHz. To match the behavior AM/AM and AM/PM for the signal without linearization is
in the CW measurements, the bias levels were tuned to presented in Fig. 17. It can be observed that the PA presents
VGG,m = −2.83 V, VGG,a = −5.10 V. Similar shifts in linear responses for the modulated signal with the same trends
bias levels are seen in [22] and [23]. Normalized power as in the CW measurements. For the modulated signal without
spectral densities, with and without digital predistortion (DPD) linearization, the average PAE and the ACPR are plotted versus
linearization, are presented in Fig. 16. The PA presents an average output power in Fig. 18. It can be seen that the
average PAE of 40% and a raw ACPR of −40.8 dBc at ACPR sweet spot is very close to the indented operational
an average output power Pavg = 35.5 dBm. After apply- power level. This could be attributed to the intended flat gain
ing a memoryless table-based DPD running at three times and phase responses in the Doherty region resulting from the
the signal bandwidth, i.e., 30 MHz, the PA presents an design method. Modulated measurements were also performed
ACPR = −47.8 dBc at Pavg = 35.4 dBm. The corresponding for different instantaneous bandwidths for the 8.6-dB PAPR
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12 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES

LTE signal. The ACPR with and without the mentioned DPD A PPENDIX A
is summarized in Table III. For the presented three cases, the S OLUTIONS TO THE T WO -P ORT C OMBINER PARAMETERS
average output power is roughly 35.4 dBm and the average In Section II, the output combiner parameters are derived
PAE is 40%. It can be seen that the memoryless DPD becomes for a lossy and reciprocal two-port network in terms of the
less effective as the signal bandwidth increases. transistor load terminations. These two-port network parame-
ters have the following solutions:
C. Comparison With State of the Art 
Z 11 = α12 Z L ,m,Pbo (Z L ,a,Pmax + Z OFF,a ) + Z L ,m,Pmax
The performance of the prototype Doherty PA is sum- 
(Z L ,m,Pmax − Z L ,m,Pbo )) C0 (27)
marized and compared with other similar GaN Doherty
PAs in Table IV. The Doherty PA in [24] is a three-way Z 12 = Z 21 = (α1 (Z L ,a,Pmax + Z OFF,a )

Doherty PA, whereas the rest are two-way. It should also (Z L ,m,Pmax − Z L ,m,Pbo )) C0 (28)
be mentioned that [24] requires three individually controlled 
Z 22 = α12 Z L ,a,Pmax (Z L ,a,Pmax + Z OFF,a ) − Z OFF,a
inputs. The Doherty PA in [9] is a dual-band MMIC PA whose 
best performing band is included in the table. [23] presents (Z L ,m,Pmax − Z L ,m,Pbo ) C0 (29)
an ultrabroadband MMIC Doherty PA (5.8–8.8 GHz) with an where
ACPR without DPD at 7 GHz that is very similar to what is
reported in this paper. The amplitude and phase responses vary C0 = α12 (Z L ,a,Pmax + Z OFF,a ) + (Z L ,m,Pmax − Z L ,m,Pbo ).
across the band, and it is not shown why a linear amplitude (30)
response coincides with low phase distortion at 7 GHz, which
is not the center frequency. The Doherty PAs in [17] and [18] A PPENDIX B
utilize a similar technology and a very similar design method T WO - TO T HREE -P ORT C ONVERSION
as in this paper. The design method in [17] and [18]
In Section II, the output combiner parameters are derived for
solves a black-box combiner network solely for high effi-
a lossy and reciprocal two-port network. It must be possible to
ciency. Thus, comparing this work with [17] and [18] gives
convert this two-port combiner into a lossless and reciprocal
a good understanding of the tradeoffs between efficiency
three-port combiner with the third port terminated with a resis-
and linearity. The Doherty PA in [25] utilizes complex load
tive load. Below follows the derivation of the three-port net-
combining for a tradeoff between efficiency and linearity.
work parameters in terms of the two-port network parameters.
The distinct efficiency and linearity of the prototype PA
The two- and three-port network parameters are denoted by
in this paper demonstrate the benefits of the presented novel
Ẑ i j and by Z i j , respectively. Terminating the third port of the
design method.
three-port network with a resistive load Rl will result in a
two-port network. The Z -parameters of this two-port network
VII. C ONCLUSION expressed in terms of the three-port network parameters can be
Treating the output combiner network of the Doherty PA as found in [18]. The lossless and reciprocal three-port network
a black box and solving its parameters, together with the input parameters can be written in terms of the two-port network
phase delay, based on given boundary conditions, opens up parameters and the load resistance Rl according to
the possibility to find new solutions. These new solutions have 
deviating current profiles compared with the conventional Ẑ 31 = ± j {Z 11 }/C1 (31)

Doherty PA current profiles, in other words current scaled Ẑ 32 = ± j {Z 22 }/C1 (32)
Doherty PA solutions. Current scaling together with complex 2
Ẑ 31
load terminations results in an inherent nonlinear phase Ẑ 11 = Z 11 + (33)
response, which can be utilized to counteract inherent Ẑ 33 + Rl
Doherty PA phase distortion due to the Miller effect and Ẑ 31 Ẑ 32
Ẑ 12 = Z 12 + (34)
transistor nonlinearities. The increased design space of the Ẑ 33 + Rl
current scaled Doherty PA has enabled a novel design method 2
Ẑ 32
providing a new tradeoff between efficiency and linearity. All Ẑ 22 = Z 22 + (35)
the steps in the design method have first been described for Ẑ 33 + Rl
the generic case, and then applied for a specific GaN Doherty where
PA design. Since the design method treats the output combiner Rl
network as a black box, all possible solutions in the design C1 = (36)
Rl2 + | Ẑ 33|2
space can be fully evaluated remarkably fast. The proposed
design method has been experimentally verified by a prototype and where the roots must be selected such that
PA presenting excellent efficiency and highly linear AM/AM −sgn( Ẑ 31 Ẑ 32 ) = sgn({Z 12}). (37)
and AM/PM responses. The novel design method manifests
the Doherty PA’s position in applications demanding The three-port parameters include six unknowns and
high efficiency and high linearity—completely without are given by only five equations. The equation system is
predistortion or with low-complexity predistorters, which is a underdetermined and has infinitely many solutions. Thus the
stringent requirement of future wireless infrastructures. parameter Ẑ 33 can adopt any arbitrary purely imaginary value.
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HALLBERG et al.: DOHERTY PA DESIGN METHOD FOR IMPROVED EFFICIENCY AND LINEARITY
The purely imaginary value of Ẑ 33 will determine a static
phase difference for the voltage Vl across Rl . For example,
the phase difference of Vl when Ẑ 33 → j 0 and when
Ẑ 33 → j ∞ is 90°.
Now, all the three-port parameters are known in terms
of the calculated two-port network parameters, the arbitrary
resistive Rl , and the arbitrary imaginary Ẑ 33 . Although the
three-port network parameters are derived for a resistive load
termination here for the sake of simplicity, derivations can also
be extended to a complex load termination.
ACKNOWLEDGMENT
The authors would like to thank Modelithics, Inc., Tampa,
FL, USA, for the use of Modelithics models utilized under the
University License Program. The authors would also like to
thank Dr. K. Andersson, Ericsson AB, for fruitful discussions.
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William Hallberg (S’13) received the B.Sc. degree
in engineering physics and the M.Sc. degree in elec-
trical engineering from the Chalmers University of
Technology, Gothenburg, Sweden, in 2012 and 2014,
respectively, where he is currently pursuing the
Ph.D. degree
In 2014, he joined the Microwave Electronics
Laboratory, Chalmers University of Technology.
His current research interests include highly efficient
and linear power amplifiers.
Mustafa Özen (S’10–M’14) received the B.Sc.
degree in electrical engineering from Ankara Univer-
sity, Ankara, Turkey, in 2006, and the M.Sc. degree
in microwave engineering and the Ph.D. degree from
the Chalmers University of Technology, Gothenburg,
Sweden, in 2010 and 2014, respectively.
He is currently a Joint Post-Doctoral Researcher
with the Chalmers University of Technology and the
University of California at San Diego, San Diego,
CA, USA. His current research interests include high
efficiency power amplifier architectures, lineariza-
tion, and the design of millimeter-wave SiGe/Si front-ends.
Dr. Özen was a recipient of the 2011 Best Paper Award of the IEEE Wireless
and Microwave Technology Conference and the International Post-Doctoral
Fellowship from the Swedish Research Council in 2016.
David Gustafsson received the M.Sc. degree in
engineering physics and the Ph.D. degree from the
Chalmers University of Technology, Gothenburg,
Sweden, in 2009 and 2014, respectively.
In 2014, he joined Ericsson Research, Gothenburg,
where he is currently involved in gallium nitride
monolithic microwave integrated circuits and
millimeter-wave 5G front-ends.
Dr. Gustafsson was a recipient of the 2013
IEEE Microwave Theory and Techniques Society
Graduate Fellowship.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
14
Koen Buisman (S’05–M’09) received the M.Sc. and
Ph.D. degrees in microelectronics from the Delft
University of Technology, Delft, The Netherlands,
in 2004 and 2011, respectively.
From 2004 to 2014, he was with the Delft Insti-
tute of Microsystems and Nanoelectronics, Delft
University of Technology. In 2014, he joined the
Chalmers University of Technology, Gothenburg,
Sweden, where he is currently an Assistant Professor
with the Microwave Electronics Laboratory, Depart-
ment of Microtechnology and Nanoscience. He has
authored or co-authored over 45 refereed journal and conference papers.
He holds two patents. His current research interests include varactors for
RF adaptivity, nonlinear device characterization, and technology optimization
for wireless systems.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Christian Fager (S’98–M’03–SM’15) received the
M.Sc. and Ph.D. degrees in electrical engineer-
ing and microwave electronics from the Chalmers
University of Technology, Gothenburg, Sweden, in
1998 and 2003, respectively.
He is currently a Professor with the Microwave
Electronics Laboratory, Chalmers University of
Technology. He has authored or co-authored over
100 papers in international journals and conferences.
His current research interests include the design and
modeling of linear and energy efficient transmitters
for future wireless systems.
Dr. Fager was a recipient of the Best Student Paper Award at the
IEEE MTT-S International Microwave Symposium in 2002. He is currently
an Associate Editor for IEEE Microwave Magazine.