CHAPTER 4

DESIGN METHDOLOGY FOR DIFFERENTIAL

PAIR AND OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER

4.1 INTRODUCTION

The chapter 3 described the conversion of BSIM to EKV model parameters with an objective
of using EKV model for pre-SPICE design guidance. The design of analog circuits such as
high-performance amplifiers is a complex exercise which presents many challenges requiring
intuition and experience to arrive at an acceptable solution. The complication in analog CMOS
design is more in MOSFET than bipolar technology because of there additional degrees of
design freedom - drain current, inversion coefficient and channel length. Selecting the inver-
sion coefficient permits the choice of operation in weak, moderate or strong inversion, which
controls many aspects of MOS performance. In chapter 2 the design parameters such as: satu-
ration voltage, small signal parameters, parasitic capacitances, and transconductance efficiency
are shown to be function of inversion coefficient. In this chapter we give design procedure
of differential amplifier and Operational Transconductance Amplifier(OTA) using these design
parameters. The extracted EKV model parameters on 0.18µm CMOS process obtained in chap-
ter 3 will be plugged in EKV model equations to show design methodology for standard analog
circuits. The results obtained by using EKV model for hand calculation will be compared with
BSIM simulated data.

44
4.2 DESIGN METHODOLOGY OF COMMON SOURCE
AMPLIFIER

A common source, CS amplifier shown in Figure 4.1 is the single-stage amplifier which per-
forms voltage to current conversion. The important design specifications for CS amplifier are
transconductance, output resistance, input common mode range and output swing. In this sec-
tion, we show design methodology of resistive loaded CS amplifier using Inversion Coeffi-
cent(IC) as a design parameter. The specifications for which CS amplifier is to be designed are:
fT = 100MHz, CL = 5pF , ID ≤ 1mA, output voltage swing= 2V [32].

VDD = 3V

R1 = 1kΩ

Vout

Vin C1 = 5pF

Figure 4.1: Schematic diagram of common source amplifier

4.2.1 DESIGN STEPS FOR COMMON SOURCE AMPLIFIER FOR DE-

SIRED SPECIFICATIONS

1. As per the given specifications the drain current IDS is fixed at 1 mA

2. The gm is obtained using the following expression.

g m = 2 · π · fT · C L (4.1)

3. Substituting fT and CL in the above expression the gm /IDS obtained is 3.141.

4. From Figure 4.2 the IDS /(W/L) corresponding to gm /IDS =3.141 is 2.76 × 10−5 using
BSIM simulated data and 2.66 × 10−5 using EKV model.

45
 2
10
BSIM3v3
EKV

1
10

gm/ID

0
10

−1
10 −10 −9 −8 −7 −6 −5 −4 −3
10 10 10 10 10 10 10 10
Current Density(ID/(W/L))

Figure 4.2: Transconductance to drain current gm /IDS ratio vs IDS /(W/L) using BSIM and
EKV model

5. We have chosen IDS = 1mA, so (W/L) ratio will be 33 using BSIM simulation and
37.72 using EKV model. Using this (W/L) ratio if L=0.5µm then W=16.5µm for BSIM
generated data and using EKV model if L=0.5µm then W=18.86µm.

6. The value of drain resistance RD for voltage swing of 2V peak is obtained by applying
KVL at output of the common source amplifier circuit, we get:

VDD − 2 3−2
RD = = = 1KΩ (4.2)
IDS 1 × 10−3

4.2.2 FREQUENCY RESPONSE OF COMMON SOURCE AMPLIFIER

20
BSIM3v3
10 EKV

0
Voltage Gain(dB)

−10 f =88.4 MHz

TBSIM

−20
f =103 MHz
TEKV
−30

−40

−50

−60 0 2 4 6 8 10 12
10 10 10 10 10 10 10
Frequency(Hz)

Figure 4.3: Frequency response of common source amplifier using BSIM and EKV model

The Figure 4.3, shows the frequency response of CS amplifier using BSIM and EKV model.
The midband voltage gain(AV ) obtained is approximately 10 dB using both the models and
unity gain frequency(fT ) is 88.4 MHz using BSIM and 103 MHz using EKV model.

46
4.3 DESIGN METHODOLOGY OF DIFFERENTIAL AM-
PLIFIER PAIR

4.3.1 INTRODUCTION

The Figure 4.4 show the schematic diagram of a differential amplifier [32]. It converts a
differential input voltage vIN,DM = vIN + − vIN − to a differential output current iOU T =
iOU T − − iOU T + , and ideally should not be sensitive to any variation of the common input
voltage vIN,CM = (vIN + − vIN − )/2. The design parameters of differential pair are equivalent
transconductance(gm,eq ), differential input range, input common-mode range, input capacitance,
equivalent noise, and equivalent offset.

4.3.2 SIZING OF MOS TRANSISTORS IN DIFFERENTIAL AMPLI-

FIER

The schematic diagram of differential amplifier shown in Figure 4.4 have

VDD = 3V

M4 M3

6 Vout
C1 = 5pF

Vin − 4 Vin +
M1 M2
3

I1 = 10µA
0

Figure 4.4: Schematic diagram of single-ended differential amplifier

M1 and M2 transistors as input differential pair transistors which will decide the equivalent
transconductance of the circuit. The equivalent transconductance is defined as the first-order
derivative of the output current which is the slope of transfer characteristics. The slope at the

47
origin for a small differential input voltage is equal to the transconductance of the transistors
M1,2 at the DC operating point so gm,eq = gm1 = gm2 . The M3 and M4 are the current mirror
transistors used to steer same current in the both branches of the differential pair. Biasing of the
circuit is done by an ideal current source connected at the bottom of the differential pair. The
differential pair is driving 5pF load capacitor. The desired specification of differential pair are
given in Table 4.1. The supply voltage VDD is 3V.

Table 4.1: Specifications of single ended differential amplifier

Sr. No. Parameter Value Units

1. Voltage Gain(AV ) ≥10 V/V
2. Unity Gain Frequency(fT ) 10 MHz
3. Slew Rate(SR) ≥10 V/µs
4. Output Voltage Swing 2 V
5. Load Capacitor(CL ) 5 pF
6. Power Dissipation(Pdiss ) ≤1 mW

Steps of designing differential amplifier for desired specifications

1. From Slew Rate(SR) and power dissipation expression we choose bias current for the
circuit.
Ibias
SR = (4.3)
CL
Given specifications are SR ≥ 10V/µ s and CL = 10pF, Ibias ≥ 50µA and power dissipa-
tion Pdiss ≤ 1mW. Thus
Pdiss = VDD .Ibias (4.4)

Ibias ≤ 286µA (4.5)

Therefore,
50µA ≤ Ibias ≤ 286µA (4.6)

We choose Ibias =100µA.

2. From fT and CL specifications, we obtain gm of the circuit.

g m = 2 · π · fT · C L (4.7)

Therefore, gm = 312 µs, and gm /IDS = 6.24.

3. From the characteristics of curve of gm /IDS vs IDS /(W/L) shown in Figure 4.2 , we

48
 choose the IDS /(W/L) at the corresponding gm /IDS value, i.e., at gm /IDS = 6.24 the
ID /(W/L) is 1.198 × 10−5 using BSIM simulated data and 9.958 × 10−6 using EKV
model.

4. At Ibias of 100µA, current flowing through the input transistors M1 and M2 will be 50µA.
At this current the (W/L) ratio will be 4.173 using BSIM and 5.02 using EKV model.
Using these (W/L) ratios if we choose L=2µm then W=8.346µm using BSIM model and
W=10.04µm using EKV model.

5. The transistors M3 and M4 are used as active load and are biased in strong inversion
saturation region. We choose gm /IDS in strong inversion, i.e, gm /IDS =5.8. The corre-
sponding IDS /(W/L) will be 4.758 × 10−6 for BSIM and 3.898 × 10−6 for EKV. There-
fore, (W/L)BSIM =10.52 and (W/L)EKV =12.82. The Table 4.2 show target specifica-
tions achieved using simpler EKV model and for comparison BSIM simulated results are
shown in Table 4.3.

Table 4.2: Design parameters of differential amplifier using EKV model

Sr. No. Parameter Value

1. ((W/L)M 1,M 2 ) 5.02
2. ((W/L)M 3,M 4 ) 12.82
3. Ibias 100µA
4. Voltage Gain(AV ) 98.9 V/V
5. Unity Gain Frequency(fT ) 12.4 MHz
5. Slew Rate(SR) 15.4V/µs
6. Power Dissipation(Pdiss ) 300 µW

Table 4.3: Simulated design parameters of differential amplifier using BSIM

Sr. No. Parameter Value

1. ((W/L)M 1,M 2 ) 4.173
2. ((W/L)M 3,M 4 ) 10.52
3. Ibias 100µA
4. Voltage Gain(AV ) 95.5 V/V
5. Unity Gain Frequency(fT ) 11.4 MHz
5. Slew Rate(SR) 18V/µs
6. Power Dissipation(Pdiss ) 69 µW

49
4.3.3 FREQUENCY RESPONSE OF DIFFERENTIAL AMPLIFIER

The Figure 4.5 shows the frequency response of a differential amplifier using BSIM and EKV
model.

BSIM3v3
40
EKV

20 AVBSIM= 95.5 V/V AVEKV= 98.9 V/V

Voltage Magnitude(dB)

fTEKV=12.4 MHz
0

−20 fTBSIM=11.4 MHz

−40

−60

−80 0 2 4 6 8 10 12
10 10 10 10 10 10 10
Frequency(Hz)

Figure 4.5: Frequency response of differential amplifier designed for desired specifications

The unity gain frequency, fT of differential amplifier is 11.4 MHz using BSIM model and
12.4MHz using EKV model for desired specification of 10MHz. The differential voltage
gain(AV ) is 95.5 V/V for BSIM and 98.9 V/V for EKV for the desired specification of 100
V/V.

4.4 DESIGN METHODOLOGY OF OPERATIONAL TRANSCON-

DUCTANCE AMPLIFIER

In this section we have shown design methodology of CMOS operational transconductance

amplifier(OTA) optimised for DC, balanced and AC performance. The DC optimised OTA
has high transconductance, output resistance, voltage gain and input and output voltage ranges,
combined with low input-referred flicker-noise and offset voltage. The AC optimised OTA uses
minimum channel length devices operating in strong inversion resulting in smaller gate areas.
This OTA has high transconductance bandwidth, low transconductance distortion, small input
and output capacitance but at the expense of DC optimised performance. We first describe the
circuit performance parameters for simple OTA, followed by Miller compensated OTA as a
design example for desired specifications.

50
4.4.1 CIRCUIT ANALYSIS OF OTA

The schematic diagram for the OTA is shown in Figure 4.6. This circuit have differential pair
NMOS transistor M1-M2 at the input stage and constant current source biasing provided by
NMOS transistors M5, M8 and M9. The output drain current are mirrored by PMOS transistors
M3 and M4, used as active load. The output of differential stage is fed to the second stage which
is connected in common source configuration. The drain of PMOS transistor M6 is connected to
the drain of NMOS transistor M7 which is the output of OTA. The first stage of OTA gives high
gain and second stage is used for high voltage swing. The capacitor(Cc ) connected between two
stages is miller capacitance used for phase compensation.

VDD

M9 M3 M4 M6
CC

CL

Vin− M1 M2 Vin+

M8 M5 M7

VSS

Figure 4.6: Schematic diagram of Miller operational transconductance amplifier

The specifications of OTA are open-loop gain(AoL ), small signal bandwidth(fT ), output signal
swing, Common-Mode Rejection Ratio(CMRR), Slew Rate(SR) and Power Supply Rejection
Ratio(PSRR).

4.4.2 MILLER COMPENSATION OF OTA

Compensation technique is used to improve the phase margin of the OTA. If the phase margin
of the amplifier goes below 45◦ than some compensation techniques should be used to increase

51
the phase margin so that amplifier remains stable. This compensation can be done by splitting
poles far away from each other so as to make one pole dominant [45]. The splitting can be done
by adding a Miller capacitance between first and second stage shown in Figure 4.6 of the OTA
circuit.

There are two effects of compensation capacitor Cc in OTA. First, the effective capacitance
shunting total output resistance of first stage(RI ) is increased by addition of approximately
gmII (RII (Cc )) where gmII is gm of second stage and RII is total output resistance of second
stage of OTA. This moves p1 (location of pole p1 ) closer to the origin of complex frequency plane
by a significant amount. Second, p2 (location of pole p2 ) is moved away from the origin of the
complex frequency plane, resulting from the negative feedback reducing the output resistance
of the second stage. The task in compensating an amplifier for closed loop applications is to
move all poles and zeroes, except for the dominant pole(p1 ), sufficiently away from the origin
of the complex frequency plane(beyond the unity-gain frequency). This improve stability of the
amplifier.

4.5 CIRCUIT LEVEL PERFORMANCE OPTIMISATION

OF OTA

The following are the circuit-level design parameters for OTA:

Voltage Gain(Av ) and Output Resistance(Rout )

The expression of voltage gain is given by:

Av = Av1 .Av2 (4.8)

Av1 and Av2 are the voltage gains of first and second stage of OTA. It can be written as:

gm VA2 .VA4
AV 1 = −( )1 (4.9)
IDS VA2 + VA4

gm VA6 .VA7
AV 2 = −( )6 (4.10)
IDS VA6 + VA7
The output resistance(Rout ) is given by

1
Rout = (4.11)
gds6 + gds7

52
Input Common Mode Range(ICMR) is given by:

VICM R,max = VDD − |VGS3 | − |VDsat1 | − |VGS1 | (4.12)

VICM R,min = VDsat5 + VGS1 (4.13)

Slew Rate(SR) is given by:  

IDS5 IDS7
SR = min , (4.14)
Cc CL
Unity Gain Frequency(fT ) and Phase Margin(PM) [45] by

gm1
fT = (4.15)
2πCc
ω ω ω
P M = 180◦ − tan−1 ( ) − tan−1 ( ) − tan−1 ( ) (4.16)
fp1 fp2 fz1

4.6 DESIGN EXAMPLE OF MILLER OTA

The design specifications spreadsheet of the Miller OTA shown in Figure 4.6 are given in Ta-
ble 4.4.

Table 4.4: Design specifications spreadsheet of Miller OTA

Sr. No. Parameter Value Units

1. Voltage Gain(AV ) ≥80 dB
2. Unity Gain Frequency(fT ) 15 MHz
3. Phase Margin (PM) 60 degrees
4. CMRR ≥80 dB
5. Slew Rate(SR) ≥18 V/µs
6. ICMR -0.5 to 1 V
7. Load Capacitor(CL ) 10 pF
8. Supply Voltages(VDD ,VSS ) ±2 V

1. In first step, we choose the compensation capacitor(Cc ) for phase margin 60◦ given by:

Cc ≥ 0.22CL (4.17)

Thus, Cc ≥ 0.22 × 10pF≈ 2.5 pF.

53
2. Next, we fix the bias current for slew rate SR = 18V/µ s. Using (4.14) we get:

Ibias = 45 µA (4.18)

3. After fixing the bias current, the sizing of W/L is done for current mirror NMOS transis-
tors M3 and M4 working as a active load for differential pair. The M3-M4 transistors are
operated in strong inversion for good matching and noise properties. Thus, we choose
(gm /IDS )3 =(gm /IDS )4 =10 to get (W/L)3,4 using BSIM and EKV model given in Ta-
ble 4.5.
Table 4.5: Size of NMOS transistors M3-M4 for design of Miller OTA

Model (gm /IDS )3,4 IDS /(W/L) (IDS )3,4 (µA) (W/L)3,4
BSIM 10 1.69× 10−6 22.5 13.31
−6
EKV model 10 1.35× 10 22.5 16.67

4. Next, step is to size(W/L) of M1-M2 transistors. We calculate gm1,2 of the transistor by

gain-bandwidth specifications(fT = 15MHz). Therefore, by using (4.15), gm1,2 will be

gm1,2 = 235.5µS (4.19)

From gm /IDS versus IDS /(W/L) relation we obtained (W/L)1,2 given in Table 4.6.

Table 4.6: Size of NMOS transistors M1-M2 for design of Miller OTA

Model (gm /IDS )1,2 IDS /(W/L) (IDS )1,2 (µA) (W/L)1,2
BSIM 10.47 5.07× 10−6 22.5 4.43
EKV 10.47 3.922× 10−6 22.5 5.73

5. After sizing NMOS transistors M1-M2, we calculate gm of M6 transistor. For a phase

margin 60◦ , the location of the output pole is assumed to be placed at 2.2 × gain-
bandwidth product(GBW). Based on this assumption and the relationship for |p2 | =
−gm6 /CL the transconductance gm6 can be determined by:

gm6 = 2.2(gm2 )(CL /Cc ) ≈ 2.35mS (4.20)

The M6 transistor give high voltage swing, thus we choose (gm /IDS )6 = 10 in strong
inversion. Therefore, current through M6 transistor is 235µA. The size of M6 transistor
is given in Table 4.7.

54
 Table 4.7: Size of PMOS transistor M6 for design of Miller OTA

Model (gm /IDS )6 IDS /(W/L) (IDS )6 (µA) (W/L)6

BSIM 10 1.69× 10−6 235 138.8
−6
EKV 10 1.35× 10 235 174

6. Final step is to size current biasing transistors M5, M7 and M8. For good DC bias op-
timisation, we consider these transistors to be operated in moderate inversion. Thus, we
choose, (gm /IDS )5 =(gm /IDS )7 =(gm /IDS )8 =7. Size of these transistors are shown in Ta-
ble 4.8.

Table 4.8: Size of NMOS transistor M5, M7 and M8 for design of Miller OTA

Model (gm /IDS ) IDS /(W/L) (IDS )5,8 (µA) (ID )7 (µA) (W/L)5,8 (W/L)7
BSIM 7 1.023× 10−5 45 235 4.39 22.9
EKV 7 8.159× 10−6 45 235 5.51 28.8

Considering the gm /IDS obtained in the previous design specifications, the minimum
allowable transistor lengths can be obtained based on the VA parameter that is directly
related with the transistor output resistance, and consequently with the DC gain. After
performing second round of optimisation the sizing of the Miller OTA with minimum
allowable transistor sizes are given in Table 4.9 and 4.10.

Table 4.9: Size of MOS transistors in design of OTA using BSIM simulated data

Transistors (gm /IDS ) (W/L) L(µm) W(µm)

M1 10.47 1.5 3 4.5
M2 10.47 1.5 3 4.5
M3 10 13.31 3 40
M4 10 13.31 3 40
M5 7 4.39 1 4.39
M6 10 138.8 0.6 84
M7 7 22.9 1 22.9
M8 7 4.39 3 13.17
M9 2 2.12 4 8.48

55
 VDD = 2V

2 Vout

+
+
1VAC −

0
0
VSS = −2V

Figure 4.7: Simulation setup for open-Loop analysis [45] of Miller OTA

Table 4.10: Size of MOS transistors in design of OTA using analytical EKV model

Transistors (gm /ID ) (W/L) L(µm) W(µm)

M1 10.47 2 3 6
M2 10.47 2 3 6
M3 10 16.7 3 50
M4 10 16.7 3 50
M5 7 5.51 1 5.51
M6 10 174 0.6 104.4
M7 7 28.8 1 28.8
M8 7 5.51 3 17
M9 2 2.17 4 8.68

4.6.1 OPEN-LOOP ANALYSIS OF MILLER OTA

The circuit of open-loop frequency analysis of Miller OTA is shown in Figure 4.7. Using this
circuit we can obtain gain magnitude, phase response and output voltage swing of an open-loop
OTA. The gain magnitude and phase plot of Miller OTA is shown in Figure 4.8 and Figure 4.9
respectively.

56
 BSIM3v3
80
EKV

60
AVBSIM= 77.9 dB AVEKV= 79.05 dB

Voltage Gain in dB
40
fTEKV= 17.71MHz
20

−20 fTBSIM= 15.11MHz

−40 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10
Frequency(Hz)

Figure 4.8: Gain Magnitude Response of Miller OTA

0 BSIM3v3
EKV

−50
Voltage Gain in dB

−100

PMBSIM= 59°
−150
PMEKV= 55.5°

−200 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10
Frequency(Hz)

Figure 4.9: Phase Response of Miller OTA

For target specifications of 15MHz the unity gain frequency of OTA by BSIM simulated data
is 15.11MHz and by using EKV model is 17.71 MHz. Similarly for phase margin specification
of 60◦ the phase margin is 59◦ for BSIM simulated data and 55.5◦ using EKV model. As per
the required specification of the output voltage swing for OTA using BSIM and EKV model is
shown in Figure 4.10.

4.6.2 COMMON MODE REJECTION RATIO ANALYSIS OF MILLER

OTA

For larger input Common-mode voltage rejection the higher Common Mode Rejection Ratio,
CMRR is expected from OTA. The circuit diagram for calculation of CMRR is shown in Fig-
ure 4.11. The circuit consists of two identical constant DC voltage sources Vcm placed in series
with both the OTA inputs and OTA is connected in the unity gain configuration. It is shown

57
 2

1.5
BSIM3v3
1
EKV
Output Voltage(V)

0.5

−0.5

−1

−1.5

−2
−5 −4 −3 −2 −1 0 1 2 3 4 5
Input Voltage(V) −3
x 10

Figure 4.10: Output Voltage Swing of Miller OTA

VDD = 2V

V cm
−
3
2
Vout

V cm

0 VSS = −2V

Figure 4.11: Circuit diagram for calculation of CMRR [45]

58
 85
BSIM3v3
80 EKV

75

70 CMRREKV=80.45 dB
CMRRBSIM=77.91 dB

CMRR(dB)
65

60

55

50

45

40 1 2 3 4 5 6 7 8
10 10 10 10 10 10 10 10
Frequency(Hz)

Figure 4.12: CMRR of Miller OTA

VDD = 2V

2 −

2
Vout
1 +

+
P ulseV oltage
−
0
VSS = −2V

Figure 4.13: Circuit diagram of unity gain feedback in Miller OTA [45]

that [45]
Vout ±Ac ∼ |Ac | 1
= = = (4.21)
Vcm 1 + Av − (±Ac /2) Av CM RR
Therefore, by using the above circuit and (4.21), we can calculate the CMRR of the OTA. The
Figure 4.12 shows the magnitude response of OTA for CMRR calculation. The CMRR of Miller
OTA is 77.91 dB for BSIM and 80.45 dB for EKV.

4.6.3 UNITY GAIN FEEDBACK ANALYSIS OF MILLER OTA

The circuit diagram for unity gain closed loop Miller OTA is shown in Figure 4.13. This circuit
is used to compute slew rate and Input Common Mode Range(ICMR). The slew rate and ICMR

59
 2
BSIM3v3
EKV
1.5 SR+BSIM=65V/µs
SR−BSIM=70V/µs

Output Voltage(V)
1

0.5 SR+EKV=61V/µ s SR−EKV=61.6V/µs

−0.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(s) −6
x 10

Figure 4.14: Slew Rate of Miller OTA

1.5 BSIM3v3

1
Output Voltage(V)

0.5

−0.5

−1
ICMRBSIM,EKV= −0.5 to 1.5 V
−1.5

−2
−2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5
Input Voltage(V)

Figure 4.15: ICMR of Miller OTA

for BSIM and EKV models are shown in Figure 4.14 and Figure 4.15 respectively. The posi-
tive and negative slew rate are 65V/µs and 70V/µs respectively for BSIM. Similarly, for EKV
positive and negative slew rate is 61V/µs and 61.6V/µs respectively. The slew rate obtained
is greater than target specifications of greater than or equal to 18V/µs. The Figure 4.15, shows
ICMR for both BSIM and EKV model are in range of -.5V to 1.5 V against the target specifi-
cation are -0.5V to 1V. The spreadsheet of the performance obtained in the design of OTA for
BSIM and EKV model is given in Table 4.11 and 4.12.

60
 Table 4.11: Simulated results of Miller OTA using BSIM

Sr. No. Parameter Value Units

1. Voltage Gain(AV ) ≥77.9 dB
2. Unity Gain Frequency(fT ) 15.11 MHz
3. Phase Margin (PM) 59 degrees
4. CMRR 77.91 dB
5. Slew Rate(SR±) +65,-70 V/µs
6. ICMR -0.5 to 1.5 V

Table 4.12: Results of Miller OTA using analytical EKV model

Sr. No. Parameter Value Units

1. Voltage Gain(Av ) ≥ 79.05 dB
2. Unity Gain Frequency(fT ) 17.71 MHz
3. Phase Margin (PM) 55.5 degrees
4. CMRR 80.45 dB
5. Slew Rate(SR±) +61,-61.6 V/µs
6. ICMR -0.5 to 1.5 V

4.7 CONCLUSION

The design methodology presented in this chapter are illustrations of the design procedures
that can be applied to analog building blocks. It is based on the structured design approach
and consists of, circuit partitioning, derivation of specification of each analog structure, and
step-by-step design sequence in transconductance-load-bias structure order.

The important advantage of this design procedure is that it can be implemented as design tool
for analog design assistance. In this way we can formulate some basic analog design rules in
the field of analog circuit design which is largely based on hit and trial approach.

61