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الدوائر المنطقية والمعالجات الدقيقة PDF
الدوائر المنطقية والمعالجات الدقيقة PDF
אאאאא
١٢٣
א א
אאאאא א
W،،אא،א
א א א אא א א א א
אאא،אאאאאא
אאאאא
א ؛אאאאאא
K אא
אאאאאאא
א ،א אא
א א א א א א א ،
א،אאאא
אאאאאאא אאאאא
אאא،א
Kאא،א
??א?אאאאא?אא
Kאאאאאאאא
אאאאאאא
،א،אאאא
Kאאאאא
؛ א א א א
Kא
אאאא
אאאאא
אא
אא
١
אא א
אא אאאאא א
אאWאא
KאאאאאWאא
WאאאWאא
Kאאא K١
Kאאא K٢
Kאאאא K٣
Kאא K٤
Kאאאא K٥
K٪٩٠אאאWאאא
٦Wאאאא
Wאא
K א J
KאאאאאPower pointא א J
Wאא
א א א א אא א
Kאא
-١-
אא א
אא אאאאא א
Introduction
Wאאא
KאK١
KאאאK٢
KאאאאאאK٣
KאאאאK٤
?10?אאאאא
אאאאK?0,1,2,3,4,5,6,7,8,9?
8אאW128אאK?Positional Weight?
2אא،1א8א،E100 =1אאאFא
2אE101 =10אאFאאﻋﺸﺮون
E102 =100 אאFא1אא،10 א
WאאאK100א1א
אאאאאא
W10-1אאא
א?2?אאאאא
W?2?אאאאאא ?1,0?
... 24 23 22 21 20
W (25)10א(11001)2אא
24 23 22 21 20
1 1 0 0 1
(11001)2 = (1×24) + (1×23) + (0×22) + (0×21) + (1×20)
= 16 + 8 + 0 + 0 + 1 = (25)10
Wאאאא
אאאאא
WNאאאK?Bits?א
N 2 n (1-1)
K?Bits?אא nW
N 2 2 4 Wאא?2?אא
3
N 2 8 Wאא?3?אא
-٣-
אא א
אא אאאאא א
N 2 4 16 Wאא?4?אא
W?Bit?אא■
אאאאאא
21אאאא?1??1?20א
א،אאאKא ?4?22א?2?
אא?LSB?אא?Least Significant Bit?א א
אא?Most Significant Bit? א אאאא
K?MSB?
Repeated ?2אאאאאא
K?Division-by-2 Method
אאאאאאW
א،214אWא(14)10אא
א .א2א
אאאKאאאאא
Wאא،?MSB?אאאא?LSB?
אא
14 ÷ 2 = 7 0
7 ÷ 2 = 3 1
3 ÷ 2 = 1 1
1 ÷ 2 = 0 1
1 1 1 0
MSB LSB
Kא(25)10אאWE١ J١F
א א
25 ÷ 2 =12 1 (LSB) א
12 ÷ 2 =6 0
6 ÷ 2 =3 0
3 ÷ 2 =1 1
1(25)
÷ 210 =0 1 (MSB)
= (11001)2 Wא
א
אא
87 ÷ 2 = 43 1 (LSB)
43 ÷ 2 = 21 1
21 ÷ 2 = 10 1
10 ÷ 2 = 5 0
5 ÷2=2 1
÷ 210==1(1010111)02Wא
2 (87)
1 ÷2=0 1 (MSB) :אאאאאאW
K2אאאאאאאא
אא?Decimal Fractions?אאאא
Wאאאא(0.3125)10אא،2אא
אאא
MSB ( 0 . 0 1 0 1 )2 LSB
KEאFאאא
א
0.3125 2 = 0.625 0
0.625 2 = 1.25 1
0.25 2 = 0.5 0
0.5 2 = 1.0 1
Kא(39.25)10אאWE٣ J١F
-٥-
אא א
אא אאאאא א
א
אא
39 ÷ 2 = 19 1 (LSB) W٢אאאא
19 ÷ 2 = 9 1
9 ÷2=4 1
4 ÷2=2 0
2 ÷2=1 0
(39)10 = (100111)2Wא
1 ÷2=0 1 (MSB)
W2אאאא
MSB ( 0 . 0 1 )2 LSB
א
0.25 2 = 0.5 0 (MSB)
0.5 2 = 1.00 1 (LSB)
(0.25)10 = (0.01)2W
(39.25)10 = (100111.01)2Wאאא
אא?Bit?אאאא
Kאאא،
א
26 25 24 23 22 21 20Wא
1 1 0 1 0 0 1Wאא
4
(1101001)2 = 1 × 26 + 1 × 25 + 0 × 2 + 1 × 23 + 0 × 22 + 0 × 21 + 1 × 20
(1101001)2 = (105)10 W
-٦-
אא א
אא אאאאא א
א
?16?אאאאא
?A,B,C,D,E,F?א?0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F?
Kא?10, 11, 12, 13, 14, 15?אאא
-٧-
אא א
אא אאאאא א
א?16?אאאאאאאא
אאאאאאאאא
K?2? ?16?
WאאאאאאאW
?16?97אאאא(97)10אא
Kאא?16?אא
אאא אא
אא?MSB?אא?LSB?אאאKאא
W
אא
97 ÷ 16 = 6 1 (LSB)
6 ÷ 16 = 0 6 (MSB)
Wא
(97)10 = (61)16
Kאאא(314)10אאWE٦ J١F
א
אא
314 ÷ 16 = 19
A (LSB)
19 ÷ 16 = 1 3
1 ÷ 16 = 0 1 (MSB)
Wא
(314)10 = (13A)16
-٨-
אא א
אא אאאאא א
אאאאאאאW
אאאאאא
K?16?אא
MSB ( 0 . C 8 )2 LSB
א
0.78125 x16 = 12.5 C
0.5 x16 = 8.0 8
(0.78125)10 = (0.C8)16 W
א
W?16?אאאא
אא
329 ÷ 16 = 20 9 (LSB)
20 ÷ 16 = 1 4
1 ÷ 16 = 0 1 (MSB)
(329)10 = (149)16 Wא
Wאא?16?אא
א
0.52 16 = 8.32 8 (MSB)
0.32 16 = 5.12 5
0.12 16 = 1.92 1
0.92 16 = 14.72 E
0.72 16 = 11.52 B
0.52 16 = 8.32 8 (LSB)
(0.52)10 = (0.851EB8)16Wא?6?אאא
(329.52)10 = (149.851EB8)16 Wאאא
-٩-
אא א
אא אאאאא א
?A,B,C,D,E,F?א?0,1,2,……,9,A,B,C,D,E,F?אאא
אאאא،א?10,11,12,13,14,15?
KE٢ J١F?4-bit?א،אא
אאאWE١ J١Fא
א
(3A5)16 = 3 A 5
0011 1010 0101 = (001110100101)2
- ١٠ -
אא א
אא אאאאא א
א
(B35.D1)16 = B 3 5 D 1
אאאאאא
אאאאאאאא
Kאאא
א
0001 1011 1101 1010 0100
1 B D 4
A
Kאאא
(110111101.101001)2 = (1BD.A4)16
א
0001 1010 1011 0110 1000
1 A B 6 8
(110101011.01101)2 = (1AB.68)16
- ١١ -
אא א
אא אאאאא א
?Binary Digits? א ،א א א א
W
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
אאא،אאאאא
א10א،102א?2?א1 + 1
Kאאאא
א
4 1 0 0
+3 +0 1 1
EF 7 1 1 1
א
1 1
6 1 1 0
+3 +0 1 1
EF 9 1 0 0 1
- ١٢ -
אא א
אא אאאאא א
Wאא
KאאאW
KאאאאW
אאאאEאFאאא
Wאאאאאאאא
0–0=0
1–0=1
1–1=0
0–1=1 אא?1?אא
Wאאא
Kאא
Wאאאאאא א
Kאאאא א
א?0??1?א?0??1?Wאא א
K?0??1??1?אא
Kאאאאא
א
0א1א 0 1
1 0 1 א
אאא1
– 0 1 1 א
K1א1102
0 1 0
- ١٣ -
אא א
אא אאאאא א
אKאאאאאאא
Kאאאאאאאא
Wאא?1??0??0??1?אא
1 0 1 1 0 0 1 1 אא
0 1 0 0 1 1 0 0 אא
Wאאא
?1?אKאאWאא
1HאאZאאWאאאאא
،10110011אאאא
Kאא?1?אאא
1 0 1 1 0 0 1 1 אא
0 1 0 0 1 1 0 0 אא
1+ ?1?
0 1 0 0 1 1 0 1 אא
א(LSB)אאאאWאא
?1??0?א
אאאאאאאאא
אאאאאא Kא
Kאאאאאא
Wאא(10101101)2אא،
אא 1 0 1 0 1 1 0 1 אא
0101001 1 אא
- ١٤ -
אא א
אא אאאאא א
אאאאאאאא
אאאאאאאאא
?1?،א?0?א،אאא
Kא
אאאאאאאא
אא?Sign?אאא
K?Magnitude?
אאWאאאאאא
K?2's Complement?אא?1's Complement?אא?Sign-Magnitude?
אאאא?Bit?אא،אאאא
אאKאאאאא
Wאאא(+23)
00010111
א אא
(Sign Bit) (Magnitude Bits)
W (-23)אא
10010111
Kא(–23) ، (+23)אאא
- ١٥ -
אא א
אא אאאאא א
،אאאאאאאאא
(–23) אאאKאאאאאאא
Wאא
00010111 (+23)א
Kאאאאאאאא
אאאאאאאא
KאאאאאאKאא
W(+23)אא(–23)אא
00010111 (+23)א
11101001 (–23) א
Kאאאאאאא
،אאאא
אאאאאאאא
KE٥ J١Fאא،
אאאאאאאא
Kאאאאא
Kאאאאאאאא
- ١٦ -
אא א
אא אאאאא א
א
א אאאאאא
Wאאאא
01111010 א(+122)
+11110010 אא
(Discard carry)א 111101100 א(+108)
אאאאאאא
Wאא
א
Wאאאאאאא
אאאאאאא
Wאא
8 – 4 = 8 + (-4) = 4
- ١٧ -
אא א
אא אאאאא א
א
Wאאאאאאא
אאאא
Wאאאא
103 – (9) = 94
- ١٨ -
אא א
אא אאאאא א
אא
WאאאאאאאE٣ J١F
a) 14 b) 80 c) 560 d) 3000
e) 62500 f) 204.125 g) 255.875 h) 631.25
WאאאאאאאE٤ J١F
WאאאאאאאאE٥ J١F
WאאאאאאאE٦ J١F
WאאאאE٧ J١F
WאאאאאE٨ J١F
WאאאאאאE٩ J١F
WאאאאאאE١٠ J١F
אאאאאאאאאאE١١ J١F
W(8-bits) אא
אאאאאאאאאאE١٢ J١F
W(8-bits) אא
KאאאאE٨FאאE١٣ J١F
WאאאאאאאאאאאE١٤ J١F
WאאאאאאאאאאאE١٥ J١F
WאאאאאאאאאאאE١٦ J١F
WאאאאאאE١٧ J١F
- ٢٠ -
אאאאא
אאאא
אאאא
٢
אא א
אאאא אאאאא א
אאאאWאא
KאאאאאאWאא
WאאאWאא
Kאאאא K١
Kאאא K٢
Kאאא K٣
Kאאא K٤
Kאא K٥
Kאאא K٦
Kאא K٧
K٪٩٠אאאWאאא
٧Wאאאא
Wאא
K א J
אאאאאאPower pointא א J
Kא
Wאא
Kאאאא
- ٢٢ -
אא א
אאאא אאאאא א
Introduction
אאאאאאאאאא
Kאאאאא
אאאאאאא
אאאאאאאאא
Kאאא
א?Logic Functions?אאאאאANDאא
،?Logical Multiplication?אא،אא
אאאאאאא،א
?Two Binary Variables?אאאאBA א،E١ J٢F א
?1??Open? א?0?
K?Closed? א
(A)
(B) (L)
Voltage Source
אאANDאאWE١ J٢Fא
E١ J٢FKא،אא
(L)אא،א(L)אאא
K?Truth Table?אאאא، א
- ٢٣ -
אא א
אאאא אאאאא א
A
Y
B
ANDאאWE٢ J٢Fא
E٢ J٢F א ،AND א ?Standard? א א E٢ J٢F א
KANDאא
ANDאאWE٢ J٢Fא
א א
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
א،?1?A, Bא?1?א
אא?1? א،אאאAND
nאאאאאאNאאK?1?
Wא
N 2n (2.1)
- ٢٤ -
אא א
אאאא אאאאא א
א
Wא J
N 2 n 25 32
אANDאאWE٣ J٢Fא
אא א
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
אאאא?Boolean Algebra?אא
אא?Boolean Expression?אא،א
WאANDאאא،
Y A.B or Y AB (2.2)
אאא
E٣ J٢Fא،?LOW?א?HIGH?אא?Pulses?
Yאאt1אא?1?A, Bא
Bא?0?Aאt2אא،?1?א
- ٢٥ -
אא א
אאאא אאאאא א
אKאאאאא،?0?Yא
K?Timing Diagram?אאאאא
A
B A
Y
t1 t2 t3 t4 t5 t6 t7 B
Y
ANDאאאWE٣ J٢F א
ORאאK אאאאאאאORאא
،?Logical Addition?אא،א
KE٤ J٢F אאאאאאא
(A)
(L)
(B)
Voltage Source
אאORאאWE٤ J٢Fא
?0? BAאANDאא
K?Closed? א ?1??Open?א
- ٢٦ -
אא א
אאאא אאאאא א
אא،אאאE٤ J٢Fא
K א(L)אא
A
Y
B
ORאאWE٥ J٢Fא
ORאאWE٥ J٢Fא
א א
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
אt1אא?1?B،AאE٦ J٢Fא
Aא،t2אא،?1?א Yא
KאאאאאK?1? YאBא?0?
A
A
B Y
t1 t2 t3 t4 t5 t6 t7
B
Y
KORאאאWE٦ J٢Fא
- ٢٧ -
אא א
אאאא אאאאא א
YA (2.4)
،?1?אאאא ?0?אא
NANDאא،?0?אאאא ?1?
אאאאאאאאאא
- ٢٨ -
אא א
אאאא אאאאא א
אא،אא،AND،OR،NOTא
WאNAND
Y AB (2.5)
אt1אא?1?BAאE٩ J٢Fא
Aא،t2אא،?0?א Yא
אאאא،?1?Yא?1?Bא?0?
Kא
A
A
B Y
t7 B
t1 t2 t3 t4 t5 t6
Y
NANDאאא
WE٩ J٢Fא
Y A B (2.6)
A
B A
Y
t1 t2 t3 t4 t5 B
Y
NORאאאWE١١ J٢Fא
Wאאאאאא
Y A B AB A B (2.7)
XORאאאא،BAא
E١٣ J٢Fאא،NOTORANDאאאא
XORאאE١٤ J٢FאKאXORאאאאא
אאא ،אאא
Kאא
- ٣٠ -
אא א
אאאא אאאאא א
A
B
Y
K NOT،OR،ANDא XOR א אWE١٣ J٢F א
A
B A
Y
t1 t2 t3 t4 t5 t6 t7 t8 B
Y
XORאא אWE١٤ J٢F א
A
Y
B
XNORאWE١٥ J٢Fא
א،XORאאאXNORאאא
KאאאE١٥ J٢F
Yאא،E١٠ J٢FXNORאא
?0? A=B=1A=B=0 BAאא?1?
Kא
- ٣١ -
אא א
אאאא אאאאא א
Wאאאאאא
Y AB A B = A B (2.8)
אאXNORאאאא،אא
אאאE١٦ J٢Fאא، NOT ORANDאא
KאXNORאא
A
B
Y
NOT،OR،ANDאXNORאאWE١٦ J٢Fא
،אBAXNORאE١٧ J٢Fא
K?Y?אאXNORאא
A
B A
Y
B
t1 t2 t3 t4 t6 t8
t5
t7
Y
XNORאאאWE١٧ J٢Fא
- ٣٢ -
אא א
אאאא אאאאא א
אאאא،אאא
אאאא،אאאא
Wאאא،E١٨ J٢Fא
K AB A, B WאאANDאאאK١
K A C A, C WאאANDאאאK٢
K AB A C A B , A C WאאORאאאK٣
Y AB A C Wאאא
A AB
B
Y
C AC
KאאאאWE١٨ J٢Fא
א
A A B
D A B
B
Y
BC
C
D
E٢ J٢FאאאWE١٩ J٢Fא
- ٣٣ -
אא א
אאאא אאאאא א
E١٩ J٢F א א א א א
Wאאאאא،אאא
Y D ( A B ) (B C ) (2-9)
Wאאאא٢ J٢ J٢
אא،אאא
Wאא
Y AB(CD EF ) (2-10)
אאאא٣ J٢
Wאאאא
אא، Y 1אאאאE١٢ J٢Fא K١
א، A 0, B 1, C 0 אא Y 1אא
א،?1?אא A BC א
K ABC אאא?1?א،?0?
אאא A BC אאאאא
A, B , C אאא ABC אא،ANDא A , B , C
אאאORאאאא،ANDא
KE٢١ J٢FאאאאאאאאK،Y
A
B
C
Y
Y A BC ABC אאאא
WE٢١ J٢Fא
- ٣٥ -
אא א
אאאא אאאאא א
אאWE١٣ J٢Fא
אאאאא WE٣ J٢F
אא א KE١٣ J٢Fא
A B C Y
0 0 0 0 א
0 0 1 1
0 1 0 0 א א א א
0 1 1 1
א א
1 0 0 0
1 0 1 1
OR א Y 1 א
1 1 0 0
Wאאא
1 1 1 0
Y A B C A BC AB C
KE٢٢ J٢Fאאא
A
B
C
Y
A B C A BC AB C אאאאWE٢٢ J٢Fא
Wאאא٤ J٢
אאאאא
،(22 = 4)אא،(1 or 0)א
Kא،(23 = 8)،א
- ٣٦ -
אא א
אאאא אאאאא א
אאאא،אא
?0?،אאYא?1?אא
Kאא،אא
Y A B C A BC ABC ABC
א
א،אאא?A, B, C ?א
KE١٤ J٢Fאאאאא
Wאאאאאא
،Yא?1?אא
KYאאא?0?
אאWE١٣ J٢Fא
אא א
A B C Y
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
- ٣٧ -
אא א
אאאא אאאאא א
Wאאאאאאא٥ J٢
אאאאאא
אאאאאE١١ J٢FאKאא،אאא
Kאאא
אאאאWE١٤ J٢Fא
A + 0 = A ١
A + 1 =1 ٢
A . 0 = 0 ٣
A . 1 = A ٤
A+ A=A 5
+ A =1
A 6
A . A=A 7
A . A =0 8
A =A 9
A + AB = A 10
A+AB=A+B 11
(A+B)(A+C)=A+BC 12
Y AB A( A C ) B( A C ) (2-12)
א
Y AB AA AC AB BC Wאאאאאא
Y AB A AC AB BC WE7אאFAAAא
Y AB A AC BC WAB + AB = AB،A + A = A5א
Aא
Y A( B 1 C ) BC Wאאאא
Y A.1 BC W،A+1=12א
Y A BC W،A.1= A4אא
- ٣٨ -
אא א
אאאא אאאאא א
אאאאE٢٣ J٢Fא
אאאא،?EF?אא
K?EF?א
A
B
Y
A
Y
B
C
C
EF EF
KאאאאאאאאWE٦ J٢F
Y A B C A B C A BC ABC (2-13)
- ٣٩ -
אא א
אאאא אאאאא א
א
W،אאא،אאא
Y A B C A B C A BC ABC AB C C BC A A (2-14)
Y A B 1 BC 1 W6א
Y A B BC Wאאא4א
A
B
C A
B
Y Y
EF EF
אאאא WE٢٤ J٢Fא
- ٤٠ -
אא א
אאאא אאאאא א
אא
B E٢٥ J٢Fא
X
- ٤١ -
אא א
אאאא אאאאא א
אBAאאXNORאXאאאאE٦ J٢F
KE٢٧ J٢Fאאא
WאאאאאאאאE٨ J٢F
a) AB A B b) AB AB A BC
c) AB (C D) d) A B(C D( B C ))
- ٤٢ -
אא א
אאאא אאאאא א
אE١٥ J٢FWא
אא א
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
WאאאאאE١٠ J٢F
a) A B C b) A B B C
c) A AC A B d) A A A B
WאאאאאאE1١ J٢F
Y A B C A B C A BC ABC
- ٤٣ -
אאאאא
אאאאא
אאאאא
٣
אא א
אאאאא אאאאא א
אאאאאWאא
אאאאאאאWאא
WאאאWאא
NORNANDאאאאאאאא K١
Kאאאאא
א?Karnaugh-Map?אאאא K٢
KK-mapK-א
אאאאאאאא K٣
Kאאאא
K٪٩٠אאאWאאא
٩Wאאאא
Wאא
א J
אאאאאאאPower pointא א J
Kא
Wאא
Kאאאאאאאאא א
- ٤٤ -
אא א
אאאאא אאאאא א
Introduction
אאאאאאאאאאא
אאא،،אאאא
?10?א?Combinational Logic Circuit?אאאא
Kאאא
NANDאאאאאאאאאא
،אאאאאאNOR
א?Karnaugh-Map?אאאא
KK–map أوK א
אאאאאאאאא
Kאאאא
Demorgan's Theorems١ J٣
אאא،אא א
אא?Bars?אאKORAND
W،א
A B A B Wא
A B A B Wא
E١ J٣FאANDאORWאא
אאANDאאאאNORאא
אא،אאאאאא
KE١ J٣F
K?negative AND?אANDאאאאאא
- ٤٥ -
אא א
אאאאא אאאאא א
אWE١ J٣Fא
אא א
A B A B AB
A B
A A B A
0 0 1 1
0 1 0 0 B B
1 0 0 0
1 1 0 0 ANDORאWE١ J٣Fא
0 1 1 1
1 0 1 1
1 1 0 0 OR ANDאWE٢ J٣Fא
Kאאאא
Y (A B C ) (A B C ) WאאאWE١ J٣F
א
Y (A B C ) ( A B C ) ( A B C ) ( A B C ) A BC A BC ABC A BC
א
W NAND NORאאאא٢ J٣
א،ANDאאאאאאאאא
אNORאNANDאאאאא،OR
K?Universal Gates?
،AND،אאאאNANDאא
NANDאאא،NOR،OR
KאNANDאEEF٣ J٣Fאאאא
KEEF٣ J٣FאNANDאאAND
א،EEF٣ J٣FאNANDאאORאא
KEEF٣ J٣FאNOR אא
A A A A EF
AB AB
A AB A
B
K AB EF
B
A
A
A.B A B A
A+B EF
B B
B
A A.B A B
A
A B A
B
A B EF
B
B
ORAND،אאאNORאא،NAND א
NOTאNORאאE٤ J٣FאKNANDא
KNANDאORא
A A
A A EF
A A B A B A B A
A+B EF
B B
A A
A B A.B A
B
AB EF
B
B
A A A B A.B
A
A.B AB EF
B
B
B
WNORNAND אאאאאאא٣ J٣
Design of Combinational Logic Circuits using NAND and NOR Gates
אאאNORNANDאאאאא
NORאא،?Negative-OR?אORאאNANDאאאא
K?Negative AND?אANDאא
- ٤٨ -
אא א
אאאאא אאאאא א
WNANDאאא١ J٣ J٣
א،אORאNANDאא
Wא
A B A B
NAND Negative-OR
KE٥ J٣Fאאאאאא
A AB
B
Y = AB + CD
C
D
CD
NAND אאא
WE٥ J٣Fא
Y ( AB )(CD ) Wאא?Y?אאא
Y AB CD Wא
Y AB CD W?Bars?אאא
אאEEF٦ J٣Fא?Y?אא
אא،אORאאNANDאא
E٥ J٣Fאאא،EEF٦ J٣Fאא
(NAND-NAND-NAND) (AND-AND-OR)W،EEF٦ J٣Fאאא
A AB
A
B
Y = AB + CD
B Y = AB + CD
C C
EF EF
D D CD
E٥ J٣Fאאא AND-AND-OR WE٦ J٣Fא
- ٤٩ -
אא א
אאאאא אאאאא א
אאNANDאאE٧ J٣Fא
KאORאאאא
A AB
ABC
B
C
Y
D DE
E
DEF
F
אORאאאאאאWE٧ J٣Fא
WE٧ J٣Fאא?Y?א
Y [( AB)C ] [( DE ) F ] [( A B )C ] [( D E ) F ]
( A B )C ( D E ) F
( A B )C ( D E ) F
A
AB
( A B )C
B
C Y ( A B )C ( D E ) F
D
DE
E
(D E )F
F
אORאאE٧ J٣F אא אWE٨ J٣F א
(a ) Y ABC DE
(b) Y ABC D E
- ٥٠ -
אא א
אאאאא אאאאא א
א
KE٩ J٣Fאא
A A
B
ABC B
ABC
Y = ABC + DE C Y = ABC + D + E
C
D
D
EF E
EF
E DE
KE٣ J٣FאאאאWE٩ J٣Fא
אאANDאNORאNORאא
Wא
A B A B
NOR Negative-AND
KE١٠ J٣Fאאאאא
A B
A
B (A + B) (C + D)
C
D
CD
NORאאא WE١٠ J٣F א
Y A B C D Wאאאאא
Y ( A B) (C D) Wא
Y ( A B ) (C D ) Wאאא
- ٥١ -
אא א
אאאאא אאאאא א
אאא،NORאאE١٢ J٣Fא
Wא?Y ?א KאANDאא
Y [ ( A B ) C ] [( D E ) F ]
[ A B C] [D E F ]
( A B C )( D E F )
A A B
( A B) C
B
C
Y
D DE
E
(D E) F
F
NORאא WE١٢ J٣F א
KE١٣ J٣FאאאNORאאאANDאא
- ٥٢ -
אא א
אאאאא אאאאא א
AB
A
B C
A
B
C
Y ( A B C ) (D E F)
D DE
E
DE F
F
E١٢ J٣Fאאאאא WE١٣ J٣F א
א
A KE١٤ J٣Fאא
B A B C A B C
C Y A B C ( D E)
D
E
NOR אאאאא WE١٤ J٣F א
WKarnaugh Map٤ J٣
אאאאK-
אKאאאא
،?Cells?א?Array?،א
אאKאאאא
Kאאא
- ٥٣ -
אא א
אאאאא אאאאא א
،،،אאאא
א،אא،א
Kאאא
א،?א?אאאא
? A, B ?א?A وB?א،E١٥ J٣F
K?00, 01, 10, 11?
A B Y B B
0 0 AB
AB AB
0 1 AB
A
1 0 AB A AB
AB
1 1 AB
אWE١٥ J٣Fא
،אאאאאא
E١٦ J٣Fאא?Input Labels?א
،אא A אאא،Kאא
אא B אאKאאAא
אאאא،KאאאBא،א
EEF١٦ J٣F،EEF١٦ J٣F،EEF١٦ J٣FאK AB א
K??א،??א،??
CD CD CD CD
AB
AB
BC BC BC BC B B
AB A A
AB A - ٥٤ - A
4 3 2
אא א
אאאאא אאאאא א
،א
אאא،אאא
KEEF١٧ J٣Fא
א،אאאאWאא
١٧ J٣FאORאאא،א?1?א
KEEF١٧ J٣FאאאאאאEEF
KEEF١٧ J٣FאאאאWאא
B B B B A A B B
A 0 0 A 0 0
Y
A 1 1 A 1 1
EF A
EF EF
Kאאא WE١٧ J٣F א
אא
?1?א?1?אKאאאא
א?0?א?0?א،אא
?אאא?1?Kא
- ٥٥ -
אא א
אאאאא אאאאא א
אאאWאא
אאאK A A 1 Wא،?Complements?א
אאאא،EEF١٧ J٣Fא
אאEEF١٧ J٣FאאKא
אא،א?Adjacent cells?
אאא،א، א
אאאEEF١٧ J٣Fא?1?
،א B ، B AB, AB אאא،אאא
WAא
Y A( B B) A 1 A Wא Y AB AB Wאאא
EEF١٧ J٣Fאאאאאאאא
אאא ،AאYאא
KEEF١٧ J٣Fא
- ٥٦ -
אא א
אאאאא אאאאא א
א
WאאאאWאא
?1?אWאא
אא
E٣ J٣Fא?1?אKE١٨ J٣FאYא
?0?KE١٨ J٣Fאאא?1?
Kאאא
BC BC BC BC
1
A
A 1 1 1
AB EF
BC
E١٨ J٣Fאא?1?אWאא
EאאFאאאאאא
אא، BC א A, A אאאא
אאאאאK AB א C, C א
KE١٩ J٣Fאאאא،אא
A A B B C C
Y AB BC
Y
- ٥٧ -
אא א
אאאאא אאאאא א
ANDאאאאא
١٢אאאא OR אא
K
ANDאאאא
א٤אאאאא،ORא
KE١٩ J٣Fא
?א?א1'sא
E٢١ J٣FאE٢٠ J٣FאK2אא،،
Kאאאא،א
אא1'sאאא
אאKאאאא
Kאא،1'sאאא
CD CD CD CD AB CD CD CD CD
1 1 1 1 1 0 1 1
AB AABB AC
1
AB 1 0 0 1 AB 1 0 1 1
AD 1 1 1 0 AB 1 0 0 1
ABC
AB 0 1 1 0 AB 1 0 1 1
AD
EF D BC EF
EאF EאF
Y ABC D ABC D ABCD ABCD Y A B C D A B CD A B CD A BC D
ABC D ABCD ABC D AB
C D A BCD A BCD ABC D ABCD
ABCD ABC D ABCD AB C D AB CD AB CD
F
Eא EאF
Y ABC AD AD AB Y AC BC D
אאWE٢٠ J٣Fא
- ٥٨ -
אא א
אאאאא אאאאא א
B
CD CD CD CD CD CD CD CD
1 1 0 1 0 0
BD
1 1 AB
AB
0 1 1 0 1 1 0 1
AB
D
AB
CD
AB 1 1
AB
0 1 1 0 1 0
AB
1 1 1 1 AB 1 1 1 1
AB
EEFF EאF EF EאF
A A B CD
Y A B C D A B C D A B CD Y A B C D A BC D A BC D A BCD
A B C D A BCD AB CD ABCD ABC D ABC D ABCD AB C D
AB C D AB C D AB C D AB CD AB C D AB CD AB CD
Y BD EאF Y C D AB BD EאF
אאWE٢١ J٣Fא
א
،E٢٢ J٣FאאWאא
KאאאYאא1's
CD CD CD CD
AB 0 1 1 0
AD
AB 0 1 1 0
AB 0 0 1 0
CD
0 0 1 0
AB
E٦ J٣Fא WE٢٢ J٣ Fא
אE٢٢ J٣FאWאא
אאאא،1'sא
C א C א B א B א،1's
1'sאאאK AD א
אאאK CD א A, A, B, B אא
Y AD CD W
אאאאאאאאאא
Kאאאאאאאאא
- ٦٠ -
אא א
אאאאא אאאאא א
אאאE٥ J٣Fא،אאאא
.Carry (C)אאאSum (S)אא A, B אא
אאאאWE٥ J٣Fא
אא א
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
אא،XORאאא Sאא
EEF٢٣ J٣Fא .ANDאא Cא
אאא C, S אא A, B אאא
Kא
A B
A
S (Sum) א
HA B
C (Carry) א
S
EF
C
EF
אEEF٢٣ J٣Fאאאאאא
S ,Cאאאא،אאHalf AdderHA
Wא،אא
S AB A B (3.2)
C AB (3.3)
- ٦١ -
אא א
אאאאא אאאאא א
א2-bitsאאאא
א،אאאCarryאאא
אאBitsאא
א ،אא
Kאאאאא،א
،אBitsאאאאא
אאאאA,Bאאא،א
،אאאאאInput carryECinFא
KE٦ J٣Fאאאא،Sum
אCarryא
- ٦٢ -
אא א
אאאאא אאאאא א
אא،אאאאאא
WSאאאא
Wאא C א
אא،EEF٢٤ J٣FאאCS
אFAאEEF٢٤ J٣Fאאאא
Kאא?Full Adder?
A B Cin A
B S (Sum)
FA
S C Cin
C (Carry)
EF EF
Kאאא אWE٢٤ J٣F א
- ٦٣ -
אא א
אאאאא אאאאא א
אאאEEF٢٤ J٣Fאאא
ORא2אאאאORאא
KE٢٥ J٣Fא
A
Cin S S
HA
A S B C
HA
C
B C
Kאא אWE٢٥ J٣F א
אאא
Kאאא
אא،
Bit،א،אאאאאא
אאאאאא
KDifference
Borrowed?1?א،אאא
،
،אא
K
א?D??2-bits?אאאא
אאKאא?1?? B0 ?
אאאאא،אא?1?אאאא
Kאא،
אאאא?אאאאE٧ J٣Fא
Wאא B0 א،DאאK?א
- ٦٤ -
אא א
אאאאא אאאאא א
D AB AB & Bo AB (3.11)
אאאאWE٧ J٣Fא
אא א
A B D B0
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
אאSאDא
AאאאCא B0 א، XOR א
K B ، A א AND א
A B
A
D (Difference) א
B
HS
B0 (Borrow) א
D B0
אאEF אאאEF
אאאאאאWE٢٦ J٣Fא
1אא 2-bitsאאאאא
אאKאאאKאא
DאאאאKא Bi n אאBאA
אאאE٨ J٣Fאא، B0 א
- ٦٥ -
אא א
אאאאא אאאאא א
K A B Bin אאאKאאא
Kאאאא Bin 0 אא
KאאאאWE٨ J٣Fא
אא א
A B Bin D B0
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Wאאאאא
אE٤ J٣FאFאאS
Wאא
WאאאB0א
Bo Bin ( A B ) AB (3-15)
- ٦٦ -
אא א
אאאאא אאאאא א
אאא،EEF٢٧ J٣FאB0Dא
Full SubtractorאFSאEEF٢٧ J٣Fאא
אאEEF٢٧ J٣FאאאKאא
KE٢٨ J٣Fאאא،ORאאא
A
B Bin
A
B D
FS
Bin B0
D B0
אאאאEF
אאEF
KאאאאאאWE٢٧ J٣Fא
Bin A
D
D
HS
D B B0
A
HS
B0 B0
B
אאאאאאWE٢٨ J٣Fא
- ٦٧ -
אא א
אאאאא אאאאא א
אא
WאאאE١ J٣F
a) AB(C D) b) AB (CD EF )
c) ( A B C D) ABC D d) ( A B C D )( A BC D )
a) ABCD DE b) ABC AB D
c) ABC D E d) ABC ABC ABC ABC
a) ( A B C )( A B ) b) ABC ( D E )
c) ( AB C )( D E F ) d) ( A B )(C D )
WאאאאאE٤ J٣F
אאWE٩ J٣Fא
אא א
A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
a) A = 1, B = 1, Cin = 1 b) A = 0, B = 1, Cin = 1
c) A = 0, B = 1, Cin = 0 d) A = 1, B = 1, Cin = 0
WאאאאאאאאאאE٧ J٣F
a) S = 0, Cout = 0 b) S = 1, Cout = 0
c) S = 1, Cout = 1 d) S = 0, Cout = 1
a) A = 1, B = 1, Bin = 1 b) A = 1, B = 0, Bin = 1
c) A = 1, B = 1, Bin = 0 d) A = 0, B = 1, Bin = 1
- ٦٩ -
אא אאא
אאאא
אאאא
٤
אאא א
אאאאWאאא
אאאאאאWאא
WאאאWאא
Kאאא K١
Kאאא K٢
Kאאאאא K٣
KאאEאFאא K٤
K٪٩٠אאאWאאא
١٢Wאאאא
Wאא
K א J
אאאאאאPower pointא א J
Kא
Wאא
Kאאאא א
- ٧٠ -
אאא א
Introduction
אא،אאאאאאאאאא
אوא،?Flip-Flop Circuit?אאאאא
K?1?א?0?אאא
K?1?אאא?0?אאאא
אאאאאא
אא
אאאאאא אאאא
א،NORאNANDאא?Bi-stable Multi-vibrator?
אאK?Digital Integrated Circuits?א
K?Shift Registers?אא?Counters?אאאא
WFlip-Flop's א١ J٤
WLatchesא١ J١ J٤
אאאאאא
אאאאאKאא
אאאאאאא
אאאאאאKאא
Kאא
- ٧١ -
אאא א
KBistable Multi-vibratorאאא?Latch?א
SRאאאאאE١ J٤Fא
R?1?אא?Set Input?אS
?0?אא?Reset Input?א
Kא Q אQ
SET
Q output
Inpu S Q
RESET R Q Q output
Input
SRאאאאאWE١ J٤Fא
Q 0 , Q 1 Setאא
אאK Q 1 ، Q 0 Reset
EאאF Q 1אא?1?אSא
אK Q 0 אאא،א Q א
،EאאF Q 0 א Q 1 א?1?אRא
אא?1?אאS, Rא
Kאאא،?Unpredictable?א
אאאאNORאSRאא
KE٢ J٤Fאאאאאא
S
Q
Q
R
אאאא SR אא WE٢ J٤Fא
- ٧٢ -
אאא א
אאF?1?NORאאאאא
אאאאאאא،Eא
.?Active High Inputs?אאאאאאאאא،E١ J٤F
אאאSRאאאWE١ J٤Fא
אא א
א (Mode of Operation)
S R Q
0 0 Q0 EאFא No Change
0 1 0 א Latch RESETS
1 0 1 א Latch SETS
1 1 ? א Invalid condition
Wאאא
אאS ,Rא?0?אא -١
K Q o אאאאEאאFא
אF Q 0 א?1??0?Rאאא -٢
K Q 0 א،אאEא
אאאS, Rא?1?אא -٤
Kאאאא،NORאא
אאאאא -٥
،אאאאא،אא
Kא
- ٧٣ -
אאא א
אאאE٣ J٤FאNANDאאא
E٢ J٤Fאאאאאא?0?NANDא
K?Active Low Inputs?אאאאאאאאא
S
Q
Q
R
אאאא SR אא WE٣ J٤F א
אאאSRאאאWE٢ J٤Fא
אא א
א
S R Q (Mode of Operation)
0 0 ? א Invalid condition
0 1 1 אא Latch SETS
1 0 0 אא Latch RESETS
1 1 Qo EאFא No Change
Wאאא
אאאאאא?0?א K١
KEאאFאNAND
?1?אא R 1 S 0 אאאא K٢
K Q 1 אא،אא
،?0?אא R 0 S 1 אאאא K٣
K Q 0 אא،אאאא
אאאאא?1?אא K٤
KEאאF Q0
- ٧٤ -
אאא א
S S Q Q S S Q Q
R Q Q R R Q Q
R
LOWאאאאEFHIGHאאאאEF
אאאאא אאא אWE٤ J٤Fא
אאאאאאאא
S 0, R 0 K Q אא S, R
Kאא
א
S
R
Q
KאאאאWE٥ J٤Fא
Q אאאאאאא SR SRא
،אאאאאאאאאא
Kאאאאאאאא
- ٧٥ -
אאא א
EאFאאאאא
אאאאאא
א אאSRאא،אא
אאאK א
KCKאא?Clock Pulse?אאא
אאSRאאE٦ J٤Fא
KCKאאא
S Q S Q
CK CK
R EFE
Q R F
Q
אאEFאא EF
אאSRאאWE٦ J٤Fא
אאאEEF٦ J٤Fא
א?Positive Edge Trigger?אאSRא
אEEF٦ J٤Fא،?1??0?א
K?0??1?אא?Negative Edge Trigger?אא
א،NANDאאאאSRאאE٧ J٤Fא
אאKאאאאNAND
אאאאQאS ,Rא
Kאאא
S
Q
CK
Q
R
אאSRאאWE٧ J٤Fא
- ٧٦ -
אאא א
אאSRאאאWE٣ J٤Fא
אא א
א (Mode of Operation)
S R CK Q
0 0 X Qo EאFא No Change
0 1 0 אא Latch RESETS
1 0 1 אא Latch SETS
1 1 ? א Invalid condition
WאאאאSRאE٣ J٤Fא
א?0?אאS, Rאא،אCKאא K١
Kאאאא
?1??0?אא S 0, R 1אRאא K٢
.Resetאאא?0?א
?1??0?אא S 1, R 0 אאSאא K٣
.SetאאאQ = 1א
א S 1, R 1 אא K٤
Kא
?1?)אאאאSRאא
אאאאאא (?0?
Kאאאא
א
K Q 0 Qא، S 0, R 0 Wאאא -١
K(Reset) Q 0 א، S 0, R 1Wאאא -٢
- ٧٧ -
אאא א
S
R
Q
SRאאאאWE٨ J٤Fא
?Single Bit?אאאDאאא
אאאאSRאאאK?10?א
KE٩ J٤FאD
D S Q
CK
R Q
אאDאאDאאא
، R 0 א S 1א?1?אאDאKCK
DאK (Set)?1?אאאא،CKאאא
،CKאאא، R 1א S 0 א?0?אא
K(Reset)?0?אאאא
- ٧٨ -
אאא א
?Reset?אא،אא?1??Set?אא
אDאאאאאKאא?0?
KE٤ J٤Fא?Positive Edge Trigger?אאאאא
אא א
א (Mode of Operation)
D CK Q
1 1 אא (SET) (stores 1)
0 0 אא (RESET) stores 0)
אKאאDאQאא
אאDאאאאאEEF١٠ J٤F
אאK?Delayed time Filp-flop?אאאCK
KEEF١٠ J٤FNANDאD
D
S
Q
D
Q
CK
CK
Q Q
R
EF E F
NANDאDאאWE١٠ J٤Fא
אאDאאאQאאW٣ J٤
אאאKE١١ J٤FאDאאE١٠ J٤F
Kא Q 0
- ٧٩ -
אאא א
א
CK
D
Q
DאאאאאE١١ J٤Fא
אאאSRא JKא
JKאא.(Reset)אא(Set)אאאא
KSRאא
אאJKאאEF אאJK אEF
אאWE١٢ J٤Fא
KאאאאJK
- ٨٠ -
אאא א
SRאאאאאE١٢ J٤Fא
Kא Q ، Q א
אאא،JKאE٥ J٤Fא
אאאא،?0?J, Kא
א،אא J 0, K 1 אא?0?א(Reset)א
J 1, K 0 אאJK(Set)אאאא
،?Toggle?אJKאאאאKאא
אאQא?1?אאJ, Kא
KCKאאא
אאJKאWE٥ J٤Fא
אא א
א (Mode of Operation)
J K CK Q
0 0 Q0 EאFא No Change
0 1 0 אא (RESET)
1 0 1 אא (SET)
1 1 Q א Toggle
K
Q
KאאJKאאאאWE١٣ J٤Fא
- ٨١ -
אאא א
אאא?1?J, K،אאא -١
K?1?אQ
K J K 0 אאאאאא -٢
K Q 0 Reset J 0, K 1،אא -٣
K Q 1 Set J 1, K 0 ،אאא -٤
QאJ, KאאאSet א-٥
K?1?א
אאאJKאאTאאא
Tאא،E١٤ J٤FאאJ,K
(Toggle)אTאKאאTאא
Kאא
אא،אאCKא?1?אTא
אאאאאאCKאאא
אKE١٤ J٤FאCKאאאאא
KTאאE٦ J٤F
T J Q
CK
K Q
TאאאאאWE١٤ J٤Fא
TאאWE٦ J٤Fא
אא א
א (Mode of Operation)
T CK Q
0 Q0 EאFא No Change
1 Q0 א Toggle
- ٨٢ -
אאא א
אTאאTאאאQאאW٥ J٤
Kא Q 0 אאE١٥ J٤FאCK
א
CK
T
Q
TאאאאאWE١٥ J٤Fא
א،אאאT=1אQאא
Kא?1??0?Q T 1אא،Qא T 0 א
:Shift Registersאא٢ J٤
،אא،אאאאאא
אא?Bit?אאאא
א،אאא،
אאא
א ?Left Shift?אאא?Buffer Register?אא
א?Parallel Data?א?Serial Data?אאא?Right Shift?
K?Shift Registers?אא
?Digital word?א
אאאEEF١٦ J٤FאK?Bits?אא
אאאאא?4-stages? א Dא
K?Positive edge-triggered?
- ٨٣ -
אאא א
D Q D Q D Q D Q
Q
Q Q Q
CLR CLR CLR CLR
CK
CLR
Q1 Q2 Q3 Q4
?Parallel data outputs? אאא
Dאאאאא EF
Clock
1
D1
0
D2
א
Input data D3 1
0
D4
Q1
א
Q2
Output data Q3
Q4
אאא
EF
אאאW١٦ J٤Fא
- ٨٤ -
אאא א
א،אאא
אא Jאאא،אא
א?Clear-input?אK?Parallel-in, Parallel-out Registers?
Kאא?Active-low?אא
א?Shift?א?move?אאאא
WE١٧ J٤Fאאאאאא،
E F
Serial-in, parallel-out "SIPO" Shift Registers Parallel-in, Serial-out "PISO" Shift Registers
Parallel Data In
Serial-In
Serial-Out
אאא
Wא
אאאKאאE٧ J٤Fא
א1001אאאאEאאF0110א
Kאא
אא
WE٧ J٤Fא
אא אאא א
Clock Input Q0 Q1 Q2 Q3
- - 0 1 1 0
1st 1 1 0 1 1
2nd 0 0 1 0 1
3rd 0 0 0 1 0
4th 1 1 0 0 1
אא4-bitsאאEEF١٨ J٤Fא
א،FF0אאאDאאאאKDאא
Q1אאא،FF1אאאDאQ0אא
- ٨٦ -
אאא א
אאאQ2אאא،FF2אאאא
Kאאאאאא Q3 אאאא،FF3אא
FF0 FF1 FF2 FF3
Serial Serial
Data D Q0 D Q1 D Q2 D Q3
Data Out
Input
CK CK CK CK
Clock
Input
SISO Shift
Right
EF
Serial
Serial Data
Data Out Input
D Q3 D Q2 D Q1 D Q0
CK CK CK CK
Clock
FF3 FF2 FF1 FF0
Input
Shift
SISO Left
EF
،א ?Clock input? אא
،א א 1-bitאאא?Positive edge?
אאא אא –אאאא
אא אא ،אא
Kא
DאאEEF١٨ J٤Fאאא
.?SISO Shift-Right Shift Register?אא–אאאאא
- ٨٧ -
אאא א
אאאEEF١٨ J٤Fאאא
K?SISO Shift-Left Shift Register?אא–אאאDא
אאאאאאאאE١٩ J٤Fא
Kאא–א
4-bitsאאאא،אאא
אFאאאאא?Serial data input?אאא
KEאאא
Serial
FF0 FF1 FF2 FF3
Data Q0 Q1 Q2 Q3
D D D D
Input
CK CK CK CK
Clock
Input
Q0 Q1 Q2 Q3
Parallel data outputs
אא Jאאא WE١٩ J٤F א
- ٨٨ -
אאא א
אאאאא?4-bits?
אאאאאאאKא
Kאא?4-bits?Q3,Q2,Q1,Q0
אאאE٢٠ J٤Fא
אאאKDאאאאאא–א
،Lowא SHIFT / LOAD אK SHIFT / LOAD א
א?Enabled?AאאAND אא
אאאאאK?Inverter?א
Clock ?אאKאאאאD3,D2,D1,D0
.Q3,Q2,Q1,Q0אאאא،?pulse
( SHIFT / LOAD ) control
(1 for shift , 0 for load ) Parallel data inputs
D0 D1 D2 D3
B A B A B A
FF0 FF1 FF2 FF3 Serial
Out
D Q0 D Q1 D Q2 D
Q3
CK CK CK CK
Clock
Input
Kאא Jאאא WE٢٠ J٤F א
- ٨٩ -
אאא א
WCountersאאא٣ J٤
אKאאאאאא
אאאאא،?Binary bits?אא
אאא،?Clock input?אאאאא
אאאאאאאאא
Kאאאאא
אאאאאאאא
אK?Synchronous Counters? אאאאא?Asynchronous Counters?
Kאאאאאאאאאא
،אאאEEF٢١ J٤Fא
אאאאKאאJKא
Kאאאאאאא
א،HighאJ, Kא
Kאא?Negative edge??Toggle?א
אQאאאאאאא
KEEF٢١ J٤Fא
- ٩٠ -
אאא א
א?4-bit word?אאQ3,Q2,Q1,Q0א
אאא0000אא
FF0אאKE٨ J٤Fאאאא
KQ3MSBFF3אאQ0LSB
FF0 FF1 FF2 FF3
J Q0 J Q1 J Q2 J Q3
Clock CK
CK (
Input CK
CK CK
K K K K
Q0
Q1 Q2 Q3
א٤ אא E F
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Q0
0
Q1
0
Q2
0
Q3
0
אאא EF
אאאאWE٢١ J٤Fא
- ٩١ -
אאא א
،?Clock input?אאאFF0אא
אאא?Toggle?Q0א
Q0אאאאאא،EEF٢١ J٤FאQ0א
Q0אא Kא?0? ?1? אאא ?1? ?0?
Q0 ،FF1אא א
، Q2 א Q1 K?Toggle? Q1 א
KQ3אQ2
אאאאאWE٨ J٤F
אא
Q3 Q2 Q1 Q0 א
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7 Cycle Repeats
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 13
1 1 1 1 15
Binary Count
- ٩٢ -
אאא א
אאאא،אאאאא
WאMaximum count before cycle repeats
N 2n 1 (4-1)
K?Number of flip-flops in the counter circuit?אאאאא nW
WאEEF٢١ J٤Fאאאאא
N 2 n 1 2 4 1 16 1 (15 )10 (1111) 2 (4-2)
WModulus of Counter MODאא
אאMOD?Modulus of counter?אא
16MODEEF٢١ J٤FאאאאKאא
KE٨ J٤Fא11110000 16אא
WאאאMOD
n
MOD = 2 (4-3)
WAsynchronous Binary-Down Countersאאאאאאא٢ J٣ J٤
אאאאאאאאא
אאאאאאאאאK?1?
אEEF٢٢ J٤FאKא?1?א
Q אKJKאאאא
Kאאא Q אא
- ٩٣ -
אאא א
KאKKK،FF2א Q 1 K?0??1?
Q0 Q1 Q2 Q3
HIGH
FF0 FF1 FF2 FF3
J Q0 J Q1 J Q2 J Q3
Clock
CK CK CK CK
Input
Q0 Q1 Q2 Q3
K K
EF
K K
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Clock
Input
0
Q0
0
EF
Q1
0
Q2
0
Q3
אאאא WE٢٢ J٤Fא
אא
א
Q3 Q2 Q1 Q0
1 1 1 1 15
1 1 1 0 13
1 1 0 1 13 אWE٩ J٤F
1 1 0 0 12 אאאא
1 0 1 1 11
1 0 1 0 10
1 0 0 1 9
1 0 0 0 8 Cycle Repeats
0 1 1 1 7
0 1 1 0 6
0 1 0 1 5
0 1 0 0 4
0 0 1 1 3
0 0 1 0 2
0 0 0 1 1
0 0 0 0 0
Binary Count
- ٩٤ -
אאא א
(15)10 = 1111Q3,Q2,Q1,Q0אאאאאא
אאאאאKE٩ J٤F אאאא
אKאאאא
FF0אא،EEF٢٢ J٤Fא
Q3,Q2,Q1א،אQ0א،אא
Kאאאאאא
WאאאLאאאאא٣ J٣ J٤
אאאא،אאאאאאא
Q אאאאאאאאא
K Q אאאאאאאאא
LאE٢٣ J٤Fא
K UP / DOWN אאAND-OR
Q0 Q1 Q2 Q3
HIGH
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J A J A J A J
Clock
CK CK CK CK
Input
Q0 Q1 Q2
Q3
K B K B K B K
UP/DOWN
Control
אANDאJKאאE٢٤ J٤Fא
אאMOD-16 أو4-bitאאא
אאאאאאא??אא
، אאאאאאאKאאא?Trigger?
Kאאאא
Q3
Q0 Q1 Q2
HIGH
A B
FF0 FF1 FF2 FF3
Q1
Q3
J Q0 J J Q2 J
CK CK CK CK
Clock K K K K
Input
Kאאא WE٢٤ J٤F א
FF0אאJ, Kאאאאא
א?Toggle?א،Highא
Lowא،אאאאאאאא
KאLowHighHigh
א2אאאFF1אאJ, Kא
אאQ1א،LowאQ0אאKFF0א
Q1א،HighאQ0א?No change?FF1
K?Toggle?
- ٩٦ -
אאא א
AND-AאאFF2אאJ, Kא
،High AND-Aא Q0 Q1 HighאKQ0 ,Q1
KאאFF2אא?Enable?אא
אאAND-BאאFF3אאJ, Kא
AND-BאHighאQ2,Q1,Q0אKQ2,Q1,Q0
KאFF3אאאאHigh
- ٩٧ -
אאא א
אאאא
א א א Kא א א
אאאאאא
אאE٢٥ J٤Fא Kא אא
Kא
So 0
S1 1
Do 0 Mux Y
אא D1 1
D2 2
D3 3
١ ٤ WE٢٥ J٤Fא
א S אE٢٥ J٤Fאאאא
S1 0, S 0 0 ?0? א א א ،א א א א
אאא،אD0אא
אאא،א D1א S1 0, S 0 1 ?1?
אאאא،אD2א S1 1, S 0 0 ?2?
KE١٠ J٤Fא،אD3א S1 0, S 0 0 ?3?
אאאWE١٠ J٤F
S0 S1 א אא
0 0 D0 Y D0 S1 S 0
0 1 D1 Y D1S1S0
1 0 D2 Y D1S1 S 0
1 1 D3 Y D1S1S0
- ٩٨ -
אאא א
אאANDאאא
KE٢٦ J٤FS1, S0אאORאא
S0
S1
D0
D1
Y
D2
D3
אאא
WE٢٦ J٤Fא
D0
א א W٦ J٤
D1
א אא
D2
E٢٧ J٤F א
D3
א א
S0 0 1 0 1 0 1 0 1
KE٢٦ J٤F
S1 0 0 1 1 0 0 1 1
Y
א אא
KאY
D0 D1 D2 D3 D0 D1 D2 D3
אאאWE٢٧ J٤Fא
WDemultiplexers אא٥ J٤
א א א א א א
K?Data subscriber? א א א א
- ٩٩ -
אאא א
א א א E٢٨ J٤Fא
אאא אא KANDא א
Kאאאאאאאא
Data
Input D0
D1
Data
S0 Output
Lines
Select D2
Lines
S1
D3
א
אאאאא
KE٢٩ J٤FD3, D2, D1, D0
S0
S1
D0 1 0
D1 1 0
D2 0 1
D3 1 1
א אאWE٢٩ J٤Fא
- ١٠٠ -
אאא א
אאא
אאאאSRאאQאאE١ J٤F
א א?Negative edge trigger?אא
Q 0 אאאKE٣٠ J٤F
Kאא
CK
D
E٢ J٤FאאWE٣١ J٤Fא
אאאאJKאאQאאE٣ J٤F
KE٣٢ J٣FאאNegative edge triggerאא
Kאא Q 0 אאא
- ١٠١ -
אאא א
CK
J
K
E٣ J٤FאאWE٣٢ J٤Fא
אאאTאאאQאאE٤ J٤F
אא?Negative edge trigger?אאא
Q 0 אאאKE٣٣ J٤F
Kאא
CK
T
E٤ J٤FאאWE٣٣ J٤Fא
S1=0, S0=1, D3=0, D2=1, D1=0, א٩٥אE٢٥ J٤FאE٥ J٤F
KאD0=1
- ١٠٢ -
אאאאא
א
א
٥
אא א
אWאא
KאאאאאאWאא
WאאאWאא
Kאאאא K١
Kאאאא K٢
Kאאא K٣
Kאאאא K٤
K٪٨٠אאאWאאא
٥Wאאאא
Wאא
K א J
אאאPower pointא א J
Kא
Wאא
Kאאאאא א
-١٠٣-
אא א
Introduction
א אאאאא
אאאאאאאאאאאא
אאאאא
אאאאאא
אאאאאאאא
K
אאאאאאא
Wאאא١ J٥
-١٠٥-
אא א
-١٠٦-
אא א
אאWאא
Input and Output ?אא?Memory?אא?Central Proccessing Unit CPU?
?Data Bus?אאאאא?Devices
אאK?Control Bus?א?Address Bus?אא
KE١ J٥Fאאא
אWא
Wא
אא
Wא Wא
WE١ J٥Fא
WMotherboardאא٢ J٥
،אאאא
،אאאא،אאא א
?Motherboard?אאאא
אאאאא،E٢ J٥Fא
?Clock?א?Logic Gates?אאא?Multiplexers?אאא
K?Power Supply?א
?Motherboard? אא WE٢ J٥F א
-١٠٧-
אא א
WאאLא٣ J٥
Kאאאאא
אאאאאאא
Kאאאאא،א
Parallel TransmissionאאאW
D7D6D5D4D3D2D1D0אאאאאא
Kאאא
Do
D1
D2
אL
D3
D4
D5
D6
D7
א
אאאא
אאאWE٣ J٥Fא
אאאא אאאא
KE٤ J٥Fאאאאאאא،א
-١٠٨-
אא א
אא
אL
D0 D1 ----D7
D7 D6 ----D0
א
אא
אאא WE٤ J٥ Fא
WאאLאאאא٣ J٣ J٥
?Handshaking?אאאא
אאא،אאLאאא
אאאאאאאKאא
WאאKאא
א
אL
א
אא
אאWE٥ J٥Fא
-١٠٩-
אא א
אא?Data Available?אאאאא
Wאאאאא،?Data Acknowledge?
KאאLאאאא
אאאא א
KאאאאKא
Wאא٤ J٥
Wאא١ J٤ J٥
אK10אאא
KE٦ J٥Fאאא?Word?
Wאאאאאאאא
Kאאאאאאא
Knאאא2n אאא
16 12 10 8Wאא
WE١ J٥F
21621221028Wאא
26Kbyte22 Kbyte1Kbyte256 byteWאא
-١١٠-
אא א
Wאאא ٢ J٤ J٥
Kאא
KTemporary א
Kאאא
אאאאא
אא
Kאאאא א
Kאא א
،אאאאאאא
אאאאאאאא
Kאאאא
1
1 2د 1د 4خ 3خ 2خ 1خ
2
0 0 0 0 0 1
2 0 1 0 0 1 0
3 1 0 0 1 0 0
4 1 1 1 0 0 0
אא?43،2،1?אא?A14A15?אא
KE٨ J٥Fא
1 CS
A15 1
2 CS
A14 2
3 CS
4 CS
אאאאWE٨ J٥Fא
Wאאאא٤ J٤ J٥
WאאEאLאאF
KERD: ReadFא
KEWR: WriteF
K(CS: Chip Select) א
Wאאאאא
Kאא،אאאאאאאא K١
אEאאFאאאK K٢
Kא
K אא K٣
Wאאא٥ J٤ J٥
אאאאאאאא
אאאKא
אאאאאK?Memory Access Controllers?
Kא
-١١٢-
אא א
WMicroproccessorאא٥ J٥
אאאא
א،E٩ J٥Fא
Kאאאאא
אא
א א
אא א
אא
א א
אא אא
Wאא
אאא א
Kא
אאאא א
Kאא
W אא١ J٥ J٥
א אא
א
.אאאW(١٠ J٥)א
،אא אאאאאא
Wאאאאא
אאאאאWData Busא
אאאאא،אאאKא
K8BitאאאD7 D6D5D4D3D2D1D0،64,32,16,8Bits א
-١١٤-
אא א
אאKא،אאWAddress Busאא
EאאאאFאא א
A15...A2A1A0.אאאא א
Kאאאאאאאא،16א
אאאאאWControl Busא
Kאאאאאאאאא
א
אא
ROM
א
אא
RAM אא
א
א
א
אאאאאאW(١١ J٥)א
-١١٥-
אא א
אא א
1111 0101 0000 1100
D7 – D0א
11010110
אא
0
א
1
1
0
1
0
1
1
אאאאWE١٢ J٥Fא
אאאאאא
אא،EWRFאERDFאאאא،א
Kא
Wאאאאא
א א
ROM RAM אאאא MEMR
RAM אאא MEMW
אאא IOR
אאא IOW
Wאאא٣ J٥ J٥
?Word???אאא
K،אא64,32,16,8Bitsאאא א
Wאאא،Byte ??אא8
-١١٦-
אא א
אאאKאאאא
Kאאאאאאאאא
אאאא
א
א
אא
א
א
א
א
א
א
א
אאא אW א
-١١٧-
אא א
Kאאאאא K١
Kאאאאאא K٢
Kאאאאאא K٣
Wאא٥ J٥ J٥
،אאאא
א א א ،א א א
KE١٤ J٥FאאFאאKאא
7 6 5 4 3 2 1 0
S Z A P C Y C
אא
0 2 4 6 7 אא
CY(Carry) P(Parity) AC(Auxiliary Carry) Z(Zero) S(Sign) א
א א א א א א
Wא٦ J٥ J٥
KAאא1אאאאW א
אאא1אאW א
K0
-١١٨-
אא א
אאא1אאWא
Kאאאאאאאאאא
א02Bא0EאWE٥ J٥F
EA+BF
00001110 א
H 00000010Bא
Z00010000א
KD3אאD4אא אא
Fאאאא1אאW א
KE
Aאא1אאW א
EFFFאא
א 10 B א FF א WE٦ J٥F
W(A)+(B)א
KE5,3،1אאF10אאא
11111111א
H10000000Bא
Z01111111א
אאאאאאאא
K1א
-١١٩-
אא א
אא
WאאאאאאאE١ J٥F
WאאXE٣ J٥F
KEFאאאRAM/ROM
KEFRAM/ROM
אאאאאאאאאאE٤ J٥F
؟אאאאא
WאאאאאאאאאאE٥ J٥F
؟אא؟
WאאאE٦ J٥F
Wאאאאא
Kא JKא J
Kאאא JKא J
Kא JKא J
K JKא J
-١٢٠-
אא א
؟אאאאE٧ J٥F
א
א
א
א
א א
IOR MEMW MEMR
؟אאאאאאאKE٩ J٥F
؟אLאE١٠ J٥F
؟אאאאאE١٢ J٥F
WאאאאאאאאאE١٣ J٥F
אאא
אא
Kא
א
אאאאאאE١٤ J٥F
؟
-١١٨-
אא א
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[1] Nigel P. Cook, Introductory Digital Electronics. New Jersey: Prentice-Hall, Inc. 1998.
[2] M. Morris Mano, Digital Logic and Computer Design, Prentice- Hall, Inc. of India –
2000.
[3] Thomas L. Floyd, Digital Fundamentals, Seventh Edition, Prentice-Hall, Inc. 2000.
[4] M. Morris Mano, Digital Design, Prentice- Hall, Inc. Aug 2001.
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J١ J K K K K K K K K K K K K K K K K K K K K K KNumbers SystemsאאWאא
J٢ J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J٢ J K K K K K K K K K K K K K K K K K K K K K K K Numbers Systemsאא١ J١
J٢ J K K K K K K K K K K K K K K K KDecimal Numbering Systemsאאא٢ J١
J٢ J K K K K K K K K K K K K K K K K Binary Numbering Systemאאא٣ J١
J٢ J K K K K K K K K K K K K Hexadecimal Numbering Systemאאאא٤ J١
J٢ J K K K K K KArithmatic Operations in Binary Systemאאאא٥ J١
J٢ J K K K K K K K K K K K K K K K K K K K K K K K K K K Kאא
J٢ J K K K K K K K K K K K K K K K Simple Logic Circuits אאאאWאא
J٢ J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J٢ J K K K K K K K K K K K K K K K K K K K K K K K K Logic Gatesאאא١ J٢
J٣٣ J K K K K K K K K K K K K K K K K K Rules of Boolean Algebraאאא٢ J٢
J٣٥ J Implementaion of Logic Circuit via Truth Table אא٣ J٢
J٣٦ J Converting Booleen Expression to Truth Table אאא٤ J٢
J٣٨ J K K Simplification of Boolean Expressionאאאאאא٥ J٢
J٣٨ J K K K K K K K K K K K K K K K K K K K K K Kאא
J٤٤ J K K K K K K K K K K K K Combinational Logic Circuits אאאאאWאא
J٤٥ J K K K K K K K K K K K K K K K K K K K K K K K K K K K K Introduction
J٤٥ J K K K K K K K K K K K K K K K K K K K Demorgan's Theorems١ J٣
J٤٧ J K K K K K K K Universal Properties of NAND and NOR Gatesאאאא٢ J٣
J٤٨ J K K K K K K K K K K K K KNOR،NAND אאאאאאא٣ J٣
J٥٣ J K K K K K K K K K K K K K K K K K K K K K K K K Karnaugh Map٤ J٣
J٥٤ J K K K K K K K K KSimplification Using Karnaugh Mapאא٥ J٣
J٦٠ J K K K K K K K K Binary Adder and Subtractor Circuits אאאא٦ J٣
J٦٧ J K K K K K K K K K K K K K K K K K K K K K K K K K K אא
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English
1's Complement אא
st
1 Clock pulse אאא
2's Complement אא
4-stages א
Active High Inputs אאאא
Active Low Inputs אאאא
Active-low אא
Addition of Binary Numbers אאא
Address Bus אא
Adjacent cells אא
Advantages א
Analogue
Arithmetic Operations אא
Array
Asynchronous Binary Up/Down Counters אאאאאאאא
Asynchronous Binary-Down Counters אאאאאאא
Asynchronous Binary-Up Counters אאאאאאא
Asynchronous Counters אאאאא
Auxiliary Carry AC א
Bars אא
Basic Construction of a Computer אאא
Binary Adder and Subtractor Circuits אאאא
Binary bits אא
Binary Coded Decimal אאא
Binary Decoder אא
Binary Digits אא
Binary Numbering System אאא
Binary Point אא
Binary Subtraction אא
Binary Variables אאא
Binary-to-Decimal Conversion אאאאא
Binary-to-Hexadecimal Conversion אאאא
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English
Bi-stable Multi-vibrator אאאאא
Bits א
Block Diagram אא
Boolean Algebra אא
Boolean Expression אא
Borrowed
Buffer Register אא
Bus Types אא
Carry א
Cells
Central Processing Unit CPU אא
Central Processors אא
Clear-input א
Clock Pulse א
Clocked SR Flip-Flop אאSRא
Closed
Combinational Logic Circuit אאאאא
Complementation א
Complements א
Control Bus א
Control Unit CU א
Converting
Core Memory אאאא
Counters אאא
CS: Chip Select א
CY(Carry) א
Cycle Repeats א
Data Acknowledge אא
Data Available אא
Data Bus א
Data subscriber א
Decimal Fractions אא
Decimal Numbering System אאא
Decimal Point אא
Decimal-to-Binary Conversion אאאאא
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אאאאא א
English
Decimal–to–Hexadecimal Conversion אאאא
Delayed time Filp-flop אא
Demorgan's Theorem
De-multiplexers א
Design of Combinational Logic Circuits אאאאא
Developments of Computer אא
Difference bit א
Digital
Digital Electronic Circuits אאאא
Digital Integrated Circuits א
Digital word
Disabled א
Discard
Enabled
Flip Flop א
Flip-Flop Circuit אא
Full Subtractor Circuit אאא
Full-Adder Circuit אאא
Gate א
Half Subtractor Circuit אאא
Half-Adder Circuit אאא
Handshaking אא
Hardware א
Hexadecimal Numbering System אאא
Hexadecimal-to-Binary Conversion אאאא
Hexadecimal–to–Decimal Conversion אאאא
HIGH א،
Implementation ،،
Input and Output Devices אא
Input Interface אא
Input Labels א
Input unit
INTEL א
Invalid condition א
Inversion א
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English
INVERTER א
JK Flip Flop JKא
Karnaugh-Map א
Latches א
Least Significant Bit אא
Left Shift אאא
Logic Circuit א
Logic Functions אאא
Logic Machine
Logic Symbol אא
Logical Addition אא
Logical Multiplication אא
LOW
Magnitude א
Maximum Count of a Counter א
Memory אא
Memory Access Controllers אא
Microprogramming אא
Mode of Operation א
Most Significant Bit אא
Motherboard אא
Multiplexers or Data Selectors אאא
NAND Gate as a Universal Logic Element NANDאא
Negative Edge Trigger אא
No Change EאFא
NOR Gate as a Universal Logic Element NORאא
NOT Gate אא
Number of Binary Combinations אא
Numbering Systems אא
Output interface אא
Output unit א
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Parallel Data א
Parallel Data In א
Parallel Data Out א
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Parallel Transmission אאא
Parallel-in, Serial-out Shift Registers אא–אאא
Positional Weight אא
Positive edge
Positive Edge Trigger אא
Power Supply א
PROM & EPROM אאאא
Propagation-delay time א
Pulses
Random Access Memory RAM אאאא
RD: Read אא
Read Only Memory ROM אאא
Repeated Division-by-2 Method ٢אא
Representation of Signed Numbers אאאא
Reset
Reset Input אא
RESETS א
Right Shift אאא
Ripple Counters אאא
Rotate Left א
Rotate Right א
Rules of Boolean Algebra אאא
S(Sign) א
Sequential Logic Circuits אאאא
Serial Data אאא
Serial-In א
Serial-in, Parallel-out Shift Registers אא–אאא
Serial-in, Serial-out Shift Registers אא–אאא
Serial-Out א
Series Transmission אא
Set Input אא
SETS א
Shift Registers אא
Sign
Signed Numbers אאאא
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English
Sign-Magnitude אאא
Sign-Magnitude System אאא
Simplification
Simplification of Boolean Expressions אאא
Simplification Using Karnaugh Map אא
Single Bit א
SISO Rotate-Right אאא–אא
Software אא
Standard
stores
Sum א
Synchronous Binary Counters אאאאאא
Synchronous Counters אאאאא
Temporary
Timing Diagram אא
Toggle א
Trigger
Truth Table א
Universal Gates א
Universal Properties אאא
Unpredictable א
Vacuum Tube
via
Voltage Source
Whirl Wind Computer א
WR: Write
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Parallel Data Output אאא
Modulus of Counter MOD אא
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