IEEE SPONSORED 2ND INTERNATIONAL CONFERENCE ON ELECTRONICS AND
COMMUNICATION SYSTEM(ICECS 2015)
IMPLEMENTATION OF CIRCUIT IN
DIFFERENT ADIABATIC LOGIC
ARPAN CHAUDHURI MAMIA SAHA
CAPGEMINI RELIANCE JIO INFOCOMM
HYDERABAD LIMITED
INDIA MUMBAI
arpanchaudhuri18@gmail.com INDIA
mamiasaha20@gmail.com
Abstract- Adiabatic circuits are widely employed in Low power
VLSI circuit to achieve power efficient system at the cost of
reduced performance. The power saving of adiabatic circuit
can reach more than 90% compared to conventional static
CMOS logic for extreme low frequency applications. The
power efficiency of 4:1 multiplexer, designed in different
adiabatic logic families is presented in this paper. Power
saving more than 50% is achievable beyond 1000MHz also.
Keywords—Low-power,adiabatic logic,multiplexer, CMOS,
Positive feed back adiabatic logic, Efficient charge recovery
logic,2N2P2N.
I. INTRODUCTION
With the development of VLSI technology power
dissipation is increasing dramatically. Low power has become
one of the crucial design constraint, especially for portable and
battery operated systems. Compared with the conventional low
power approaches, power dissipation can be significantly
reduced by using the adiabatic computation.
The term adiabatic comes from thermodynamics, used to
describe a process in which there is no exchange of heat with
the environment. The adiabatic logic structure dramatically
reduces the power dissipation. The adiabatic switching
technique can achieve very low power dissipation, but at the
expense of circuit complexity. Adiabatic logic offers a way to
reuse the energy stored in the load capacitors rather than the
traditional way of discharging the load capacitors to the ground
and wasting this energy. By properly mixing the ideas derived
for adiabatic and static CMOS circuits one can achieve low
power dissipation in the circuit. Adiabatic logic circuits utilize
AC voltage supplies (power-clocks) to recycle the energy of
circuit nodes. During recovery phase, the energy of the circuit
nodes is recovered to the power source instead of being
dissipated as heat. In the adiabatic circuits, circuit nodes are
charged and discharged by AC voltage supplies, thus their
output signals are clocked AC signals (adiabatic signals).
978-1-4788-7225-8/15/$31.00 ©2015 IEEE
3
MOUMITA BHOWMIK,
4
SAMBHU NATH PRADHAN
5
SUBHRAJIT DAS
5
PUNJAB NATIONAL BANK
ECE DEPARTMENT
NIT AGARTALA
AGARTALA, INDIA
moumitabk23@gmail.com,
sambhu.pradhan@gmail.com
subhrajit54@gmail.com
Since, the AC supplies controls the working of the circuits,
they are also called power clocks.
Over the years different low power adiabatic logic circuits
are proposed [1-4]. Though, CMOS technology provides
circuits with very low static power dissipation, during the
switching operation currents are generated, due to the discharge
of load capacitances that cause a power dissipation which
increases with the clock frequency [5]. The adiabatic technique
prevents such losses. The charge does not flow from the load
capacitance to ground, but it flows back to a trapezoidal or
sinusoidal supply voltage and can be reused [6]. Power losses
due to the resistance of the switches needed for the logic
operation still occur. In order to keep these losses small, the
clock frequency has to be much lower than the technological
limit.
Multimode operations of adiabatic circuits are presented
in [7]. In this paper a simple combinational circuit -4:1
multiplexer is implemented using different configuration of
adiabatic logics and the power saving in different frequency
are compared to see the effeteness of different adiabatic
logic families with respect to low power consumption. The
rest of the paper is organized as follows. Section II starts
with the discussion on working principal and power
dissipation of conventional CMOS and adiabatic circuit.
Section II ends with the description of different adiabatic
logic families. Simulation results of adiabatic multiplexer
(mux) are presented in section III. The paper ends with the
conclusion given in section IV.
II. CONVENTIONAL AND ADIABATIC LOGIC
A. CONVENTIONAL CMOS LOGIC
The conventional switching can be understood by using a
simple CMOS inverter. The CMOS inverter can be
considered to consist of a pull-up and pull-down networks
connected to a load (or internal) capacitance C. The pull-up
and pull-down networks are actually MOS transistors in
series with the same load C. The capacitance in this case
models the fan-out of the output signal.
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Power loss in conventional CMOS transistors mainly occurs
because of device switching and can easily be understood by
studying the CMOS inverter as shown in Fig. 1.
Figure 1. Conventional CMOS Inverter.
A more compact way to model this is with an ideal
switch and a channel resistance R in saturation mode.
Voltage waveforms at the input, capacitor output and
resistor equivalent circuit are shown in Fig 2. The transistors
are in parallel between them and in serial with C. A more
compact way to model this is with an ideal switch and a
channel resistance R when in saturation mode
When the logic level is set to high, there is a sudden flow of
current from the voltage source, through the ideal switch and
lumped resistor to the capacitance C. The sudden change in
voltage level across R accounts for the large amount of
energy lost during CMOS charging.
Figure 2. Voltages at the input, capacitor, and resistor
equivalent circuit.
The energy dissipated in this circuit can be modelled by:
2 Figure 3. A single-phase trapezoidal PC with stages marked.
Eapplied = CVdd (1)
The amount of energy stored in C is found by integrating
the power over time and is given by:
CV 2dd
Estored = (2)
2
That means that half of all supplied energy is stored in the
capacitor (C) and the other half is dissipated in R during the
charge cycle. In regular CMOS circuits, the energy stored in
C is dissipated during the discharge cycle on the falling edge
of the clock.
Since the energy stored in the capacitor does not need to be
minimized, it is necessary to minimize the energy wasted in
the transistor network in order to achieve any energy
savings. If the circuit is driven with a frequency f and period
T, the total power used in the circuit during a cycle
calculated using the above formula yields:
E applied CV 2dd
Papplied = = (3)
ܶ T
Adiabatic switching tries to minimize the energy wasted
during charging by using a constant current source and
charging at a lower frequency f. Both of these optimizations
can be calculated by minimizing the function of energy
dissipation and current, yielding the dissipated energy
formula given by:
CV 2
Edissipated 3ǻ7 ቀ dd ቁ 5ǻ7 (4)
οT
If charging time T is infinitely long, theoretically there will
be no energy dissipated. Infinitely long charging times are
impractical, but by spreading out the charge transfer evenly
during the charging time, the peak current and large initial
power loss are greatly reduced. Adiabatic switching is
achieved by replacing the constant DC voltage supply with a
time-varying LC driver/oscillator in order to get a constant
charging current.
B. ADIABATIC LOGIC
A large part of the dissipated energy is lost due to the
sudden flow of charge on the rising edge of the square wave
clock, as stated earlier. Adiabatic computing methods have
tried to avoid this loss by making the clock as linear as
possible, depending on the design of the logic family.
Because the oscillator acts both as a clock and a power
supply reference, the convention is to call it a Power Clock
(PC). One of the first proposed adiabatic oscillators has a
trapezoidal waveform [8]. This oscillator consists of 4
general stages (Fig. 3): charge, evaluate, discharge, and idle.
The output capacitor is charged in the Charge stage,
evaluated during the Evaluate stage, and discharged
adiabatically back to the PC during the Discharge stage. The
PC is then held at ground (GND) during the idle stage. This
type of PC allows the signal to stabilize better during the
two plateaus (at V dd and GND), but uses a 4-, 6- or even 8-
phase clock, which gets very difficult to control in larger
circuits. Additionally, new circuitry is needed in order to
generate a linear ramp voltage for charging/discharging.
The general representation for Adiabatic Logic circuit
designing is- Where Functional block F denotes the Pull Up
Network and the Inverted functional blockŇġ ťŦůŰŵŦŴġ ŵũŦġ
Pull Down Network. And the Vdc is replaced by Pulse
Vpwr. And the circuit yeilds Vout & ŗŰŶŵį
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 Figure 4. An Adiabatic logic gate

C. STEPS OF ADIABATIC CIRCUIT DESIGN
General rules or steps to be followed for adiabatic
circuit design are as follows:
x Replace each of the PMOS and NMOS devices in
the pull-up and pull-down networks with T-gates.
x Use expanded pull-up network to drive the true
output.
Figure 5. General Schematic (left) and timing of NOT gate
(right) for ECRL
E.POSITIVE FEEDBACK ADIABATIC LOGIC (PFAL)
The structure of PFAL logic is shown in Fig. 6. Two n-
trees realize the logic functions. This logic family also
generates both positive and negative outputs [4,5].

x Use expanded pull-down network to drive the

complementary output.

x The Pull up network is given the input where as the

pull down network is feed will inverted input.

x Both networks in the transformed circuit are used

both to charge and discharge the load capacitance.

x Replace DC V dd by a pulsed power supply (Vpwr)
with varying voltage to allow adiabatic operation.
Today’s adiabatic circuit employs MOSFET in place of T-
gates.
In this work, out of the many adiabatic logic families
following three logic families are chosen.
x Efficient Charge Recovery Logic (ECRL)
x Positive Feedback Adiabatic Logic (PFAL)
x 2N-2N2P
D. EFFICIENT CHARGE RECOVERY LOGIC (ECRL)
Efficient Charge Recovery Logic (ECRL) proposed by
Moon and Jeong , shown in Figure 5, uses cross-coupled
PMOS transistors [2]. It has the structure similar to Cascade
Voltage Switch Logic (CVSL) with differential signaling. .It
consists of two cross-coupled transistors M1 and M2 and
two NMOS transistors.
Fig.5 shows the general schematic for ECRL and the
waveforms of the supply clock as well as I/O signals for a
NOT gate. In order to recover and to reuse the supplied
energy, an ac power supply is used for ECRL gates.
Figure 6. General Schematic for PFAL family
The two major differences with respect to ECRL are that
the latch is made by two pMOSFETs and two nMOSFETs,
rather than by only two pMOSFETs as in ECRL, and that
the functional blocks are in parallel with the transmission
pMOSFETs. In the same way, energy recycling is there.
F.2N-2N2P LOGIC
This adiabatic logic family is derived from ECRL in order
to reduce the coupling effect. Fig.7 shows the general
schematic of ECRL logic [3]. The primary advantage of 2N-
2N2P over ECRL is that the cross-coupled nMOSFETs
switches result in non-floating outputs for large part of the
recovery phase.
This family is a variation of the 2N-2N2P family and
consists of 2 new cross-coupled nMOS transistors added in
parallel to the 2 nMOS transistors. The timing and operation
of this family is identical to the 2N-2N2P p family and the
buffer/inverter is shown in Fig. 7.
A 4:1 multiplexer is designed and simulated to get the
power dissipation result using Conventional CMOS logic,
2N-2N2P logic, ECRL logic and PFAL logic.
Also, we are going to compare the power results obtained
from them in different frequencies to ensure the benefits of

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adiabatic logic designing over conventional CMOS 30ps
designing. A 4:1 Multiplexers has four inputs. A, B, C, D ܸܽ pulse of T=100ps
and two select lines ܵ0 , ܵ1 .The output is Y = (A. ܵഥ0 ܵഥ1 Ĭġ ܸܽ :Square
pulse Rise Time: 30ps, Fall Time:
(B. ܵഥ0 ܵ1 ) + (C. ܵ0 ܵഥ1 ġĩŅįܵ0 ܵ1 ). 30ps
Input
ܸܾ :Square ܸܾ pulse of T=400ps
pulse Rise Time: 30ps, Fall Time:
30ps
Input ܸܿ :Square ܸܿ pulse of T=600ps
pulse Rise Time: 30ps, Fall Time:
30ps
ܸ݀ :Square ܸ݀ pulse of T=500ps
pulse Rise Time: 30ps, Fall Time:
30ps
Selection ܵ0 V pulse of T=900ps
lines Rise Time: 30ps, Fall Time:
30ps
ܵ1 V pulse of T=800ps
Rise Time: 30ps, Fall Time:
30ps
Figure 7. General Schematic for 2N-2N2P logic family

7$%/( ǿǿ ܸ‫ݎݓ݌‬ AT VARIOUS

FREQUENCIES
Frequency Time period Rise Time Fall Time
0.1 MHz 10us 30 ps 30 ps
1 MHz 1us 30 ps 30 ps
10 MHz 100ns 30 ps 30 ps
Figure 8. A simple 4:1 MUX 100 MHz 10ns 30 ps 30 ps
200 MHz 5ns 30 ps 30 ps
300 MHz 3.33ns 30 ps 30 ps
III. SIMULATION RESULT 400 MHz 2.5ns 30 ps 30 ps
500 MHz 2ns 30 ps 30 ps
Adiabatic switching techniques based on energy recovery 600 MHz 1.67ns 30 ps 30 ps
principle are one of the innovative solutions at a circuit and 700 MHz 1.4ns 30 ps 30 ps
logic level to achieve power reduction. In this work we have 800 MHz 1.25ns 30 ps 30 ps
applied adiabatic logic design approach to design 4:1 900 MHz 1.11ns 30 ps 30 ps
multiplexer in CMOS, 2N-2N2P logic, ECRL logic and
PFAL logic.
All the logics are designed and simulated in CADENCE
Virtuso Spectree at 180 nm TSMC technology. The designed schematic for 2N-2N2P, ECRL and PFAL for
The implementation of CMOS Designing & Adiabatic 4:1 MUX are shown in Fig. 9, Fig. 10 and Fig. 11
Logic Designing for 4:1 Multiplexer is done in Cadence respectively. And all the design level parameters are
software with Parameters taking as mentioned in Table I. tabulated in Table I. Power dissipations of CMOS and
different adiabatic logic of 4:1 MUX are noted in Table III.
7$%/(ǿ DESIGN PARAMETERS The same results are plotted in Fig. 12 and 13. Saving of
TYPE CMOS Adiabatic Logics power over convention CMOS is also given in Table II. By
PMOS observing all the values and plotted graph we can practically
800nm 800nm
(WIDTH) conclude that all logic families described as such 2N-2N2P,
NMOS ECRL and PFAL can reduce dynamic power dissipation of
400nm 400nm
(WIDTH) CMOS circuit significantly. Of all the logic circuits,it is
AC pulse voltage at different found that PFAL has the lowest power dissipation. As
1V DC
Vpwr freq expected with the increase in frequency power saving
voltage
Rise Time: 30ps, Fall Time: decreases which is observed from the power results.

356
V. CONCLUSION
This paper reviews the basics of adiabatic computation and
the most well-known adiabatic logic families are described.
Out of several logic families, positive feedback adiabatic
logic (PFAL) gives the better results in terms of power
dissipation. Results upto 1 GHz has been shown and
adiabatic logic may well be applied in lower power
computation within this frequency. However, new adiabatic
design at high frequency may be targeted so that adiabatic
circuit may be used in many high frequency applications
also.

Figure 9. Schematic of 2N-2N2P 4:1 MUX

Figure 10. Schematic of ECRL 4:1 MUX

357
 Figure 11. Schematic of PFAL 4:1 MUX

7$%/(ǿ,, POWER RESULTS OF DIFFERENT LOGIC CIRCUITS

Power (mW) % saving
% saving
of 2N- % saving of
of PFAL
Frequency (MHz) 2N2P ECRL over
CMOS 2N-2N2P ECRL PFAL over
over CMOS
CMOS
CMOS
0.1 128.3 60.02 54.39 64.58 53.22 57.61 49.66
1 94.33 36.50 32.02 39.36 61.31 66.06 58.27
10 81.56 21.09 21.07 22.07 74.14 74.17 72.94
100 71.08 16.28 16.53 15.48 77.10 76.74 78.22
200 68.06 15.07 17.16 16.29 77.86 74.79 76.07
300 67.79 16.92 17.07 17.13 75.04 74.82 74.73
400 69.04 17.19 17.32 16.56 75.10 74.91 76.01
500 69.14 16.99 17.24 18.03 75.43 75.07 73.92
600 70.03 19.34 20.06 18.40 72.38 71.36 73.73
700 70.26 19.97 23.92 18.69 71.58 65.96 73.40
800 70.62 21.93 27.83 19.04 68.95 60.59 73.04
900 70.95 25.09 32.03 19.91 64.64 54.86 71.94
1000 71.51 29.84 35.52 23.43 58.27 50.33 67.24
Average 69.62 67.48 70.71

358
 Graphical Comparison Between CMOS logic 2N- Graphical Comparison Between CMOS logic 2N-
2N2P,ECRL & PFAL logic 2N2P,ECRL & PFAL logic

CMOS 2N-2N2P ECRL PFAL

CMOS 2N-2N2P
140
140
120
120
100

Power (mW)
100
80
Power ( mW)

80
60
60
40
40
20 20

0 0

0.1
1
10
100
200
500
700
800
900
1000
0.1
1
10
100
200
300
400
500
600
700
800
900
1000

Frequency (MHz) Frequency (MHz)

Figure 12. Power plot over frequency. Figure 13. Power plot as bar chart over frequency

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