Digital Systems M Master Degree in Electronic Engineering

1
Introduction
Digital Systems M
Master Degree in Electronic Engineering
Curriculum Electronic technologies for
Big-Data and Internet of Things
A.A. 2019-20
Prof.ssa Elena Gnani

Adapted from J. Rabaey et al, Digital Integrated Circuits2nd, 2003 Prentice Hall/Pearson a.a. 2019-2020
Course Schedule
2
Time Mon. Tue. Wed. Thu. Fri.

12:00-12:30
12:30-13:00 Room 4.1
13:00-13:30 Room 7.7 Room 4.1
13.30-14:00 Room 7.7 Room 4.1
14:00-14:30 Room 7.7 Room 4.1
14.30-15:00 Room 7.7
15:00-15.30 Room 7.7
15:30-16.00 Room 7.7
Course info and Contacts
3
 Course: 90394 - Digital Systems and Introduction to

Computer Architecture
 Module II – Digital Systems – M
 Online material:
https://iol.unibo.it/course/view.php?id=39802
 Exam: Oral examination
 Prof. Elena Gnani

 e-mail: elena.gnani@unibo.it
 telephone: 051 20 93773 (int: 93773)
 Website:
https://www.unibo.it/sitoweb/elena.gnani/en
 Distribution list: elena.gnani.Digital-Systems
 Office hours time slots can be requested by email.
Goal of the Course
4
 Provide a vision of digital circuits at

transistor and gate level so as to have
clear ideas about the main factors
determining circuit performance, power
consumption, signal integrity and digital
throughput.
5
Course Program
 MOS Transistor
 Combinational logic gates
 Sequential logic gates
 Arithmetic building blocks
 Memories and array structures
 Design Methodologies
6
Readings/Bibliography
 J.M. Rabaey, A. Chandrakasan, B. Nikolic: “Digital
Integrated Circuits: a Design Perspective2nd”,
Prentice Hall Int., 2003.
Slides
 Provided by the Teacher (IOL)
 Adapted from J. Rabaey et al, Digital Integrated Circuits, 2003
Prentice Hall/Pearson
Pre-requisites 7
 Analysis and synthesis of combinational and

sequential circuits (Introduction to Computer
Architectures M).
 Basic knowledge on analysis and design of
digital electronic circuits (Elettronica-T1).
Exam
 Final Oral Exam.
8
Electronics Systems Today
Embedded Systems
 Electronics everywhere
 Disappearing computer,
 Ubiquitous computing,
 Pervasive computing,
 Ambient intelligence,
 Post-PC era.
 Basic technologies:
 Embedded Systems
 Communication technologies
Definition
 Embedded computing system: any device that includes a
programmable computer but is not itself a general-
purpose computer.
 Take advantage of application characteristics to optimize
the design
Semiconductor Market by product B€ ES Market in EU
Embedded Systems
 Consumer: cell phones,
digital TV, cameras, …
 Automotive
 Automation
 Smart buildings
 Instrumentation:
measurements, biomedical
 Telecomunications
 ….
The Cyber-Physical Loop
Digital Electronics
Transportation ES
 Automotive electronics
 Avionics
 Trains
Consumer ES
 Mobile
 Phones
 Tablets
 Wearables
 Home
 DTV (4K, OLED)
 Game (PS4)
 Smart white goods
 Smart home – energy
management
Upcoming Applications
Internet of Things (IoT)
 IoT as a term generally refers to a world in which a large range of objects are
addressable via the network
 Objects can include:
 Smart buildings and
home appliances, e.g.
washing machines, TVs,
fridges, cookers, doors,
chairs…
 Civil engineering
structures, e.g. bridges,
railways …
 Wearable devices, e.g.
smart watches, smart
glasses, rings, clothes …
 Medical devices, e.g.
embedded pills
 And possibly every
THING in the world…
The Internet of Things-some popular projections
What is driving the embedded explosion?
Moore’s Law (a statement about economics):
IC transistor count doubles every 18-24 months
Why Scaling?
19
 Transistor count is the most common

measure of integrated circuit complexity.
 Intel's 10-core XeonWestmere-EX  2.5 Billion
 Xilinx currently holds the "world-record" for
an FPGA containing 6.8 Billion transistors.
 More integration due transistor scaling:

 More compact devices
 faster
 Less power hungry
Bell’s Law: A new computer class every decade
“Roughly every decade a new,
lower priced computer class
forms based on a new
programming platform, network,
and interface resulting in new
usage and the establishment of a
new industry.”
- Gordon Bell [1972,2008]
What’s wrong? The end of Moore’s Law
Economy, not technology!
N. Thompson, S. Spanuth
The Decline of Computers As a General Purpose Technology: Why Deep Learning and the
End of Moore’s Law are Fragmenting Computing 2018 Available at SSRN:
https://ssrn.com/abstract=3287769
What’s wrong? Power & Memory Wall
Typical Embedded System Challenges (1-2)
 Small Size, Low Weight
 Handheld electronics
 Transportation applications weight costs money
 Low Power
 Battery power for 8+ hours (laptops often last only 2 hours)
 Limited cooling may limit power even if AC power available
Typical Embedded System Challenges (2-2)
 Harsh environment
 Heat, vibration, shock
 Power fluctuations, RF interference, lightning
 Water, corrosion, physical abuse
 Safety-critical operation
 Must function correctly
 Must not function incorrectly
 Extreme cost sensitivity
 $.05 adds up over 1,000,000 units
Efficiency
 ES must be efficient
– Code-size efficient
(especially for systems on a chip)
– Run-time efficient
– Weight efficient
– Cost efficient
– Energy efficient
26
Targeting Cost Efficiency
27
Cost of Integrated Circuits

 NRE (non-recurrent engineering) costs
 design time and effort, mask generation
 one-time cost factor (design, verification)
 Recurrent costs
 Cost of wafer
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
IC cost = Variable IC cost + NRE/Volume

Variable IC cost = chip cost + packaging cost + test cost
Idealized Cost Curve
Revenue and Profits
Cumulative profit = cumulative revenue – cumulative cost
Impact of Respins
Severely delays time-to-profit
• first-time successful silicon, time-to-market are everything
31
Mask Cost Increases Every Node
Good News: Mask Cost Decreases 32
(NRE)
Good News: Yield Increases 33
(Variable)
34
PCB (Printed Circuit Board)

 electronic components are
mounted on the board and the
traces connect the components
together to form a working circuit
 e.g. STM32 NUCLEO Boards (development
board with STM32 MCU), IoT node, PV
harvesting module, …
 Pros
 Cost Effective
 Heterogeneous Integration
 Cons
 Low Performance
 Area/Weight
 Low Volumes
Systems In Package
35
 SiP (System in Package)(MCM

(Multi Chip Module): integrate
system-level functionality in
package (multichip packaging)
 Pros
 Heterogeneous Integration
 Compactness
 Cons
 More Expensive than PCBs
Integrated Circuits
36
 IC (integrated circuit) : all components (active

and passive) are integrated on a single
semiconductor substrate to form a working
circuit
 Pros
 Extremely Compact
 High-performance
 Low-power
 Cons
 Cost !!!
System On Chip
37
 SoC (System on Chip): integrating an entire

system onto a single die of silicon (IC)
 GP Processors Provide Flexibility VolumesSmall
costs
 Analog IPs / Accelerators specialize the platform for
a given application
 IP (Intellectual Property) Cores: circuit designs that

are licensed for use in a SoC (e.g. MPU core,
UART interface, …)
 Targeting time to market
 Highly Expensive (ARM, synopsys…)
 Potential Good target for embedded systems

 No need to go for super scaled (expensive node)
 Open-Source Hardware Opportunity for New
Applications (IP barrier)
Productivity Trends
Complexity outpaces design productivity
39
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S D
n+ n+
Hardware Description Languages
 Purpose of Hardware Description Languages:
 Capture design in Register Transfer Language form
– i.e. All registers specified
 Use to simulate design so as to verify correctness
 Pass through Synthesis tool to obtain reasonably optimal gate-
level design that meets timing
 Design productivity
– Automatic synthesis
– Capture design as RTL instead of schematic
– Reduces time to create gate level design by an order of magnitude
 Synthesis
 Basically, a Boolean Combinational Logic optimizer that is timing
aware
Digital IC Design Flow 41
HDL (VHDL/Verilog)
Clock frequency, Area, I/O delay…
Synthesis
Design constraints:
Gate-level Netlist
If results don’t match
requirement,
Place & Route Come back and re-try
with a different strategy…
Routed Design
Verification (DRC, LVS,

Timing/Power Analysis)
Chip Tape-Out
Thanks to C. Mucci
Hardware Implementations
 HDLs can be compiled to semi-custom and
programmable hardware implementations
Full Semi- Programmable

Custom Custom
Manual Standard Gate

FPGA PLD
VLSI Cell Array
less work, faster time to market
implementation efficiency
42
43
Targeting Energy Efficiency
Summary of Power Dissipation Sources
P ~ a  C L   Vswing  VDD  f  I DC  I Leak   VDD

 a – switching activity
 CL – load capacitance
 IDC – static current
 Vswing – voltage swing
 Ileak – leakage current
 f – frequency
energy
P  rate  static power
operation
The Traditional Design Philosophy
 Maximum performance is primary goal

 Minimum delay at circuit level
 Architecture implements the required function
with target throughput, latency
 Performance achieved through optimum sizing,
logic mapping, architectural transformations.
 Supplies, thresholds set to achieve maximum
performance, subject to reliability constraints
The New Design Philosophy
 Maximum performance (in terms of
propagation delay) is too power-hungry,
and/or not even practically achievable
 Many (if not most) applications either can
tolerate larger latency, or can live with lower
than maximum clock-speeds
 Excess performance (as offered by
technology) to be used for energy/power
reduction
Trading off speed for power
Exploring the Energy-Delay Space
Energy
Unoptimized
design
Emax Pareto-optimal
designs
Emin
Dmin Dmax Delay
Exploring the Energy-Delay Space
Energy Energy
E3
TN90 TN90
E2 E
TN65 TN65
E1 TN45 TN45
D Delay D1 D2 D3 Delay
In energy-constrained world, design is trade-off process

♦ Minimize energy for a given performance requirement
♦ Maximize performance for given energy budget
Reducing power @ all design levels
 Algorithmic level
 Compiler level
 Architecture level
 Micro-Architecture
 Circuit level
 Silicon level
 Important concepts:
 Lower Vdd and freq. (even if errors occur) /
dynamically adapt Vdd and freq.
 Reduce circuit
 Exploit locality
 Reduce switching activity, glitches, etc.
Algorithmic level
 The best indicator for energy is …..
…. the number of cycles
 Try alternative algorithms with lower complexity

 E.g. quick-sort, O(n log n)  bubble-sort, O (n2)
 … but be aware of the 'constant' : O(n log n)  c*(n log n)
 Heuristic approach
 Go for a good solution, not the best !!
Biggest gains at this level !!
Architecture level
 Going parallel
 Going heterogeneous
 tune your architecture, exploit SFUs (special
function units)
 trade-off between flexibility / programmability /
genericity and efficiency
 Add local memories
 prefer scratchpad i.s.o. cache
 Cluster FUs and register files (see next slide)
Organization (micro-arch.) level
 Enabling Vdd reduction
 Pipelining
– cheap way of parallelism
 Enabling lower freq.  lower Vdd
 Note 1: don't pipeline if you don't need the performance

 Note 2: don't exagerate (like the 31-stage Pentium 4)
 Reduce register traffic

 avoid unnecessary reads and write
 make bypass registers visible
Circuit level
 Clock gating: clock is gated (or stopped) from reaching a set of
flops. It implies the load flops on that clock will not consume power
from the power supply because of clock activity. However,
combinational logic will consume power from the supply. Leakage
current will also be consumed by this block.
 Power gating: gating the power supply to a particular block in the
design (which can be multi-clock domain or single clock consuming
block) which will limit the current from supply and thereby reducing
power consumption by that particular block.
 Multiple Vdd modes
 Reduce glitches: balancing digital path's
 Special SRAM cells
 normal SRAM can not scale below Vdd = 0.7 - 0.8 Volt
 Allow errors and add redundancy to architectural invisible
structures
 .. and many more ..
Silicon level
 Higher Vt (V_threshold)
 Back Biasing control
 see thesis Maurice Meijer (2011)
 SOI (Silicon on Insulator)
 silicon junction is above an electr. insulator
(silicon dioxide)
 lowers parasitic device capacitance
 Better transistors: Finfet

 multi-gate
 reduce leakage (off-state curent)
 .. and many more

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1

Prof.ssa Elena Gnani

Time Mon. Tue. Wed. Thu. Fri.

 Course: 90394 - Digital Systems and Introduction to

 Prof. Elena Gnani

 Provide a vision of digital circuits at

 Analysis and synthesis of combinational and

Electronics Systems Today

 Transistor count is the most common

 More integration due transistor scaling:

Economy, not technology!

Targeting Cost Efficiency

Cost of Integrated Circuits

IC cost = Variable IC cost + NRE/Volume

Mask Cost Increases Every Node

PCB (Printed Circuit Board)

 SiP (System in Package)(MCM

 IC (integrated circuit) : all components (active

 SoC (System on Chip): integrating an entire

 IP (Intellectual Property) Cores: circuit designs that

 Potential Good target for embedded systems

Complexity outpaces design productivity

Verification (DRC, LVS,

Full Semi- Programmable

Manual Standard Gate

Targeting Energy Efficiency

P ~ a  C L   Vswing  VDD  f  I DC  I Leak   VDD

 Maximum performance is primary goal

In energy-constrained world, design is trade-off process

 Try alternative algorithms with lower complexity

Biggest gains at this level !!

 Note 1: don't pipeline if you don't need the performance

 Reduce register traffic

 Better transistors: Finfet

 .. and many more

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