Digital Beamforming Techniques

for Phased Array Systems

PETER DELOS
Technical Lead
Aerospace and Defense Applications Group
Greensboro NC

01/25/2017
1
Topics

►Historical Perspective ►Cascaded Analysis

 Noise Figure
►Phased Array Overview
 Third Order Intercept
 Block Diagram  Phase Noise
 Antenna Pattern
►Receiver Architectures
 Benefits / Challenges
 Heterodyne
 Element Spacing
 Direct Conversion
►Front End Subsystems  Direct Sampling
 T/R Modules
►Calibration
 Analog Beamformers
►References

2
Phased Array Concept

► An array of antenna elements where the relative phase of each element is varied
► Effective
radiation pattern is constructively reinforced in the desired direction (main lobe)
and suppressed in undesired directions (side lobes)
► Allows the radar to
concentrate energy in
one place and maintain
stealth elsewhere.

3
Analog vs Digital Beamforming

Analog Beamforming Digital Beamforming

Centralized Receiver Distributed Receivers

 Analog Beamforming Systems: Legacy, Limited flexibility

 Digital Beamforming Systems: Emerging, Most flexible
 Challenged by SWaP (Size, Weight, and Power)
 Digital processing of all data requires significant power

 Difficult to implement close to the antenna

 Many systems use a mix (Sub-Arrayed Architecture)

4  Analog Sub-arrays with reduced digital channels and digital beamforming
Phased Array Radar System Evolution
Classical
► Analog Beamforming or
Mechanical Scanning
► Centralized Receivers & Exciters
► Low electronics content:
5
Hybrid Solution
► Sub-array Architecture
► Analog/Digital Beamforming
► Distributed Receivers & Exciters
► At Subarray Level
All Digital
► Every Element Digital Beamforming
► No Analog Beamforming
► Distributed Receivers & Exciters
► At a per element level
Generic Digital Beamforming Phased Array Signal Flow

Digital Analog
Digital Up/Down Up/Down T/R Antenna
Beamforming Conversion Converters Conversion Analog Beamforming Modules Elements

NCO
LO
EQ
D/A
Number of Elements
1:
Number of Channels
1 : Number of Beams A/D

EQ
Beam Data

1 : Number of Channels
1 : Number of Elements

EQ

NCO LO

D/A

EQ
A/D

Waveform Generator and Receiver Channels

6
Digitally Beamformed Antenna Patterns

Key Points
Digitally
Beamformed ►Three Beam Patterns to Consider
Pattern  Element Pattern
Antenna Gain

 Subarray Pattern
 Digitally Beamformed Pattern
Subarray
Pattern ►Subarray Pattern Limitations
 Antenna gain for interference outside of
digitally beamformed pattern
 Directional diversity of multiple digitally
Element
Pattern
beamformed patterns

Angle
7
Digital Beamforming : Benefits / Challenges
►Benefits
 Most flexible, programmable
system
 Many simultaneous beam
patterns possible
 Adaptive antenna pattern
programming possible
 Noise improvement from
combining distributed waveform
generator and receivers
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►Challenges
 Synchronization / Calibration of
many waveform generator and
receiver channels
 Power up Synchronization
 Channel to Channel drift
 LO / Clock Distribution
 DC Power Distribution
 SWAP-C associated with the
waveform generator and receiver
designs
 More difficult at higher frequency
operating bands
 Processing large volume of digital
data
Channel Footprint Considerations

► Element Spacing
 Max spacing at λ/2 -> As operating frequency ↑, channel spacing ↓
 Reduced based on scan angles and sidelobe objectives
 Reduced to account for mechanical structure
 Reduced in half for a dual pole system
► Analog Beamforming Impact
 Transmit Receive Module size allocations typically unchanged
 Waveform Generator, Receiver, and Processor Quantity Reduced
 Footprint allocation relaxed
 Performance requirements may become more stressing

► Dilated Array:
 Electronics wider than the Antenna face
 Method to increase volume for system electronics
 Reduces Scalability

9
Basic Radar Transmit & Receive Module (TRM) Diagram

► TRM
► Combines PA, LNA, TR Switch and
potentially Phase / Gain control
► Highly integrated solution Example Front End Integrated Approach

Functional Block Diagram

10
Analog Beamforming Topologies
Generic Analog Beamformer Multi Sub-Arrayed Analog Beamforming Architecture

Analog Beamformer 1
To Analog
From Element 1
Beamformer 1
Element 1
Subarray Beam 1
To Analog
Beamformer M
From
Element N

Reuse Phase Shifter and Attenuator

Analog Beamformer M
From
Element 1
Subarray Beam M To Analog
Element N
Beamformer 1

From
To Analog
Element N
Beamformer M

11
 Phase Shift vs True Time Delay

Beam Squint: Change in Beam Direction vs Frequency

Narrow Band: Phase Shifters Adequate

Wide Band: True Time Delay Used

Figures From:
Cascaded Analysis

13
Receiver Noise

► Much receiver design effort is placed on minimizing noise figure (NF). Noise figure
is a measure of the degradation in signal to noise ratio.

F
S / N In
, standardized at 290K TO 
S / N Out
NF  10 log F
► The impact of a component or subsystem noise figure is that the output noise power
is increased above the level of thermal noise and gain by the noise figure.
Term Gain/NF

Noise Power = -174dBm/Hz + Gain(dB) + NF(dB)

► Cascaded Noise Figure Equation

𝐹2 − 1 𝐹3 − 1 𝐹𝑁 − 1
𝐹𝑇𝑜𝑡𝑎𝑙 = 𝐹1 + + + ⋯+
14 𝐺𝑎𝑖𝑛1 𝐺𝑎𝑖𝑛1 ∗ 𝐺𝑎𝑖𝑛2 𝐺𝑎𝑖𝑛1 ∗ 𝐺𝑎𝑖𝑛2 ∗ ⋯ ∗ 𝐺𝑎𝑖𝑛𝑁−1
Receiver Noise (Continued)

► Receiver Total Noise

 Combination of RF section and A/D
Signal at -1dBFs
 RF section shaped by anti-aliasing filter
 A/D noise typically flat
► Calculation Method Noise Limited Dynamic Range
 Convert to common units = Signal – Noise Power in Channel BW

 Noise added in units of power

► Noise Limited Dynamic Range
 Signal – Noise Power in Channel BW Total Noise
Receiver Noise

A/D Noise( dBm / Hz )  A/D Full Scale ( dBm)  A/D NoiseDensity( dBFs / Hz )
 Receiver Noise ( dBm / Hz ) A/D Noise ( dBm / Hz )
 A/D Sensitivity Loss
Total Noise(dBm / Hz)  10 log10 10 10
 10 10 

 
A/D Sensitivity Loss (dB)  Total Noise( dBm / Hz )  Receiver Noise( dBm / Hz )

A/D Noise

15
Third Order Intercept (TOI)

► Purpose: Industry standard metric to measure linearity in RF amplifiers

Illustration of Two Tone Intermodulation Intercept Point Concept

Two Tone Output Third Order
Two Tone Input With Intermodulation Products Intercept Point

f1 f2 f1 f2 Amplifier

Bd
B/
Compression Curve

Pout

1d
↑
cy
2f1-f2 2f2-f1

en
u
Intermodulation

eq
Fr
Product

ut
↑3dB/dB

p
In
Pin
Calculation Method
Pout Output Third Order Intercept
Cascaded ITOI
dBc 1 1 1 1
dBc OTOI  Pout  = 𝐼𝑇𝑂𝐼 + 𝐼𝑇𝑂𝐼2 + ⋯+ 𝐼𝑇𝑂𝐼𝑁
2 𝐼𝑇𝑂𝐼𝑇𝑜𝑡𝑎𝑙 1
𝐺𝑎𝑖𝑛1 𝐺𝑎𝑖𝑛1 𝐺𝑎𝑖𝑛2 𝐺𝑎𝑖𝑛𝑁−1
Input Third Order Intercept
ITOI  OTOI  Gain
Linear ITOI, not dB, used for this equation
16
Cascaded Analysis, ADISimRF

► Purpose ADISimRF Example

 Cumulative Tracking of Key RF
Parameters
 Signal Power, Cumulative Gain
 NF, Noise Power, TOI, ► Many components included

 Compression Headroom ► Easy to add user defined

blocks
► Most common key metrics
calculated

► Common Methods
 Spreadsheets
 Pros: most user flexibility
 Cons: cut and paste error prone
 RF Simulators
 Industry Calculators
 Example: ADISimRF

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 Phase Noise: Definition

 Measure of Deviation in the zero crossing of a signal

 Consider a Cosine Wave with Phase Fluctuations
f  instantaneous frequency
x(t )  cos2ft   (t ) 
 (t )  randomly fluctuating phase in radians

 Power Spectral Density

 (t ) 2RMS rad 2
S f   with units of
BW Hz

 Phase Noise: specified in dBc/Hz from 10𝑙𝑜𝑔 𝐿 𝑓 Plot Method

S f 
L f  

dBc/Hz
2

– Absolute Phase Noise

 Total Phase Noise at Output
 Sum of Source Oscillators and Device
– Residual Phase Noise Frequency Offset
 Additive Phase Noise of a Device
18  Device Noise independent of source used
Phase Noise Test Setups
Absolute Phase Noise
Cross Correlation Method
Phase Detector Method

Residual Phase Noise

DUTs with No Frequency Translation DUTs with Frequency Translation

19
Figures from Keysight Application Notes
System Phase Noise Considerations
Coherent Combining
– Sum of Noise Voltages Phased Array Block Diagram from LO/Clock Perspective
 𝒗𝑻 = 𝒗𝟐𝟏 + 𝒗𝟐𝟐 + 𝟐𝒄𝒗𝟏 𝒗𝟐
 C = correlation coefficient Master Synthesizers Receivers / WFGs TRMs
 Ranges -1 to +1 Reference
 -1 -> Cancels
LO/Clock Generation D/A
 0 -> Uncorrelated
 1 -> Completely Correlated
Could be: A/D
– Uncorrelated Noise · DDS Based
 Signal Increases 20logN, · PLL Based
 Noise Increase 10logN
· Direct Analog
 -> 10logN Improvement

► Noise Tracked by LO/Clock Generation

– Quantities D/A

• 10logN A/D

– Frequency Scaling
• 20logN
– PLL Loop BWs Objective
20 10logN Combining Improvement of Distributed Waveform Generators and Receivers
Receiver Architectures

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Receiver Architecture Options

Type Configuration Benefits Challenges

LO • Proven/Trusted
Clock
• High Performance
• SWAP
Heterodyne • Optimum Spurious
RX • Many Filters
A/D • High Dynamic Range
• EMI Immunity
Clock • Image Rejection
A/D -IQ Balance
• Maximum A/D BW • In-band IF harmonics
Direct Conversion RX 0 LO • Simplest WB option • LO Radiation
90
• EMI Immunity (IP2)
A/D
• DC and 1/f noise

Clock
• A/D Input BW
• No Mixing
Direct Sampling RX • Gain not distributed across
A/D • Practical at L/S Band
Frequency

22
Receiver Architecture Options (Continued)

Heterodyne with 2nd Nyquist IF Sampling

Downconversion
LO Aliasing
Clock

RX A/D
High Side LO
0 Fs/2 Fs Fc
=Fc+3Fs/4
Direct Conversion / Zero IF
Clock
Downconversion
I
A/D

RX 0 LO
90
Q
A/D LO
-Fs -Fs/2 0 Fs/2 Fs

Direct Sampling with Digital Downconversion

Digital
Down
Clock Conversion Aliasing
I

RX A/D NCO

Q
23
0 NCO Fs/2 Fs
Superheterodyne Solutions

Traditional Dual Up/Down Converter Approach

• ADI components available for entire signal chain

24
• Support will continue
Trends in Direct Conversion Architectures

► Architecture Benefit
 Lowest power: process only the ADC Digital.
desired band at the lowest Decimate
QEC
possible frequency Dc offset JESD204b

 Best out-of-band performance: no AGC

images, NXM mixing products … ADC RSSI
BW tune
 Smallest size: eliminate some
filters and relax others
Synth/
 Lowest system cost VCO
LOgen ClkGen
 Reduces filters:
 Reduce cost and volume and
increase flexibility
Digitally Assisted Analog
► Challenge : Quadrature Error • Digital processing implemented in CMOS
 Digital Assistance implemented in • Correct Analog Errors
CMOS mitigates issue • I/Q matching,
• Digital detection with analog correction
• Zero power correction
• Correction tracks temperature
• Infrequent updates
25 • Better dynamic performance
AD9371: Integrated Dual RF Transceiver with Observation Path

► Integrated Dual Traffic Rx and Tx ► Total Power (@ max

 Tuning Range: 300MHz < Fc < 6GHz bandwidth)
 FDD/TDD Operation  Dual Rx = 2.7W
► Receiver  Dual Tx = 3.7W
 Max Rx BW = 100MHz  FDD = 4.9W
 NF: 14dB @ 3.5GHz, max gain
 IIP3 20dBm @ 3.5GHz, max gain ► Digital Features
 IIP2: 65dBm @ 3.5GHz, max gain  Tx/Rx QEC,
 Gain Range/Step (dB): 30/0.5  DC offset,
► Transmitter  LO leakage
 Max Tx BW = 250MHz  6GSPS JESD204-B
interface
 64dBc ACLR (20MHz LTE)
 OIP3: 27dBm (5dB atten)
 Gain Range/Step (dB): 42/0.05

► Integrated Observation and Sniffer Rx

 Max ORx BW = 250MHz
 2 inputs
 AD9361-like sniffer front end
 Dedicated LO
26  3 inputs
All digital Radar Using RF Transceivers

ADI
SW
Transceivers

Radar Digital
Processor(s)
ADI
SW
Transceivers

ADI
SW
Transceivers

► ADI Transceivers in Radar: ► Utilized Today in a Number of Next Gen Radar

 Integration level supports SWaP needs for digitizing Systems
every element  ADI TRx + TRM (LNA, PA, SW)
 Consistent Interface to Baseband Processor / FPGA
 Complete solution for L & S band
 Combines with ADI RF portfolio for X, Ku, Ka Band systems
 Flexible Frequency Planning
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 High linearity Direct Conversion Architecture
Trends in Direct Sampling & Higher IF Conversion

Digitally Influenced Architectures

► L&S band systems
 Direct RF sampling using GSPS
ADCs / TRx Solutions
 No Discrete Mixing stages
► X, Ku and Higher
 Analog Sub-Array ICs
 Reduced Mixing Stages with
higher integration using GSPS
ADCs / TRx.
► DDCs
 Increase system configurability X & Ku band with no 2nd IF & Utilizing DDC
 Increased Agility
 Dynamic changing from Wideband
FPGA/DSP
to Narrowband system DDC ADC
MXR
LNA

28
Direct Sampling Solution Example
HMC625B HMC8410
RF DVGA LNA
DC-6.0 GHz .01 – 10 GHz
Balun
AD9625
Interface to FPGA (JESD204B Serial Interface)

AD9680
ADC
BPF BPF Preselector

Clock
Dist. Clock
HMC7043 ADF4355

Balun
AD9164
RF DAC
Pout: +36 to +40 dBm
BPF ADL5602 BPF
HMC1114
G=20dB 10 W
DC-4.0GHz 2.7-3.8GHz

L –Band Direct Sampling now Practical,

29 S-Band Direct Sampling Imminent with Emerging Converters
Device & System Calibration / Synchronization Challenges
Synchronizing and maintaining local and remote
Multi-channel system level sync
System Level • Large phased array radar
• Distributed antenna arrays

Channel level, across multiple components

• Equalization
Channel Level • Linearization
• I&Q matching and compensation

• Deterministic latency between the converter and

FPGA/ASIC
Device Level
• Component Level Programmability

► Some applications need a solution that just works to a reasonable degree at power up and is repeatable cycle to cycle.
► Advanced/Extreme synchronization can in some cases be done off-line (although undesirable) but should take less than
a few ms, and at a known interval/instance in time.
► Advanced/Extreme synchronization will likely need to continuously monitor environment conditions to compensate for
temp drift

30
Building the Solution

Support: Products:
System Integrated
MODULES / SYSTEMS Applications & Analog,
Integrated SW, FW & HW ISS Technology Modules, SIPS
Group and iSensors
Sensor Fusion

REFERENCE Support: Products:

DESIGN CFTLs, FMCs,
Systems Prototypes,
SOLUTIONS Applications Tier 1 Example
Group Solutions

ADVANCED
DEVICES Support: Products:
Product and Die, EP
Systems Devices, Class
Applications S Devices,
Groups Integrated
Products

Solutions ranging from components to subsystem

31
References

1. Delos, “RF Circuit Design References”, High Frequency Electronics, 2015

2. Longbrake, “True Time Delay Beamsteering for Radar”, IEEE, 2012
3. McClaning, Vito, “Radio Receiver Design”, New York, Noble Publishing, 2000.
4. O’Donnell, “Radar Systems Engineering” online lecture notes, http://aess.cs.unh.edu/radar%20se.html
5. “Fundamentals of RF and Microwave Noise Figure Measurements”, Keysight Application Note
6. “Phase Noise Characterization of Microwave Oscillators, Phase Detector Method”, Keysight Product Note 11729B-1.
7. “Practical Intercept Measurements and Cascaded Intermod Equations”, Keysight Application Note
8. Razavi, “Design Considerations for Direct-Conversion Receivers”, IEEE, 1997
9. Delos, “Receiver Design Considerations In Digital Beamforming Phased Arrays”, Microwaves and RF, 2014
10. Henderson, “Mixers in Microwave Systems” WJ Tech-Note, 1990.
11. Delos, “Phase Locked Loop Noise Transfer Functions”, High Frequency Electronics, Jan 2016
12. Harris, “What’s up with Digital Downconverters” Part 1 and 2, Analog Dialogue, 2016
13. Kester, “Analog-Digital Conversion”, Analog Devices, 2004
14. Ali, “High Speed Data Converters”, IET, 2016

32
Conclusion

► Digital Beamforming Phased Array Concepts Reviewed

 Architectures
 Main Subsystems
 Benefits / Challenges
 Signal Chains
 Analysis Considerations

► Proliferation of Phased Array Technology Emerging

 Enabled by RF semiconductor technology developments

► Analog Devices looks forward to the future

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