Timing Exception Lab

TIMING EXCEPTION LAB :
 CODE:1
module fp2( index, in0, in1, in2, a, b, out1, out2);
input index;
input [15:0] in0, in1, in2;
input [31:0] a, b;
output [31:0] out1, out2;
reg [1:0] muxReg;
wire [15:0] t0;
wire [31:0] t1;
always @*
begin
muxReg = 2'b0;
muxReg[index] = 1'b1;
end
assign t0 = (muxReg[0] ? in1 : in0);
assign out1 = t0 * in2;
assign t1 = a + b;
assign out2 = (muxReg[1] ? out1 : t1);
endmodule
 Resource Utilization:
STATIC TIMING ANALYSIS FOR VARIOUS PATHS:

 REGISTER TO REGISTER PATH: No timing paths found.
 INPUT TO REGISTER PATH:No timing paths found.
 REGISTER TO OUTPUT PATH:No timing paths found.
 INPUT TO OUTPUT PATH:10.817 ns
 CRITICAL PATH : 10.817 ns (input to output path)
 Set up Analysis :(Max At Slow Process Corner )
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST
2018
| Date : Sat Apr 4 15:36:43 2020
| Host : SauDips running 64-bit major release (build 9200)
| Command : report_timing -from [all_inputs] -to [all_outputs]
| Design : fp2
| Device : 7z020-clg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------
Slack (MET) : 0.183ns (required time - arrival time)
Source: index
(input port)
Destination: out2[11]
Path Group: **default**
Path Type: Max at Slow Process Corner
Requirement: 11.000ns (MaxDelay Path 11.000ns)
Data Path Delay: 10.817ns (logic 7.619ns (70.429%) route 3.199ns
(29.571%))
Logic Levels: 5 (DSP48E1=1 IBUF=1 LUT3=2 OBUF=1)
Output Delay: 0.000ns
Timing Exception: MaxDelay Path 11.000ns
------------------------------------------------------------------------------------------
 Hold Analysis :(Min At Fast Process Corner )
 Implementation :
 RTL Code :2
module mcp_chg( clk, rst, a_in, b_in, out);
input clk, rst;
input [31:0] a_in, b_in;
output [31:0] out;
reg [31:0] a, b, out;
reg [1:0] state;
wire [31:0] out_sum, out_mul;
assign out_sum = (a + b);
assign out_mul = (a * b);
always @(posedge clk)
begin
if (rst)
out = 0;
else
out = (state == 1 ? out_sum : state == 2 ? out_mul : 0);
end
begin
if (rst)
begin
a = a_in; b = a_in;
state = 2'd1;
end
else
begin
if (state == 2'd0)
begin
a = a_in;
b = b_in;
state = state + 1'b1;
end
else if (state == 2'd1)
state = 2'd0;
end
end
endmodule
 Utilization report:

STATIC
TIMING ANALYSIS FOR VARIOUS PATHS:

 REGISTER TO REGISTER PATH: 8.733ns
 INPUT TO REGISTER PATH:2.692 ns
 REGISTER TO OUTPUT PATH:4.037 ns
 INPUT TO OUTPUT PATH: No timing paths found.
 CRITICAL PATH : 8.733 ns (Register to Register path)
 After doing above process concluded that there were many logic levels so modified
the RTL code in such a way that the logic levels are reduced by using restructuring
technique.
 Modified RTL Code:
module mcp_chg( clk, rst, a_in, b_in, out);
input clk, rst;
input [31:0] a_in, b_in;
output [31:0] out;
reg [31:0] a, b, out;
reg [1:0] state;
//reg [31:0] out_sum, out_mul;
//assign out_sum = (a + b);
//assign out_mul = (a * b);
begin
if (rst)
out = 0;
else if(state == 1)
out = a+b;
else
out= a*b;
end

begin
if (rst)
begin
a = a_in;
b = a_in;
state = 2'd1;
end
else
begin
if (state == 2'd0)
begin
a = a_in;
b = b_in;
end
else
state = 2'd0;
end
end
endmodule
 Utilization report:

STATIC
TIMING ANALYSIS FOR VARIOUS PATHS:

 REGISTER TO REGISTER PATH: 8.733ns
 INPUT TO REGISTER PATH:2.645 ns
 REGISTER TO OUTPUT PATH:4.037 ns
 INPUT TO OUTPUT PATH: No timing paths found.
 CRITICAL PATH : 8.733 ns (Register to Register path)
 Set Up Analysis:(Max At Slow Process Corner )

------------------------------------------------------------------------------------
2018
| Date : Sat Apr 4 19:02:41 2020
| Command : report_timing -from [all_registers] -to [all_registers]
| Design : mcp_chg
------------------------------------------------------------------------------------
Source: out0__0/CLK
(rising edge-triggered cell DSP48E1 clocked by clk
{rise@0.000ns fall@4.500ns period=9.000ns})
Destination: out_reg[29]/D
(rising edge-triggered cell FDRE clocked by clk
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 9.000ns (clk rise@9.000ns - clk rise@0.000ns)
(16.887%))
Logic Levels: 7 (CARRY4=4 DSP48E1=1 LUT2=1 LUT4=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.078ns = ( 11.078 - 9.000 )
Source Clock Delay (SCD): 2.406ns
Clock Pessimism Removal (CPR): 0.183ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
------------------------------------------------------------------------------------------------------
-
Slack at Max at Slow Process Corner is 0.131ns . The Require time is 11.270 ns and
Arrival Time is 11.1399 ns.
 Hold Analysis:(Min At Fast Process Corner)
------------------------------------------------------------------------------------
2018
| Date : Sat Apr 4 19:03:04 2020
| Command : report_timing -from [all_registers] -to [all_registers] -hold
| Design : mcp_chg
------------------------------------------------------------------------------------
Slack (MET) : 0.230ns (arrival time - required time)
Source: state_reg[1]/C
Destination: state_reg[0]/D
Path Group: clk
Path Type: Hold (Min at Fast Process Corner)
(48.300%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.982ns
-----------------------------------------------------------------------------------------
Slack at Min at Fast Process Corner 0.230 ns and Require Time is 0.872 and arrival
time is 1.102 ns .
 Implementation :
 Constraints Provided :
The
Implementation failed due to the above constraints.
The
Implementation completed and design is meeting timing.
 Slack After Implementation (Max at Slow Process Corner)

------------------------------------------------------------------------------------
2018
| Date : Sat Apr 4 21:21:54 2020
| Command : report_timing -from [all_registers] -to [all_registers]
| Design : mcp_chg
------------------------------------------------------------------------------------
Source: out0__0/CLK
(rising edge-triggered cell DSP48E1 clocked by clk
Destination: out_reg[29]/D
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
(29.449%))
Logic Levels: 7 (CARRY4=4 DSP48E1=1 LUT2=1 LUT4=1)
Clock Path Skew: -0.065ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.502ns = ( 16.502 - 12.000 )
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
--------------------------------------------------------------------------------------------
 Slack is 1.790 ns of Max at SLow Process Corner after Implementation.
 Slack After Implementation (Min At Fast Process Corner)

-----------------------------------------------------------------------------------
2018
| Date : Sat Apr 4 21:29:08 2020
| Command : report_timing -from [all_registers] -to [all_registers] -hold
| Design : mcp_chg
------------------------------------------------------------------------------------
Slack (MET) : 0.267ns (arrival time - required time)
Source: state_reg[0]/C
Destination: state_reg[1]/D
Path Group: clk
Path Type: Hold (Min at Fast Process Corner)
(47.991%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.024ns
------------------------------------------------------------------------------------------------------------
 Slack during Hold Analysis is 0.267 ns in Min at fats Process corner.
 RTL Code :3
module constant_mux( in1, in2, in3, contl, z, out, IN1, IN2, IN3, CONTL, OUT);
input in1, in2, in3, contl, z;
output out;
input IN1, IN2, IN3, CONTL;
output OUT;
wire t1, t2;
wire T1, T2;
assign t1 = (contl ? in1 : z);
assign t2 = (t1 | in2);
assign out = (contl ? z : t2);
assign T1 = (CONTL ? IN1 : 1'b0);
assign T2 = (T1 | IN2);
assign OUT = (CONTL ? 1'b0 : T2);
endmodule


Timing Exception Lab

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Timing Exception Lab

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TIMING EXCEPTION LAB :

STATIC TIMING ANALYSIS FOR VARIOUS PATHS:

TIMING ANALYSIS FOR VARIOUS PATHS:

always @(posedge clk)

TIMING ANALYSIS FOR VARIOUS PATHS:

 Set Up Analysis:(Max At Slow Process Corner )

Implementation completed and design is meeting timing.

 Slack After Implementation (Max at Slow Process Corner)

 Slack After Implementation (Min At Fast Process Corner)

 Slack during Hold Analysis is 0.267 ns in Min at fats Process corner.

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