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CH 08
CH 08
CH 08
Chapter 8
Jin-Fu Li
Chapter 8 Low-Power VLSI Design
Methodology
• Introduction
• Low-Power Gate-Level Design
• Low-Power Architecture-Level Design
• Algorithmic-Level Power Reduction
• RTL Techniques for Optimizing
Power
• Adiabatic Logic Circuits
Cinput
interconnect
Cdrain Cinput
Vout
VA nMOS C drain + ∑ Cint erconnect + ∑ Cinput
VB network
1 T /2 dVout T dVout
Pavg = [∫ Vout (−Cload )dt + ∫ (VDD − Vout )(Cload )dt ]
T 0 dt T /2 dt
VA VA
Vinternal VB
VB Cinternal Vinternal
Vout
VA VB Cload Vout
∑
i
P i (1 − P i ) C i
A 0.2 α = 0.0384
α = 0.0196
B 0.2 α = 0.0099
C 0.5
D 0.5
A
B
C
D A 0.2 α = 0.0384
B 0.2
α = 0.0099
C 0.5
D 0.5 α = 0.1875
National Central University EE613 VLSI Design 9
Gate-Level Design – Phase Assignment
A
A
B
B
C
C
a b c d a b c d
d a
Switching activity
Switching activity
c b
b c
a d
d a
c
b b
a c
d
A
A
B
B D
C
E D
C
E
C Chain structure
D
B Tree structure
C
D
REG REG
Combinational Logic
R1 R2
REG REG
Combinational Logic
R1 R2
Precomputation
Logic
REG
A<n-2:0>
R2
(n-1)-bit REG
Enable
Comparator R4
Precomputation logic F
REG
B<n-2:0>
R3
D Q D Q D Q D Q
Fail DFT rule
clk checking
T
Add control pin
D Q D Q D Q D Q to solve DFT
violation
problem
clk
f1
clk
+
select
f2
32 16 32
16x16 16x16
fref fref/2
multiplier multiplier
16 R
B R
M 32
U
fref fref/2 X
32 Half Half 32
(A ,B) REG REG
multiplier multiplier
fref
V ref
Ppipeline = 1 .2C ref ( ) f ref = 0 .36 Pref
2
1 .83
National Central University EE613 VLSI Design 19
Architecture-Level Design – Retiming
Retiming is a transformation technique used to change the
locations of delay elements in a circuit without affecting the
input/output characteristics of the circuit.
w2(n)
(2) (2)
REG C1 C2 REG C3
(6ns) (2ns) (4ns)
fref
REG C1 REG C2
C3
(6ns) (2ns)
(4ns)
fref
C2
C1
C1_FREEZE
C2_FREEZE
C2
C1
C1_FREEZE
C2_FREEZE
Cbus
Cbus1
Interface
Bus
Cbus1
stable Mux
A<B Mux
glitchy
glitchy
Mux A<B Mux
stable
128x32
din
32
addr dout
write
noe
q addr[7:0]
8 M 32
pre_addr d addr[7:1] U dout
X
clk noe
write
addr dout
din 32
addr0 128x32
Reads
64K bytes
Data
ARM
Addr
Core
R/W
Addr
28K 4K 32K Range
64K
Decoder
ARM
R/W
Addr
Addr
CS
Data
R/W
Addr
R/W
CS
Data
CS
Data
Core
V 1
E=∫ Cv o dv o = CV 2
0 2
Isource C
1
VC (t ) = I source ⋅ t
C
VC ( t )
I source = C
t
RC
E diss = CV C2 (T )
T
• A number of simple observations can be obtained
− The energy is smaller than the conventional case if the
charging time T is larger than 2RC
− The dissipated energy is proportional to the resistance R
• Can a portion of the energy stored in the capacitance be
reclaimed by reversing the current direction?
− The possibility is unique to the adiabatic operation
VA
X X’
Y’ Y
X’ iC
X CY’ X CY X’
VA
X Y
X’ Y’
A’ B’
Vout
A B
A
VA
A’ Vout’
B
B’
VA
constant R Vout
current VA
low Vout ic C
Cload
VDD
VA
VDD/n
Vout
t
National Central University EE613 VLSI Design 40
Adiabatic Logic Circuits – Adiabatic Logic Gates
VN
Vout
V2
Vout
V1
C
t