ECE 545—Digital System Design with VHDL

Lecture 1

Digital Logic Refresher

Part B – Sequential Logic Building Blocks

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Lecture Roadmap – Sequential Logic

•  Sequential Logic Building Blocks

•  Flip-Flops, Latches
•  Registers, Shift Registers
•  Counters
•  RAM

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Textbook References

•  Sequential Logic Review

•  Stephen Brown and Zvonko Vranesic, Fundamentals of Digital
Logic with VHDL Design, 2nd or 3rd Edition
•  Chapter 7 Flip-flops, Registers, Counters, and a Simple
Processors
(7.3-7.4, 7.8-7.11 only)
•  OR your undergraduate digital logic textbook (chapters on
sequential logic)

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Sequential Logic Building Blocks

some slides modified from:

Brown and Vranesic, “Fundamentals of Digital Logic with VHDL Design, 2nd Edition”
S. Dandamudi, “Fundamentals of Computer Organization and Design”

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Introduction to Sequential Logic

•  Output depends on the current input and the internal

state
•  Past inputs effects the internal state
•  Sequential circuits consist typically of
•  Storage elements (flip-flop, latch, register, RAM, etc.)
•  Combinational logic

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 Introduction (cont’d)
Main components of a typical synchronous sequential circuit
(synchronous = uses a clock to keep circuits in lock step)

INPUT OUTPUT
COMBINATIONAL
LOGIC

PRESENT STATE NEXT STATE

S(t) S(t+1)
STATE-HOLDING
STORAGE
ELEMENTS
(i.e. FLIP-FLOPS)

CLOCK
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State-Holding Memory Elements
•  Latch versus Flip Flop
•  Latches are level-sensitive: whenever clock is high, latch
is transparent
•  Flip-flops are edge-sensitive: data passes through (i.e.
data is sampled) only on a rising (or falling) edge of the
clock
•  Latches cheaper to implement than flip-flops
•  Flip-flops are easier to design with than latches
•  In this course, primarily use D flip-flops

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D Latch vs. D Flip-Flop

D Q D
CLK
CLK

Latch transparent when clock is high

D Q CLK
CLK
Q

“Samples” D on rising edge of clock

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D latch
Graphical symbol Truth table
Clock D Q(t+1)
D Q
0 – Q(t)
Clock 1 0 0
1 1 1

Timing diagram
t1 t2 t3 t4

Clock
D
Q
Time

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D flip-flop
Graphical symbol Truth table
Clk D Q(t+1)
D Q
↑ 0 0
Clock ↑ 1 1
0 – Q(t)
1 – Q(t)
Timing diagram
t1 t2 t3 t4

Clock
D
Q
Time

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D Flip-Flop with Asynchronous Set and Reset

•  Bubble on the symbol means

“active-low”
•  When Set = 0, set Q to 1
Set
•  When Set = 1, do nothing
•  When Reset = 0, set Q to 0
D Q
•  When Reset = 1, do nothing
Q
Reset •  “Set” and “Reset” also known
as “Preset” and “Clear”
respectively
•  In this circuit, Set and Reset are
asynchronous
•  Q changes immediately when
preset or clear are active,
regardless of clock
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 D Flip-Flop with Synchronous Reset
D
Reset
Clear
D Q Q
D

Clock Q Q CLK

Reset

Q
(asynchronous Reset)

Q
(synchronous Reset)

•  Asynchronous active-low Reset: Q immediately clears to 0

•  Synchronous active-low Reset: Q clears to 0 on rising-edge
of clock
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Register
D(3) D Q Q(3)
CLK

D(2) D Q Q(2) 4 4
CLK D Q

D(1) D Q Q(1)
CLK

D(0) D Q Q(0)
CLK

Clock

•  In typical nomenclature, a register is a name for a collection

of flip-flops used to hold a bus
•  All flip-flops of a register share the same clock and control
signals 13
Shift Register

Sin Q3 Q2 Q1 Q0
D Q D Q D Q D Q Q

Clk

(a) Circuit
Clk
SHIFT Sin Q3 Q2 Q1 Q0 = Q
Sin REGISTER Q t0 1 0 0 0 0
t1 0 1 0 0 0
t2 1 0 1 0 0
t3 1 1 0 1 0
t4 1 1 1 0 1
t5 0 1 1 1 0
t6 0 0 1 1 1
t7 0 0 0 1 1

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4-bit Shift Registers: symbols

a) with Enable b) with Enable and Parallel Load

4 Enable 4 4 Enable 4
D Q D Q
Load
Sin Sin

Clock Clock

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Shift Register with Enable: internal structure

Q(3) Q(2) Q(1) Q(0)

Sin
D Q D Q D Q D Q

Clock

Enable

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 Shift Register with Parallel Load: internal structure
Load

D(3)
D(2) D(1) D(0)
Sin

D Q D Q D Q D Q

Clock

Enable

Q(3) Q(2) Q(1) Q(0)

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Synchronous Up Counter

enable
load carry
D0 Q0
D1 Q1
D2 Q2
D3 Q3

clock

•  Enable (synchronous): when high enables the counter, when low

counter holds its value
•  Load (synchronous) : when load = 1, load the desired value into the
counter
•  Output carry: indicates when the counter “rolls over”
•  D3 downto D0, Q3 downto Q0 is how to interpret MSB to LSB
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Random Access Memory (RAM)
•  More efficient than registers for
storing large amounts of data
•  Can read and write to RAM
•  Addressable memory
DIN DOUT
•  RAM dimensions are: n n
•  (number of words) x (bits per
word) ADDR
•  Address is m bits, data is n bits m RAM
•  2m x n-bit RAM WE
•  Example: address is 5 bits,
data is 8 bits CLK
•  32 x 8 RAM
•  Write Enable (WE)
•  When set, writing takes place
at the next rising edge of
the clock
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 Dual-Port RAM
•  Two sets of input ports
{DINA, ADDRA, WEA}
DINA DOUTA
{DINB, ADDRB, WEB} n n
ADDRA
•  Two corresponding outputs m
DOUTA
DOUTB WEA

•  One memory matrix n

DINB RAM DOUTB
n
•  Possible operations: ADDRB
m
•  Read from two memory locations
•  Write to two different memory WEB
locations
•  Read from a memory location CLK
and write to a memory location
(different or the same)

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