2004 IEEE International Conference on Integrated Circuit Design and Technology
Advanced SO1 Substrate Manufacturing
C. Mazur6, G. K. Celler, C. Maleville, and I. Cayrefourcq
Soitec S A
Parc technologique des Fontaines, Bernin - 38926 Crolles Cedex- France
ABSTRACT
300 mm SO1 wafers with sub-1OOnm thick
active Si layers are currently produced in
large quantities and used in advanced
microprocessor circuits. To further enhance
the performance of the next generation of
devices, strained Si layers on insulator are
being developed. The lattice mismatch
between silicon and SiGe alloys, combined
with layer transfer through the Smart Cutm
technology allow forming two types of
strained Si - strained Si on SiGe on
insulator, known as SGOI, and strained Si
directly on insulator, known as sSOI.
Fabrication methods and wafer
characteristics for SOI, SGOI, and SSOI are
discussed here.
INTRODUCTION
Advanced engineered silicon substrates are a
powerful tool in increasing performance of
integrated circuits. Availability of Si-on-
insulator (SOI) wafers has accelerated the
move to high-speed microprocessors and to
circuits with greatly reduced power
consumption.
As demands for transistor performance
increase, enhancing mobility of charge
carriers in silicon has become an important
challenge. By inducing a bi-axial strain in
thin Si films on insulator, significant gains
in transistor speed become available.
In this paper we provide some recent data on
300m SO1 wafers that are mass-produced for
high performance CMOS applications. We
also describe the status of strained Si
technology, specifically strained Si on SiGe
0-7803-8528-4/04/$20.00 02004 IEEE
on insulator (SGOI) and strained Si that is
directly on insulator (sSOI).
SMART CUT TECHNOLOGY FOR
UNIBOND WAFERS
Smart Cut” technology is the dominant
commercial approach to SO1 formation [l-
51. It is based on wafer bonding and ion
implantation induced weakening or splitting.
The sequence of steps to make SO1 wafers,
using hydrogen ions as the implant species, is
as follows [5,6]. After wet cleaning, a “seed”
wafer, from which a layer of Si will be
removed, is oxidized to a desired thickness in
a furnace in order to obtain a very uniform
oxide thickness. This oxide helps to
dechannel hydrogen ions during implantation
and later becomes the buried oxide (BOX) of
the SO1 structure. Typical <200 nm thick
oxide films are grown with a uniformity of
&4% (*30). The next step is hydrogen
implantation through the oxide and into Si
with a dose that is typically about 5 ~ 1 0cm-
’~
’. After implantation, the seed wafer and the
handle wafer are carefully cleaned in order to
eliminate any particle and surface
contaminants and to make both surfaces
hydrophilic. Wafer pairs are aligned and
contacted so that the bonding wave can
propagate across the entire interface. A batch
of bonded wafer pairs is loaded into a furnace
and heated to a suitable temperature, at which
point the wafers split along the hydrogen
implanted zone. The as-split wafer surface
has a mean roughness of a few nanometers.
Surface finishing steps bring the final surface
roughness to values similar to those of
105
standard bulk Si wafers. The seed wafer is
reclaimed so that it can be used again.
There are several important practical aspects
to the method of controlled transfer of a
layer of Si, the thickness of which is defined
by ion implantation energy, to a handle
wafer. This approach makes it possible to
reuse the seed wafer several times, thus
reducing the final cost of the SO1 wafer. It is
the premium seed wafer that defines the
quality of the SO1 film, whereas the handle
wafer only serves as a mechanical support
and can have lower quality. Defining film
thickness by implantation energy leads to a
much better thickness control than is
possible with either mechanical or chemical
thinning. The thickness of the silicon film
andor buried oxide can be adjusted within a
wide range in the Smart Cut'" process by
tuning the implant energy and oxidation
time. Values between 5nm to 1.5pm are
possible for silicon films, and the buried
oxide thickness can be from about 5nm to
5pm. Not all of these values are
commercially available yet, but there is a
strong trend to thinner films, as will be
discussed later in this chapter. These wafers,
known by their trademark name Unibond",
which derives from the fact that only 1 + ~
(~<<1)starting wafers are needed to make
one SO1 wafer, are adaptable to most device
architectures, from ultra-thin CMOS to
thick-film power transistors and sensors. It
is also worth noting that only conventional
equipment is needed for mass production of
200 and 300 mm wafers.
Standard bulk Si wafers are used as the
starting material for both the handle and the
Si film of the final SO1 product. The
characteristics of these two wafer groups are
often different. Crystalline quality of the Si
film that will be transferred to a handle
wafer is of utmost importance. For that
reason, seed wafers must have the minimum
of defects of any kind. Conventional CZ
106
material has COP (crystal originated
particle) defects that are formed by
agglomeration of vacancies during crystal
pulling from the melt. With the steady
shrinkage of device design rules, the
deleterious impact of COP defects has been
increasing. Special techniques have been
developed by the leading Si suppliers to
produce nearly COP-free Si wafers.
Unibondm wafers are typically made by
transferring Si layers from the COP-free Si
seed wafers. An alternative is to transfer
epitaxially grown Si films, since they do not
contain any COPS. The requirements for
handle wafers are less stringent. Wafer
flatness and lack of contamination are
important, but crystalline quality and dopant
concentration are of less significance in
many cases.
LARGE SCALE MANUFACTURING
OF ADVANCED SO1 WAFERS
Below we highlight the current status of
commercial Unibond" wafers produced by
Soitec S A.
300mm SO1 wafer manufacturing
When the bulk silicon industry started
transitioning from 200 to 300 mm wafers,
the SO1 community had to do the same. The
feasibility of making 300mm Unibond"
wafers was demonstrated in 1997, first
samples were built in 2000, and a 300mm
pilot line began operation in January 2002.
The early manufacturing experience
convinced us that there is no major
limitation to producing 300mm Unibond"
wafers [7]. Since 300mm silicon wafers
incorporate the most advanced silicon wafer
engineering, the SO1 quality and
manufacturability has been improved in this
transition to a larger diameter.
Nanotopology improvements are
particularly beneficial [8]. Currently, large
numbers of 300 mm wafers are produced
and shipped to customers.
Ultra-thin wafers
The ITRS 2003 roadmap for SO1 wafers
highlights many challenges, particularly in
the area of the Si film thickness. Device
scaling that is required to continue the
progression along the Moore’s curve has a
strong impact on SO1 wafer parameters. As
we move from 130 to 90 to 65nm device
generations, Si film thickness has to scale as
well. An anticipated transition from partially
depleted (PD) to fully depleted (FD) device
designs that is likely to occur in the next few
years, further accelerates the demand for
thinner Si films. Films <20 nm thick with f
5% (i30) thickness uniformity will be
required in large production volumes by
2006-07 for FD device applications. These
requirements lead to lOA thickness accuracy
across a 300 mm wafer. As a general trend,
it appears that such high uniformity needs to
sites, all wafers, i 3 0
[A]
AFM roughness RMS
2x2 pm
10x10 pm
BOX layer thickness
lli]
BOX layer TTV
In order to implement the Smart CUT
process in production of large diameter
wafers with very thin Si films, many
technical challenges bad to be solved.
In the Unibond” process, the final
uniformity is defined by oxidation,
implantation and polishing steps. In new
process generations, optimization of
oxidation and implantation conditions has
led to very uniform as-split structures,
approaching 1 8, thickness uniformity (lo).
New processes are all based on the same
107
be guaranteed at all spatial wavelengths,
from millimeters down to angstroms. Buried
oxide also needs to scale down in thickness,
although not as rapidly.
Table I lists five progressively thinner SO1
wafer generations produced by Soitec, and
their key specifications. It shows that in
2005 a new wafer technology, with film
thickness as low as 200A and superior
thickness uniformity of *20A, will go into
full-scale production. In 2006, the thickness
uniformity of *lOA will move to high
volume manufacturing. In parallel with
production schedules, development of even
thinner films continues. For example,
feasibility of making films with only 100 8,
of Si on 200 A of oxide has been
established.
highly uniform “as-split” SO1 structures.
Differences in these generations stem from
the steps used to remove surface roughness
and obtain the final SO1 structure.
Examination of ITRS targets indicates that
thinner and more uniform films will be
needed in the future. The desired thinner
films can be achieved by a combination of
reduced ion implant energy and appropriate
film thinnindfinishing techniques.
In addition to film thickness uniformity,
density of defects is a critical parameter for
SO1 wafers. Figure 2 compares defect
density distributions in 200 and 300mm
wafers. Optimization of manufacturing
processes for 300 mm wafers has led to
rapid quality improvement, so that currently
the defect densities in these wafers are equal
or better to those in a more mature 200mm
product.

xpos = 55
vpos = -44
Value = -0.0 A.

- Histogram -
T o t a l N 7525
MinLtmit 362 6 A
MaxLlmil 375 0 A
oo<imo~0 0 %

Fig. 1. Thickness uniformity map of a 300 mm UnibondTMwafer. Mean Si film thickness is

366A, with l o of 1.7A and the total range of 12A. BOX thickness is 1450A.

300mm wafers
I
200mm wafers

0 PCZ Po1 P06 P B P i OtZ Ql4 PI6 PI8 QZ Cl22 0 PQ Po1 0.06 908 91 PI2 Pl4 a16 PI8 PZ 922
LFmmlKny(alq LR8Edly(a%q

108
STRAINED SILICON ON INSULATOR
The strained Si concept moves SO1
technology to an even higher performance
level. Introducing about 0.8% biaxial tensile
strain of the crystalline lattice can double the
mobility of electrons in Si [9]. Hole mobility
is enhanced to a lesser degree unless the
strain is 21%. Most methods of straining the
lattice rely on heteroepitaxial growth of Si
on a SiGe alloy that has the required larger
lattice spacing than that of unstrained Si.

Starting material

Fig. 3. Transfer of a thin film of strained Si together with a relaxed layer of SiGe to a new
handle substrate. The final sSOI wafer is obtained by selective etching of SiGe so that only
sSi remains on top of the oxide. If instead only SiGe is transferred from the “donor” wafer,
and sSi grown over it afterwards, a SGOI stiucture is obtained.

But to get to that point, a good quality layer
of relaxed SiGe with desired Ge content has
to be grown frst. The technology for
obtaining such SiGe layers usually requires
a series of steps, often involving the
epitaxial growth of a thick alloy film with
the Ge composition gradually rising from
0% to the final value of about 20%. By
setting the growth conditions properly,
misfit dislocations that accommodate stress
resulting from the lattice mismatch are
confined within this thick “graded buffer”
layer and do not penetrate into the relaxed
SiGe film of uniform composition that is
formed on top of it. An alternative to the
thick graded buffer is a thin strain-relaxed
buffer, where the relaxation is facilitated by
intentional introduction of nucleation sites
for formation of misfit dislocations. These
nuclei can be formed by very low
temperature epitaxial deposition of Si or
SiGe [IO], by C doping [ll], or by ion
implantation [ 121.
Smart CutTMtechnology makes it possible to
transfer a thin layer of relaxed SiGe from a
substrate on which it was initially grown to a
new handle wafer [13-IS]. Depending on the
exact sequence of layers in the stack being
transferred, we obtain either SGOI or sSOI
structure, as shown in Fig. 3. In the latter
case, the SiGe template layer is removed by
the selective wet etch so that the final
structure consists of strained SOI, i.e. a

109
strained Si layer that is supported by the
oxide below. sSOI wafers are ideally suited
for FD device applications as the film
thickness is of the order of 200A or less. In
Fig 4, Raman spectra are shown for a thin
strain Si film that is still on a donor wafer
(starting material) and after transfer to a
handle wafer (strained SO1 or sSOI). The
key point is that there is no frequency shift
between the two peaks, indicating that the
strain is preserved in the Si film on oxide.
Furnace annealing experiments with 15 min
at any given peak temperature proved that
there is no strain relaxation in sSOI at least
up to 1050°C.
Optimization of epitaxial growth and layer
transfer processes for 200 and 300mm
strained Si on insulator wafers is under way.
Pilot-line production quantities of 300mm
sSOI wafers will be available in 2005.

Resotiant Ramm scattering (Ecxc=3.4eV)

5 U- 1.25 GPa
cd

480 SO0 510 520 530

wavenumber (cm")

Fig. 4. Raman spectra of strained Si before and after layer transfer from a donor wafer to a
handle wafer. Peaks for unstrained bulk Si and for SiGe are also shown.

SUMMARY ACKNOWLEDGMENTS
SO1 wafer technology has reached maturity. Contributions of many colleagues in Soitec
Global wafer production is of the order of R&D and Manufacturing divisions are
IM wafedyear and is increasing rapidly. greatly appreciated. We also would like to
But the demand for thinner and thinner films thank Dr. Vincent Paillard of LPST-UPS in
places new demands on the fabrication Toulouse for performing Raman
methods. At the same time SGOI and sSOI, measurements.
two strained Si on insulator technologies,
are moving into the prototyping phase.

110
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