CHARACTERIZATION OF VTH CURVE

Plot of VT vs Length of MOS

Plot of VT vs Width of MOS

Test bench for plotting VT

CHANNEL sp ANALYSIS
 Channel sp Analysis - Attenuation is 11.9159 dB at 5GHz

SPECIFICATIONS
Specificati
Parameter
on
DC Gain 0 dB
Peaking Frequency 5 GHz
Peaking 12 dB
Peak Gain 12 dB
Technology Used 45 nm
Input Type PRBS
Input Bit Period 0.2 ns
400 mV p-
Differential Input Voltage
p
DC Supply Voltage 1.1 V
DC Bias Voltage 880 mV
Temperature 27 0 C

CALCULATIONS
We are using 2 CTLEs in cascade, each having 6 dB peak, to get the resultant 12 dB peak.
So, Peaking = 6 dB
So, 20log(1+gmRs/2) = 6 => 1+gmRs/2 = 1.9952
Let, gm = 12.26 mS, correspondingly we get Rs = 162 Ω. Theoretically we get Rs = 162 Ω, but
practically this value reduces even further because of the on resistance of the tail MOS. Hence, Rs
must be set higher than calculated value.
We are biasing our MOS at 850 µA.
Finger width kept constant for all MOS at 1 µm, no. of fingers = 1 for all.
Load Resistance = 266 Ω
To lower the Threshold voltage of M1, we are keeping l of M1 = 90 nm.
DC Bias voltage = 880 mV (Given), hence Gate voltage for M1 = 880 mV.
With the designed circuit, due to loading effect for the next stage, practically we do not get 6 dB
gain for each CTLE. Hence, we use Inductor Peaking to achieve the desired gain of 6 dB in each
stage at 5 GHz peak frequency.
Hence, we use and Inductor of 6.5 nH in series with the Load Resistance. The inductor acts as a
short circuit at low frequencies, and increases the load impedance at higher frequency, thus
increasing the gain.
Resultant Circuit:
DC Analysis and DC Bias Margins:

____VT ____VGS ____VDS

AC Analysis:

AC Response of CTLE Block

 AC Response of Channel and CTLE

Transient Response:

Channel Output CTLE Output

Test Bench for Analysis:

RESULTANT EYE DIAGRAM

 Eye for Channel
 Eye for CTLE

MOS AMPLIFIER
SPECIFICATIONS
Parameter Specification
DC Gain 26-30 dB(*)
3dB Frequency 2.5 GHz
Technology Used 45 nm
Input Type PRBS
Input Bit Period 0.2 ns
Differential Input Voltage 150 mV p-p
DC Supply Voltage 1.1 V
DC Bias Voltage 800-860 mV
Temperature 27 0 C

(*)- The DC gain should be as high as possible to attain saturation, the only criteria is that the 3dB frequency
should be nearly 2.5GHz.

Week Assignment:
1. Variation of threshold Voltage (Vth) with Respect to length, Width and Multiplier

The Test bench used here was a Diode connected Mosfet. The variation with respect to the
parameter is as shown below.

FIGURE 1: VTH versus Length

 FIGURE 2: VTH versus Width

FIGURE 3: VTH versus Multiplier(m)

From the above three graph, the marker is shown which shows the used value for length and
width. The length was slightly high to prevent the short channel effect. The length could not
be made much high because we would also require high gm value which is inversely
proportional to length and directly to width. That’s why these specific values are chosen for
the analysis.

2. Design of MOS Amplifier with the common mode voltage being that of the
Drain voltage of the last CTLE stage.
 The Final PRBS output of the CTLE stage is 150mVp-p equalized output. The Final VD
i.e. the common mode voltage of my input stage is within the range of 800 to 860mV.
The circuit have been tried and tested with the two range of common voltage.

FIGURE 4: Characterization of MOSFET

FIGURE 5:TestBench used for the characterization

 The Overall circuitry is what shown below. The output common mode voltage of the
MOS amplifier should be kept above 800mV such that the upper rail is saturated
properly.
 FIGURE 6: SCHEMATIC

 The TESTBENCH used for the analysis of the Amplifier is as shown below.

FIGURE 7: TESTBENCH

As seen from the Testbench three Stages are required to acquire the desire gain and the cut-
off frequency as seen in the Magnitude Curve below. Final Common Mode Voltage is
800.75mV. The drain current through the two matched transistor is 1.5mA, and gm is about
20.2355 mS. The total Load capacitance of the input stage which is same as that of the output
stage is 125fF( Cgs+2Cgd).

 AC ANALYSIS:
 FIGURE 8: Magnitude Curve

 TRANSIENT RESPONSE:

FIGURE 9: Transient response (prbs input signal)

The Transient Response Shown is the response of a input prbs signal of input 150mV p-p ,5GBPS
signal. The output Shown is Outp and Outn individually.