Analog Integr Circ Sig Process (2008) 57:169–178
DOI 10.1007/s10470-008-9167-8
OTA based on CMOS inverters and application in the design
of tunable bandpass filter
H. Barthélemy Æ S. Meillère Æ J. Gaubert Æ
N. Dehaese Æ S. Bourdel
Received: 24 July 2007 / Revised: 24 February 2008 / Accepted: 20 March 2008 / Published online: 22 April 2008
Ó Springer Science+Business Media, LLC 2008
Abstract A new operational transconductance amplifier
(OTA) builds with CMOS inverters only is proposed in this
paper. Simulations with typical BSIM3V3 parameters of a
0.35 lm CMOS process have shown a 3.56 GHz gain-band-
width product under 2.5 V supply voltage. The corresponding
total harmonic distortion is equal to 0.46% for 2 V peak–peak
differential output voltage. At the same supply voltage, the
circuit can provided at each output a voltage swing of 2.25 V
peak–peak. From VDD = 2 V to VDD = 2.5 V the differen-
tial transconductance varies from 72 to 108.4 lX-1. The
corresponding common mode rejection ratio and the total
power consumption are always lower than -31 dBc and
800 lW, respectively. Typical application of a biquad filter is
proposed to illustrate the circuit capabilities.
Keywords Operational
Transconductance
Amplifier

OTA
CMOS
Bandpass filter
1 Introduction
Operational transconductance amplifiers (OTA) are used to
realize numerous continuous time circuits and systems
H. Barthélemy
S. Meillère
J. Gaubert
N. Dehaese

S. Bourdel
Institut Matériaux Microélectronique Nanosciences de Provence
(IM2NP), UMR CNRS 6242, Université Paul Cézanne, Provence
et Sud Toulon-Var, Marseille Cedex, France
H. Barthélemy (&)
Université Sud Toulon Var, Bâtiment R, BP 132, 83957 La
Garde Cedex, France
e-mail: herve.barthelemy@univ-tln.fr
S. Meillère
J. Gaubert
N. Dehaese
S. Bourdel
Polytech’Marseille, IMT Technopôle de Château Gombert,
13460 Marseille Cedex 20, France
[1–8]. They are for example largely used to implement
Gm-C (or OTA-C) filters [1–6] and oscillators [7, 8].
Classically OTA are designed from a differential pair of
two transistors [1]. In this case the OTA differential
transconductance is controlled by modifying the current
sink of its differential pair(s) [2]. In this paper as the
transconductor proposed by Nauta and Seevinck in [9, 10],
the proposed OTA is directly voltage controlled.
Digital cells can be easily designed from CMOS logical
gates and CMOS switches working under two possible
electrical signal states. These two states often correspond to
the electrical values 0 (ground) and VDD, where VDD is the
power supply of all the logical gates. In an opposite way
analog systems are often used to amplify continuous time
signals for which the noise, sensibility, and linearity are
more important than the digital counterpart. Even is they
are basic universal analog functions (operational amplifi-
ers, controlled current or voltage sources), it is relatively
difficult to synthesize automatically analog systems from
basic universal analog cells. The interest of using CMOS
inverters to realize analog operations is that the CMOS
inverter (normally used in digital operation) can be auto-
matically synthesized on silicon from digital tools. The
concept of using CMOS inverters to implement analog
transconductance was presented in [9, 10]. The CMOS
inverter is also currently used as transimpedance amplifier
to detect the current flowing through a diode [11].
In this paper Sect. 2 presents the CMOS inverter working
in transconductance mode of operation. In this case the
CMOS inverter operates at small-signal around a common
mode voltage equal to the half of the supply voltage VDD
(VCM = VDD/2). In this operation the CMOS inverter sim-
ulates a negative transconductor [9]. In Sect. 3, after a brief
overview of the OTA properties in Sect. 3.1, the proposed
topology is first introduced (Sect. 3.2). The traditional rail-
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to-rail OTA based on the classical differential pairs of two
transistors is presented in Sect. 3.3. The Nauta transcon-
ductance [9, 10] properties are discussed in Sect. 3.4.
Simulation results of the proposed topology compared to
the simulated traditional OTA and Nauta configuration are
done in Sect. 3.5. In this section, it is underlined that the
Nauta configuration provides a very high common mode
transconductance and consequently a very poor CMRR.
Low CMRR also leads to a poor power supply rejection
ration (PSRR). Then, the proposed OTA can be viewed as a
design alternative to implement CMOS OTA with CMOS
inverters only. A typical application example using the
proposed OTA is simulated and discussed in Sect. 4. This
example consists in the implementation of a classical
biquad filter [2, 5] based on a Gyrator [12] that simulates a
tunable L-active inductor which is presented in the Sect.
4.1. Biquad filter simulation and comparisons are detailed
in Sect. 4.2. Functioning of the proposed OTA and Nauta
configurations was acted from prototypes assembled with
HEF4069UBPs [13]. Variations obtained from measure-
ment of the central frequency as a function of the supply
voltage VDD of the filter constructed with the proposed
OTA are given in Sect. 4.2. All simulations were per-
formed with the typical process parameters of the accurate
0.35 lm CMOS BSIM3v3 parameters from AMS tech-
nology [14]. Finally, in Sect. 5, we conclude.
2 Overview of the CMOS inverters
in transconductance mode
CMOS inverters are widely used in digital signal pro-
cessing. Figure 1(a) shows the typical CMOS inverter and
Fig. 1(b) its conventional symbol.
In Fig. 1, WN and WP (LN and LP) are the nmos and
pmos channel widths (channel length), respectively. Con-
sidering the difference between the nmos and pmos
mobilities (WN, WP), a traditional inverter reaches an
equilibrium (choosing LN = LP) around WP = (lN/lP)WN
[14]. At this condition, in voltage mode of operation (node
Fig. 1 CMOS inverter. (a) Transistor configuration, (b) universal
symbol, (c) transconductance operation around VDD/2
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Analog Integr Circ Sig Process (2008) 57:169–178
OUT open), the inverter threshold is near VOUT =
VIN = VDD/2. Around this particular operating point, the
nmos and pmos transistors both work in saturate mode of
operation [15, 16].
The inverter transconductance mode of operation is
simulated by forcing an equivalent ‘small signal’ short-cut
between the DC common mode voltage and the node OUT.
Around this common mode voltage (VCM = VDD/2) the
inverter simulates, at small signal amplitude, a transcon-
ductor between the input voltage (VIN) and the output current
(IOUT) of the CMOS inverter (see Fig. 1(c)). Figure 2 shows
the typical DC current characteristic of the CMOS inverter in
transconductance mode of operation (VDD = 2.5 V).
In this transconductance mode of operation, the inverter
small-signal output current (iout) is given, at low frequency,
by iout = (gmvin); were gm = (gmN + gmP) is the inverter
transconductance around the common mode voltage VCM
and vin the inverter small-signal input voltage. gmN and gmP
are respectively the nmos and pmos gate-source transcon-
ductances in saturate mode of operation. From the nmos and
pmos transistors in saturate mode of operation the voltage
dependency [16] of the inverters transcondutance mode is
explained by the following transconductance estimation:
gm  unN ðVDD  2VTN Þu1 þ rnP ðVDD  2jVTP jÞr1 ð1Þ
where gm is the sum of the nmos and pmos transconduc-
tance in saturation mode of operation, i.e. gm = gmN + gmP,
nN and nP are process dependent parameters that depend on
the field oxide depth, the transistors size and mobilities. For
a quadratic behavior of the MOS transistors u and r are
equal to 2 [15]. With short channel MOS transistors, i.e.
channel length lower than about 200 manometers, u and r
are near unity.
Fig. 2 Typical DC current characteristic of the CMOS inverter in
T-mode
Analog Integr Circ Sig Process (2008) 57:169–178 171

Fig. 4 Fully differential OTA. (a) Conventional symbol, (b) equiv-

alent circuit with common mode transconductance

In this bandwidth of operation (DC to fc) the OTA perfor-

Fig. 3 Calculation of the transition frequency (FTINV) mances can be estimated with interest without taking into
account the effect introduced by the parasitic capacitances.
Table 1 CMOS inverters (WP = 3WN = 3 lm, LN = LP = 2 lm) The usually symbol of the OTA is shown in Fig. 4(a). Fig-
Parameters Values Unit ure 4(b) corresponds to its equivalent electrical circuit
including the non-ideal common mode transconductance
Transconductance gm 217 lX-1
effect. In Fig. 4(a), the ideal OTA corresponds to GMD = gm
Output conductance gd 1.35 lX-1
and GCM = 0. The ideal fully differential OTA is no more
Output resistance R0 = 1/gd 740 kX
than a voltage controlled current source (VCCS).
CG 83.5 fF
Differential mode performance of the real OTA can be
CD 2 fF
estimated by introducing the common mode gain effect. In
CM 0.6 fF
case of OTA, this gain is a common-mode transconductance.
FTINV 413 MHz
The common-mode rejection ration (CMRR) is then the
ration between the common mode transconductance (GCM)
Based traditional calculation of the transition frequency and the differential mode transconductance (GMD). Note that
(FT) of the MOS transistors [15, 16], the equivalent for the OTA in Fig. 4(a) GMD = gm. Because a real OTA
inverters transition frequency (FTINV) can be estimated at exhibits an output parasitic impedance, the load system
small signal amplitude from the circuit given in Fig. 3. configuration is generally made with grounded impedance.
Around VDD/2, neglecting the Miller capacitance and Thus the study presented in this paper will focus on the
choosing lN/lP = WN/WP = 3, the inverter transition configuration with equivalent grounded impedance con-
frequency (FTINV) can be approximated by: nected at node OUT+ and node OUT-. In this section and in

 Sect. 4, all equations are given at small-signal amplitude.
3 lN VDD
FTINV ¼  V TN ð2Þ
8p L2N 2
3.2 Proposed OTA
where VTN is the threshold voltage of the nmos transistor.
Table 1 resumes the simulated characteristics of a typical Figure 5 shows the proposed topology derivates from [18].
inverter with WP = 3WN = 3 lm and LN = LP = 2 lm. The proposed OTA presented in this section allows oper-
In Table 1, gd correspond to the output conductance of ations both in voltage or in current mode [17]. Here voltage
the CMOS inverter which is equal to the sum of the output mode consists to connect high impedance loads at the
conductance of the nmos and pmos transistor, i.e. output nodes (ideally node OUT+ and OUT- Open). In
gd = gdN + gdP. this case the output loads are capacitive. In current mode
we assume low loading impedance at the circuit output
(ideally zero loading impedance at node OUT+ and OUT-).
3 Proposed OTA From [18] the proposed topology has been improved by
including a short-cut (resulting to a single node A in Fig. 5)
3.1 OTA symbol and operations between the inverters I3 and I7. This modification permits
to provide better frequency performances than the Nauta
Even if the OTA can implement narrow band amplifiers or configuration and to provide better stability of the DC
filters the circuit himself acts as a large-band amplifier. output common mode voltage VCM. This proposed topol-
Therefore the frequency performance of a non-ideal or real ogy can be viewed as an alternative design of the Nauta
OTA is generally estimated from its -3 dB bandwidth. The transconductor [9, 10] by providing lower common mode
OTA can then be viewed like a low-pass filter with a corner transconductance gain and better linearity. Note that the
frequency (fc) that is also equal to the OTA cut-off frequency. linearity will be evaluated in this paper from the simulated

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Fig. 5 Proposed fully differential OTA
total harmonic distortion (THD). Node A provides at node
OUT+ and OUT- a DC common mode voltage about VDD/
2 and consequently the proposed class AB OTA in Fig. 5
will not necessitate any additional common mode ‘cir-
cuitry’ to control the DC output value [15]. This is also the
case of the Nauta configuration.
Considering the working principle of the proposed OTA
in Fig. 5, the output conductance and the common mode
input voltage are neglected. In Fig. 5, because all inverters
are identical the equivalent resistance RA at node A is equal
to RA = 1/2gm. Consequently the voltage at node A is equal
to (VIN+ + VIN-)/2. At node OUT+, the output current is
the sum of the output currents provided by inverters I4 and
I2, i.e. IOUT+ = -gm(VIN-) + gm(VIN+ + VIN-)/2 = (gm/
2)(VIN+ - VIN-). Now considering the parasitic output
conductance gd, the current-to-voltage transfer function of
the proposed OTA in Fig. 5 is given by:
voutþ gm
IOUTþ ¼ ¼ ðVINþ  VIN Þ  2gd ðVINþ þ VIN Þ
ZMC 2 high in order to reduce the DC bias current flowing
ð3Þ
From the general Eq. 3 it follows that GMD ¼ gm =2 and
GCM ¼ 2gd . Compared to the Nauta configuration, the
theoretical common-mode gain is very low and do not
depend on the value of the loading impedance. The proposed
OTA is able to work both in voltage or current mode of
operation. All simulations of the proposed OTA have been
performed with the CMOS inverter configuration for which
the characteristics are given in Table 1.
3.3 Traditional OTA
Example of traditional wide-swing fully differential OTA is
shown in Fig. 6. Folded cascode equivalent topology can be
implemented from [15]. Transistor MA to ME provides the
DC current sink I0 to the nmos and pmos differential pair of
two transistors (M1–M2 and M3–M4). In Comparison with
the classical OTA using a single pair of two transistors [15],
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Analog Integr Circ Sig Process (2008) 57:169–178
Fig. 6 Transistor configuration of a full-differential wide-swing OTA
here the full-differential configuration, based on a nmos and a
pmos pair, permits, under capacitive loads to operate with
large input and output voltage variations.
To simplify the study, all the PMOS transistors are fixed
identical with a ration WP/LP, idem for the nmos transistors
with the ration WN/LN. We also fixed LN = LP. For clear
comparison with the proposed OTA using CMOS inverters,
the transconductance gm will also corresponds to the sum of
the nmos and pmos transconductances, i.e. gm = gmN + gmP.
In the same way the conductance gd will corresponds to the
sum of the nmos and pmos output conductances, i.e.
gd = gdN + gdP. Then taking into account gm and gd, the
output current at node OUT+ can be approximated to:
gm gd ðVINþ þ VIN Þ
IOUTþ ¼ ðVINþ  VIN Þ þ ð4Þ
2 2 2
From the general Eq. 4 it follows that GMD ¼ gm =2 and
GCM ¼ g2d
In this traditional topology, size of the mos transistors
cannot be set in the same way as the one used to define the
size of the CMOS inverters. In the CMOS inverter, the
length LN and LP (with LN = LP) must be choose relatively
throught the nmos and pmos transistors. A second differ-
ence is that the transistor transconductances are controlled
from an external DC bias current sink [15]. In the case of
topologies based inverters the transconductance will be
controlled by modifying the value of the DC supply voltage
VDD. Unfortunately, the traditional OTA in Fig. 6 need in
most cases, an additional common mode feedback amplifier
(CMFB) to stabilize its DC output voltage. Simulation of
the traditional OTA in Fig. 6 will be performed with WP/
LP = 18 lm/0.35 lm and WN/LN = 6 lm/0.35 lm.
3.4 Nauta transconductor
The equivalent Nauta circuit [9, 10] with grounded loading
impedances (Z) is shown in Fig. 7. This configuration has
been used to implemented very high frequency filters [9,
10]. Unfortunately in differential mode, the Nauta config-
uration in Fig. 7 needs to operate without common mode
Analog Integr Circ Sig Process (2008) 57:169–178
Fig. 7 Nauta configuration [9, 10]
input voltage and relatively high loading impedances Z.
For example, when node OUT+ or OUT- are directly
connected to ground the output current at node OUT+ is
only controlled by the input voltage VIN+; in the same way
IOUT- is controlled by the input voltage VIN- only.
These conditions can be viewed from the calculated gen-
eral expression of the current-to-voltage transfer function of
the Nauta configuration which can be approximated to:
gm gm ðVINþ þ VIN Þ
IOUTþ ¼ ðVINþ  VIN Þ þ
2 1 þ 2gm Z 0 2
and where Z0 = Z/(Z + 3gd).
From the general Eq. 5 it follows that GMD ¼ gm =2 and
GCM ¼ gm =ð1 þ 2gm Z 0 Þ. For capacitive loads and taking
into account the inverters output conductance gd, the
common mode gain GCM is given by:
gm 3gd
GCM ¼ 1 ¼ gm GCM ¼
x!0 2
1þ 2gm ð3g dÞ
Cx
1þj3g
x!1
d where R0 is the equivalent output resistance at OUT+/-
Equation 5a demonstrates that the common mode
transconductance GCM of the Nauta configuration increases
rapidly with frequency. Moreover, both with resistive or
capacitive loads, the common mode transconductance is two
time higher that the differential mode transconductance
GMD. Consequently, the Nauta configuration cannot be
reasonably viewed as a differential transconductance
amplifier. All simulations of the Nauta configuration have
been performed with the CMOS inverter configuration for
which the characteristics are given in Table 1.
3.5 Simulation results and discussion
The three configurations have been simulated with
approximately the same DC bias current thought the tran-
sistors that drives the AC signal. Table 2 resumes the
mains simulated characteristics of the proposed OTA. For
comparison the corresponding simulation of the traditional
OTA and Nauta configuration have been added in Table 2.
173
The traditional OTA exhibits a higher transconductance
because in this case the transistors length has been set to
0.35 lm. The proposed configuration and the traditional
OTA are both compatible to operate in voltage or current
mode. As discussed bellow the Nauta transconductor is not
really suited to operate under low loading impedance. Under
capacitive loads, the Nauta configuration operates with high
bandwidth, but it exhibits a common mode transconductance
twice higher than the differential transconductance. Conse-
quently the Nauta configuration will also amplify any AC
common mode input voltage. The proposed OTA provides a
simulated phase margin /M higher than 77°. This high /M
will insure the circuit AC stability. This also indicated that
the proposed topology is a ‘one stage opamp’ [15, 16].
Under 50 X loading impedance, Table 2 shows that the
proposed circuit exhibits the same differential transconduc-
tance than the Nauta configuration (GMD = 108.4 Xl-1).
This simulation result is obtained in case of VIN+ +
VIN- = 0 where GMD is estimated by GMD = IOUT+/
(VOUT+ - VOUT-). The proposed topology provides lower
CMRR, lower PSRR, better linearity and higher output
swing. In comparison with the Nauta configuration, these
performances are obtained by increasing the power con-
sumption of 100 lA only. Figure 8 shows the DC output
ð5Þ responses of the three configurations, i.e. proposed, tradi-
tional and Nauta configurations. This Fig. 8 shows that the
proposed configuration is able to work with a relatively high
output voltage swing. Figure 9 shows simulated open loop
transfer voltage of the three configurations; here OUT+ and
OUT- node are open. At low frequency the corresponding
theoretical DC open loop gain is given by:
AO ðdBÞ ¼ 20 log10 ðGMD R0 Þ ð6Þ
ð5a; bÞ
nodes. The value of AO for the different configurations,
calculated from (6), is reported in Table 2.
Figure 10 shows the variation of the differential trans-
conductance for each configuration. The simulated value of
the Nauta and the proposed are identical and follows the same
evolution. The Nauta and proposed transconductance swing
from 72 to 108.4 lX-1 between VDD = 2 and VDD = 2.5 V.
Figure 11 shows the simulated power supply rejection
ration (PSRR) of each configuration for Z = 500 fF and
for Z = 2 pF. In comparison with the proposed and tradi-
tional OTA, These last simulations clearly show that the
Nauta configuration exhibits a poor PSRR.
4 Bandpass filter application using active inductor
To illustrate the operation of the proposed circuit, simu-
lation of the traditional biquad filter based on active
inductance is presented in this section.
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174 Analog Integr Circ Sig Process (2008) 57:169–178

Table 2 OTA mains

Parameters Proposed NAUTA Traditional Unit
characteristics in current mode
OTA trans. OTA
(VDD = 2.5 V)
MOS–IDS– DC signal path 40 40 I0 = 40 lA
GMD (Z = 50 X) (1) 108.4 108.4 379 lX-1 (lS)
GCM (Z = 50 X) 3 217 13.8 lX-1 (lS)
1° phase deviation of GMD 239 136 24 MHz
CMRR @100 kHz -31 +3 -25.7 dBc
Differential input capacitance 85.15 48.9 9.65 fF
Output current swing 254 254 170 lA
Maximum output voltage swing 2.27 1.67 2.5 V
Output resistance R0 (2) 338 250 66 kX
Open loop: DC gain A0 31.3 27.8 28 dB
Open loop: (gain) 9 (bandwidth) 3.56 0.94 7.08 GHz
Phase margin /M 77° 92° 27° degree
pffiffiffiffiffiffi
Total input noise (Z = 50 X) 85 84 25.74 nV/ Hz
PSRR @ 1 kHz (Z = 0.5 pF) 37.45 30.3 38.18 dBc
THD% with Z = 20 kX 0.468 6.38 1.63 %
VOUT = 1.25 V ± 0.5 V
Power consumption * @VDIF = 0 800 700 987 lW

Fig. 8 DC voltage characteristic with infinite output load: , Fig. 9 Open loop voltage gain. , proposed OTA; h, NAUTA
proposed OTA; h, NAUTA configuration; e, traditional OTA configuration; e, traditional OTA

the simulated values of the equivalent inductance and its

4.1 Floating L-active inductor configuration
Figure 12(a) shows the classical gyrator topology [12] used
to implement the L-Active inductor [2, 5]. The estimated
parasitic resistances and capacitors introduced by the real
OTA lead, at small-signal amplitude to the classical
equivalent circuit shown in Fig. 12(b). Table 3 provides
parasitic elements in case of C2 = 10 pF.
Based on ideal OTA the theoretical value of LQ is given
by: LQ ¼ C2 =2gm3 gM4 . With C2 = 10 pF and gm = 108 lX-1
(see Table 1), LQ is 428.7 lH. In Comparison with the Nauta
configuration, Table 3 shows that the inductance quality
factor is improved (i.e. lower equivalent resistance in series
with LQ).

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Analog Integr Circ Sig Process (2008) 57:169–178 175

Fig. 12 Gyrator configuration. (a) L-active gyrator topology, (b)

equivalent circuit with parasitic

Table 3 L-Actives simulated parameters for C2 = 10 pF

Parameters Proposed OTA NAUTA Unit

LQ 429 433 lH
C0 89 135 fF
Fig. 10 Transconductance variation versus the supply voltage. , R0 664 459 kX
proposed OTA; h, NAUTA configuration; e, traditional OTA
r 125 186 X
QL = Lx/r @ 1 MHz 21.6 14.6 –

Fig. 11 Power supply rejection ration (PSRR) versus frequency

@VDD = 2.5 V. Proposed OTA: d, Z 2 0.5 pF; , Z 2 2 pF.
Fig. 13 Biquad or L-active bandpass filter
NAUTA configuration: j, Z 2 0.5 pF; h, Z 2 2 pF. Traditional
OTA: u, Z 2 0.5 pF; e, Z 2 2 pF

Now choosing gm1 = gm2 = gm3 = gm4 = gm, we have:

4.2 Bandpass filter application rffiffiffiffiffiffi
C1 2gm
QF ¼ and x0 ¼ pffiffiffiffiffiffiffiffiffiffiffi ð9a; bÞ
C2 C1 C2
The bandpass filter simulated from the L-active inductor
presented in Sect. 4.1 is shown in Fig. 13. Considering where QF is the filter quality factor and f0 = (2px0) the
ideal OTA the voltage transfer VOUT/VIN is given by: central frequency. The corresponding filter transfer gain at
VOUT jgm1 C2 =2gm3 gm4 x x = x0 is theoretically equal to unity.
¼ In this simulation example, the ration C1/C2 has been set
VIN 1 þ 2ggm2 C2
m3 gm4
x  4gCm31 Cg2m4 x2
to 1, i.e. C1 = C2 = C = 10 pF. Figure 14 shows the
jx=QF x0
¼ ð8Þ transfer magnitude VOUT/VIN at small-signal amplitude
1 þ jx=QF x0  x2 =x20 with VDD = 2.5 V.

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176 Analog Integr Circ Sig Process (2008) 57:169–178

Fig. 16 Transient response of the filter based the proposed OTA with
f0 = 10 MHz (VDD = 2.2 V). e, VIN+; u, VOUT+; , VIN+ – VIN-;
Fig. 14 Transfer magnitude VOUT/VIN: , proposed OTA; h, Nauta
d, VOUT+ – VOUT-

proposed filter using the proposed OTA (C1 = 20 pF and

C2 = 200 fF). In this case, the parasitic capacitances lead
to an effective value of C2 about 583 fF that corresponds to
a central frequency f0 equal to 10 MHz. The simulation
was performed with a 10 MHz–600 mVpp input differen-
tial square voltage. Like the Nauta configuration, this
simulation demonstrates the capacity of the proposed
structure to work without additional common mode feed-
back amplifier to stabilize the DC common mode voltage
around VDD/2.
Finally Fig. 17 shows the central frequency versus VDD
of the filter in Fig. 13 measured with a prototype made
with the proposed OTA [18] configured from multiple
HEF4069UBPs [13] and for C1 = C2 = 47 pF.

Fig. 15 Central frequency versus VDD. , proposed OTA; h, Nauta

In the same simulation condition, the center frequency

of the filter versus the DC supply voltage VDD is plotted in
Fig. 15.
The total power consumption, using the proposed OTA,
is equal to 3.99 mW and the Nauta corresponding value
2.39 mW. Figure 15 clearly shows the interesting possi-
bility to control the central frequency from the DC supply
voltage. However modification of the supply voltage will
directly modify the voltage reference. To maintain the
voltage reference at the OTA input, a useful DC bias
supply and AC coupling is proposed in [19]. At
VDD = 2.5 V, The DC common mode output voltage VCM
is equal to VCM = 1.177 V for the Nauta configuration
Fig. 17 Measured center frequency of the biquad bandpass in Fig. 11
based filter and VCM = 1.166 V with the proposed OTA implemented with the proposed OTA in [18] implemented from
based filter. Figure 16 shows the transient response of the HEF4069UBP(s) with C = 47 pF

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Analog Integr Circ Sig Process (2008) 57:169–178 177

5 Conclusion 15. Barker, R. J., Li, H. W., & Boyce, D. E. (1990). CMOS circuit
design, layout, and simulation. IEEE press Serie on Microelec-
tronic Systems, S. K. Tewksbury, series (Ed). New York, 1998.
For the first time, the feasibility of new high performances 16. Geiger, R. L., Allen, P. E., & Strader, N. (1990). VLSI design
operational transconductance amplifier (OTA) using techniques for analog and digital circuits. Mc Grall Hill: New-
CMOS inverters only has been proposed in this paper. This York.
proposed OTA could help analog designer in the design 17. Barthélemy, H. Current mode and voltage mode: Basic consid-
erations. Proceedings of the 46th IEEE Midwest Symposium on
and the synthesis of numerous analog functions. circuit and systems, December 2003, Cairo Egypt.
18. Barthélemy, H., Fillaud, M., Bourdel, S., & Dehaese, N. (2006).
Acknowledgement Thanks are due to the anonymous reviewers for Inverseurs CMOS configure´s en OTA: Application et comparai-
their valuable feedback. son avec la transconductance de NAUTA. Proceeding of the 7th
Colloque sur le traitement analogique de l’information, du signal
et ses applications, Strasbourg.
References 19. Bas, G., & Barthélemy, H. Negative gain transconductance
amplifier circuit. US Patent 2006/0186966 A1, 24 August 2006.
1. Voornal, H., & Veenstra, H. (2000). Tunable high-frequency Gm-
C filters. IEEE Journal of Solid-State Circuits, 35(8), 1097–1108. Hervé Barthélemy has received
2. Liu, H., & Karsilayan, A. I. (2001). A high frequency bandpass the M.Sc. degree in Electrical
continuous-time filter with automatic frequency and Q-factor Engineering in 1992 and the
tuning. IEEE International Symposium on Circuits and Systems, Ph.D. degree in Electronics from
1, 328–331. the University of Paris XI Orsay,
3. Zhang, X., & EI-Masry, E. I. (2007). A novel CMOS OTA based France in 1996. In 2002 he
on body-driven MOSFETs and its applications in OTA-C filters. received the HDR degree from the
IEEE Transaction on Circuits and Systems I: Fundamental University of Provence, Aix-Mar-
Theory and Applications, 54, 1204–1212. seille I, France. From 1996 to 2000
4. Szczepanski, S., Jakusz, J., & Schaumann, R. (1997). A linear he was an Assistant Professor at
fully balanced CMOS OTA for VHF filtering applications. IEEE the Institut Supérieur d’Electro-
Transactions on Circuits and Systems–II: Analog and Digital nique de la Méditerranée (ISEN)
Signal Processing, 44(3), 174–187. in Toulon, France. Since 2000 he
5. Yodprasit, U., & Sirivathanant, K. (2001). VHF current-mode joined the University of Provence
based on intrinsic biquad of the regulated cascode topology. IEEE where is has been a full Professor
International Symposium on Circuits and Systems, 1, 172–175. in 2005. In September 2007, Prof. H. Barthélemy joined the University of
6. Koziel, S., & Szczepanski, S. (2002). Design of highly linear Sud-Toulon-Var in La Garde, France. Since 2005 he has headed the
tunable CMOS OTA for continuous-time filters. IEEE Transac- Integrated Circuits Design Team at the Institut Matériaux Microélectro-
tions on Circuits and Systems-II: Analog and Digital Processing, nique Nanosciences de Provence (IM2NP). The team counts 12
49(2), 110–122. Researchers and 13 Ph.D. students and is involved in research projects with
7. Thanachayanont, A., & Payne, A. (2000). CMOS floating active industry. His research interests are mainly in the design of analog integrated
inductor and its applications to bandpass filter and oscillator designs. circuits. He authored and co-authored multiple publications in international
IEE Proceedings Circuits, Devices and Systems, 147(1), 42–48. journals and conference proceeding.
8. Barranco, B. L., Gotarredona, T. S., Martos, J. R., Ceballos
Caceres, J. F., Gutierrez, J. M. M., & Barranco, A. L. (2004).
A precise 90 degrees quadrature OTA-C oscillator tunable in the
50–130-Mhz range. IEEE Transactions on Circuits and Systems
Part 1:Fundamental Theory and Applications, 51(4), 649–663. Stéphane Meillère has received
9. Nauta, B., & Seevinck, E. (1989). Linear CMOS transconduc- the Engineer degree in Microelec-
tance element for VHF filters. Electronics Letter, 25, 448–450. tronics from the ISEN-Toulon,
10. Nauta, B. (1992). A CMOS transconductance-C filter technique Institut Supérieur d’Electronique et
for very high frequencies. IEEE Journal of Solid-State Circuits, du Numérique, School at Toulon in
27, 142–153. 2000 and the M.Sc. and Ph.D.
11. Kuo, C.-W., Hsiao, C.-C., Yang, S.-C., & Chan, Y.-J. (2001). 2 degrees from the University of
Gbit/s transimpedance amplifier fabricated by 0.35 lm CMOS Provence Aix-Marseille I, France,
technologies. IEE Electronics Letters, 37(19), 1158–1160. in 2000 and 2004, respectively, all
12. Tellegen, B. D. H. (1948). The gyrator, a new electric network in Microelectronics. From 2003 to
element. Philips Research Report, 3, 81–101. 2005, he worked as a Research
13. Philips Semiconductor. (1995). ‘‘The IC04 LOCMOS HE4000B Engineer at the ISEN-Toulon.
Logic Family Specifications HEF, HEC: HEF4069UB, Gates, Since 2005 he joined the University
Hex inverter’’ Product specification file under Integrated Circuits, of Provence as an Assistant Pro-
IC04, Philips Semiconductor. fessor. His research interests are mainly in the design of full custom ASICs.
14. Austria Mikro Syteme International A: Schlob Premstätten He integrated in the same time the Integrated Circuits Design Team at the
A-8141 Unterpremstätten Austria: http://www.ams.co.at. IM2NP Institut. He worked on different research project with industry.

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178 Analog Integr Circ Sig Process (2008) 57:169–178

Sylvain Bourdel received the

Jean Gaubert received the
Ph.D. in Microelectronics of the
M.S. and the Ph.D. degrees in
National Institute of Applied Sci-
Applied Physics from Paul
ence (INSA) of Toulouse in 2000.
Sabatier University, Toulouse,
He was with the LAAS laboratory
France, in 1985, and 1988,
where he was involved on radio-
respectively. From 1989 to 2001
frequency systems modeling and
he was an Assistant Professor at
on spread spectrum techniques.
the Ecole Nationale Supérieure
In 2002 he joined the IM2NP
de l’Electronique et de ses
where he works on CMOS RF and
Applications, Cergy-Pontoise,
UWB systems design. His interests
France, where he was involved
also include system packaging and
with high-speed GaAs and InP
interconnections.
bipolar devices modelling. In
2001, he joined the University
of Provence, Marseille, France,
and the Institut Matériaux Microélectronique Nanosciences de Prov-
ence (IM2NP). His research focuses on the design and integration of
RF/Microwave CMOS integrated-circuits and systems for wireless
communications, including: Low Noise Amplifiers, System-in-Pack-
age integration, wireless power transmission. He has published more
than 40 refereed journal and conference papers.

Nicolas Dehaese received the

M.S. degree from the ISEN
Engineering School, Lille,
France, in 2002 and the Ph.D.
degree in Electronics from the
University of Provence, Aix-
Marseille I, France, in 2005.
Since 2006, he is an Assistant
Professor in the Integrated Cir-
cuits Design Team from the
Institut Matériaux Microélectro-
nique Nanosciences de Provence
(IM2NP), Marseille, France. His
current field of research is in
radio architectures and design of
CMOS RF integrated circuits for wireless transceivers.

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