LIN System Basis Chip With DC Motor Pre-Driver: Advance Information

Freescale Semiconductor Document Number: MC33911
Advance Information Rev. 4.0, 2/2008
LIN System Basis Chip with DC

Motor Pre-driver 33911
The 33911 is a Serial Peripheral Interface (SPI)-controlled System
Basis Chip (SBC) combining many frequently used functions in an
MCU-based system, plus a Local Interconnect Network (LIN) SYSTEM BASIS CHIP WITH LIN
transceiver. The 33911 has a 5.0V - 60mA low dropout regulator with 2ND GENERATION
full protection and reporting features. The device provides full SPI-
readable diagnostics and a selectable timing watchdog for detecting
errant operation. The LIN Protocol Specification 2.0 compliant LIN
transceiver, has waveshaping circuitry that can be disabled for higher
data rates.
One 60mA high side switch and two 160mA low side switches with
output protection are available for driving resistive and inductive loads.
All outputs can be pulse-width modulated (PWM). Two high-voltage
inputs are available for use in contact monitoring, or as external wake-
up inputs. These inputs can be used as high-voltage analog Inputs.
The voltage on theses pins is divided by a selectable ratio and
available via an analog multiplexer. AC SUFFIX (Pb-FREE)
98ASH70029A
The 33911 has three main operating modes: Normal (all functions 32-PIN LQFP
available), Sleep (VDD off, wake-up via LIN, wake-up inputs (L1,L2),
cyclic sense, and forced wake-up), and Stop (VDD on with limited
current capability, wake-up via CS, LIN bus, wake-up inputs, cyclic
sense, forced wake-up, and external reset).
ORDERING INFORMATION
The 33911 is compatible with LIN Protocol Specification 2.0.
Temperature
Device Package
Features Range (TA)
• One 60mA high side switch and two 160mA low side switches MC33911BAC/R2 - 40°C to 125°C
• Two high-voltage analog/logic inputs 32-LQFP
MC34911BAC/R2 - 40°C to 85°C
• Full-duplex SPI Interface at frequencies up to 4MHz
• LIN transceiver capable of up to 100kbps with wave shaping
• Configurable window watchdog
• 5.0V low drop regulator with fault detection and low-voltage reset (LVR) circuitry
• Pb-free packaging designated by suffix code AC
VBAT 33911
VS1 VSENSE
VS2 HS1
L1
L2
VDD
PWMIN
ADOUT0 LS1
M
MCU MOSI LS2
MISO
SCLK
CS WDCONF
RXD
TXD LIN INTERFACE
AGND
PGND
LGND
LIN
IRQ
RST
Figure 1. 33911 Simplified Application Diagram
* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ VS2 VS1 VDD
INTERRUPT
INTERNAL BUS
CONTROL AGND
MODULE
LVI, HVI, HTI, OCI VOLTAGE REGULATOR
RESET CONTROL
MODULE
LVR, HVR, HTR, WD
LS1
LOW SIDE
WINDOW CONTROL
MODULE LS2
WATCHDOG
MODULE PGND
PWMIN
VS2
HIGH SIDE
MISO CONTROL HS1
MODULE
MOSI
SPI
&
SCLK CONTROL
ANALOG MULTIPLEXER
VBAT
VSENSE
SENSE MODULE
CS
CHIP TEMPERATURE
ADOUT0 SENSE MODULE
ANALOG INPUT L1
WAKE-UP MODULE MODULE
RXD DIGITAL INPUT MODULE L2

LIN PHYSICAL
TXD LAYER
LIN
LGND WDCONF
Figure 2. 33911 Simplified Internal Block Diagram
33911
Analog Integrated Circuit Device Data

2 Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
VSENSE
AGND
VDD
HS1
VS1
VS2
NC*
NC
32
31
29
27
26
30
28
25
RXD 1 24 NC*
TXD 2 23 L1
MISO 3 22 L2
MOSI 4 21 NC*
SCLK 5 20 NC*
CS 6 * Special Configuration Recommended / 19 LS1

Mandatory for Marked NC Pins
ADOUT0 7 18 PGND
PWMIN 8 17 LS2
10
11
12
13
14
15
16
9
LIN
LGND
NC*
NC*
NC*
IRQ
RST
WDCONF
Figure 3. 33911 Pin Connections
Table 1. 33911 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin Pin Name Formal Name Definition
This pin is the receiver output of the LIN interface which reports the state of
1 RXD Receiver Output
the bus voltage to the MCU interface.
This pin is the transmitter input of the LIN interface which controls the state of
2 TXD Transmitter Input
the bus output.
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the
3 MISO SPI Output high-impedance state.
4 MOSI SPI Input SPI (Serial Peripheral Interface) data input.
5 SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input.
6 CS SPI Chip Select SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
7 ADOUT0 Analog Output Pin 0 Analog Multiplexer Output.
8 PWMIN PWM Input High side and low side pulse-width modulation input.
Bidirectional reset I/O pin - driven low when any internal reset source is
9 RST Internal Reset I/O
asserted. RST is active low.
Internal Interrupt Interrupt output pin, indicating wake-up events from Stop Mode or events from
10 IRQ Normal and Normal Request Modes. IRQ is active low.
Output
33911

Freescale Semiconductor 3
PIN CONNECTIONS
Table 1. 33911 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin Pin Name Formal Name Definition
Watchdog This input pin is for configuration of the watchdog period and
12 WDCONF
Configuration Pin allows the disabling of the watchdog.
13 LIN LIN Bus This pin represents the single-wire bus transmitter and receiver.
This pin is the device LIN ground connection. It is internally connected to the
14 LGND LIN Ground Pin
PGND pin.
17 LS2
Low Side Outputs Relay drivers low side outputs.
19 LS1
This pin is the device low side ground connection. It is internally connected to
18 PGND Power Ground Pin
the LGND pin.
22 L2 These pins are the wake-up capable digital inputs(1). In addition, all LX inputs
Wake-Up Inputs
23 L1 can be sensed analog via the analog multiplexer.
25 HS1 High Side Output High side switch output.
26 VS2 These pins are device battery level power supply pins. VS2 is supplying the
Power Supply Pin
27 VS1 HS1 driver while VS1 supplies the remaining blocks.(2)
29 VSENSE Voltage Sense Pin Battery voltage sense input. (3)
Voltage Regulator
31 VDD +5.0V main voltage regulator output pin. (4)
Output
32 AGND Analog Ground Pin This pin is the device analog ground connection.
Notes
1. When used as a digital input, a series 33kΩ resistor must be used to protect against automotive transients.
2. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
3. This pin can be connected directly to the battery line for voltage measurements. The pin is self-protected against reverse battery
connections. It is strongly recommended to connect a 10kΩ resistor in series with this pin for protection purposes.
4. External capacitor (2µF < C < 100µF; 0.1Ω < ESR < 10Ω) required.
33911

ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2 V

Normal Operation (DC) VSUP(SS) -0.3 to 27
Transient Conditions (load dump) VSUP(PK) -0.3 to 40
Supply Voltage at VDD VDD -0.3 to 5.5 V

(5)
Input / Output Pins Voltage V
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD VIN -0.3 to VDD +0.3
Interrupt Pin (IRQ)(6)

VIN(IRQ) -0.3 to 11
HS1 Pin Voltage (DC) VHS1 - 0.3 to VSUP +0.3 V
LS1 and LS2 Pin Voltage (DC) VLS -0.3 to 45 V
L1 and L2 Pin Voltage V
Normal Operation with a series 33kΩ resistor (DC) VLxDC -18 to 40
Transient input voltage with external component (according to ISO7637-2) VLxTR ±100
(See Figure 5, page 16)
VSENSE Pin Voltage (DC) VVSENSE -27 to 40 V

LIN Pin Voltage V
Normal Operation (DC) VBUSDC -18 to 40
Transient input voltage with external component (according to ISO7637-2) VBUSTR -150 to 100
(See Figure 4, page 16)
VDD output current IVDD Internally Limited A

ESD Voltage V
VESD1-1 ± 8000
Human Body Model - LIN Pin(7)
VESD1-2 ±2000
Human Body Model - all other Pins(7)
VESD2 ± 200
Machine Model(8)
Charge Device Model(9)
VESD3-1 ± 750
Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)
VESD3-2 ± 500
All other Pins (Pins 2-7, 10-15, 18-23, 26-31)
NC Pin Voltage (NC pins 11, 15, 16, 20, 21, 24, 28 and 30)(10) VNC Note 10
Notes
5. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
6. Extended voltage range for programming purpose only.
7. Testing is performed in accordance with the Human Body Model (CZAP = 100pF, RZAP = 1500Ω),
8. Testing is performed in accordance with the Machine Model (CZAP = 200pF, RZAP = 0Ω),
9. Testing is performed in accordance with the Charge Device Model, Robotic (CZAP = 4.0pF).
10. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application shown on page 41.
33911

MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings Symbol Value Unit
THERMAL RATINGS
Operating Ambient Temperature(11) TA °C

33911 -40 to 125
34911 -40 to 85
Operating Junction Temperature TJ -40 to 150 °C
Storage Temperature TSTG -55 to 150 °C
Thermal Resistance, Junction to Ambient RθJA °C/W
Natural Convection, Single Layer board (1s)(12), (13) 85
Natural Convection, Four Layer board (2s2p)(12), (14) 56
(15)
Thermal Resistance, Junction to Case RθJC 23 °C/W
Peak Package Reflow Temperature During Reflow(16), (17) TPPRT Note 17 °C
Notes
11. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.
12. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
13. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
14. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
15. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
16. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
17. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33911

STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics

Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33911 and -40°C ≤ TA ≤ 85°C for the
34911, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY VOLTAGE RANGE (VS1, VS2)
Nominal Operating Voltage VSUP 5.5 – 18 V
Functional Operating Voltage(18) VSUPOP – – 27 V

Load Dump VSUPLD – – 40 V
SUPPLY CURRENT RANGE (VSUP = 13.5V)

Normal Mode (IOUT at VDD = 10mA), LIN Recessive State(19) IRUN – 4.5 10 mA
(19), (20), (21)
Stop Mode, VDD ON with IOUT = 100µA, LIN Recessive State ISTOP µA
5.5V < VSUP < 12V – 48 80
VSUP = 13.5V – 58 90
Sleep Mode, VDD OFF, LIN Recessive State(19), (21) ISLEEP µA

5.5V < VSUP < 12V – 27 35
12V ≤ VSUP < 13.5V – 37 48
Cyclic Sense Supply Current Adder(22) ICYCLIC – 10 – µA

SUPPLY UNDER/OVER VOLTAGE DETECTIONS
Power-On Reset (BATFAIL)(23) V

(22) VBATFAIL 1.5 3.0 3.9
Threshold (measured on VS1)
VBATFAIL_HYS – 0.9 –
Hysteresis (measured on VS1)(22)
VSUP Under-voltage Detection (VSUV Flag) (Normal and Normal Request

Modes, Interrupt Generated) V
Threshold (measured on VS1) VSUV 5.55 6.0 6.6
Hysteresis (measured on VS1) VSUV_HYS – 1.0 –
VSUP Over-voltage Detection (VSOV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
Threshold (measured on VS1) VSOV 18 19.25 20.5
VSOV_HYS
Hysteresis (measured on VS1) – 1.0 –
Notes
18. Device is fully functional. All features are operating.
19. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, cyclic sense disabled.
20. Total IDD current (including loads) below 100µA.
21. Stop and Sleep Modes current will increase if VSUP exceeds 13.5V.
22. This parameter is guaranteed by process monitoring but not production tested.
23. The flag is set during power-up sequence. To clear the flag, a SPI read must be performed.
33911

Table 3. Static Electrical Characteristics (continued)

(24)
VOLTAGE REGULATOR (VDD)
Normal Mode Output Voltage VDDRUN V
1.0mA < IVDD < 50mA; 5.5V < VSUP < 27V 4.75 5.00 5.25
Normal Mode Output Current Limitation IVDDRUN 60 110 200 mA

Dropout Voltage(25) VDDDROP V
IVDD = 50mA – 0.1 0.25
Stop Mode Output Voltage VDDSTOP V

IVDD < 5 mA 4.75 5.0 5.25
Stop Mode Output Current Limitation IVDDSTOP 6.0 12 36 mA

Line Regulation mV
Normal Mode, 5.5V < VSUP < 18V; IVDD = 10mA LRRUN – 20 25
Stop Mode, 5.5V < VSUP < 18V; IVDD = 1.0mA LRSTOP – 5.0 25
Load Regulation mV
Normal Mode, 1.0mA < IVDD < 50mA LDRUN – 15 80
Stop Mode, 0.1mA < IVDD < 5mA LDSTOP – 10 50
Over-temperature Prewarning (Junction)(26) TPRE °C

Interrupt generated, Bit VDDOT Set 110 125 140
Over-temperature Prewarning hysteresis(26) TPRE_HYS – 10 – °C
Over-temperature Shutdown Temperature (Junction)(26) TSD 155 170 185 °C
(26)
Over-temperature Shutdown hysteresis TSD_HYS – 10 – °C
Notes
24. Specification with external capacitor 2µF < C < 100µF and 100mΩ ≤ ESR ≤ 10Ω.
25. Measured when voltage has dropped 250mV below its nominal Value (5V).
33911


RST INPUT/OUTPUT PIN (RST)
VDD Low-Voltage Reset Threshold VRSTTH 4.3 4.5 4.7 V
Low-state Output Voltage VOL V
IOUT = 1.5mA; 3.5V ≤ VSUP ≤ 27V 0.0 – 0.9
High-state Output Current (0 < VOUT < 3.5V) IOH -150 -250 -350 µA
Pull-down Current Limitation (internally limited) IPD_MAX mA
VOUT = VDD 1.5 – 8.0
Low-state Input Voltage VIL -0.3 – 0.3 x VDD V
High-state Input Voltage VIH 0.7 x VDD – VDD +0.3 V
MISO SPI OUTPUT PIN (MISO)

IOUT = 1.5mA 0.0 – 1.0
High-state Output Voltage VOH V

IOUT = -250µA VDD -0.9 – VDD
Tri-state Leakage Current ITRIMISO µA

0V ≤ VMISO ≤ VDD -10 – 10
SPI INPUT PINS (MOSI, SCLK, CS)

MOSI, SCLK Input Current IIN µA
0V ≤ VIN ≤ VDD -10 – 10
CS Pull-up Current IPUCS µA

0V < VIN < 3.5V 10 20 30
INTERRUPT OUTPUT PIN (IRQ)

IOUT = 1.5mA 0.0 – 0.8

Leakage Current VOH mA

VDD ≤ VOUT ≤ 10V – – 2.0
PULSE WIDTH MODULATION INPUT PIN (PWMIN)

Pull-up current IPUPWMIN µA
0V < VIN < 3.5V 10 20 30
33911


HIGH SIDE OUTPUT HS1 PIN (HS1)
Output Drain-to-Source On resistance RDS(ON) Ω
TJ = 25°C, ILOAD = 50mA; VSUP > 9.0V – – 7.0
TJ = 150°C, ILOAD = 50mA; VSUP > 9.0V(27) – – 10
– – 14
TJ = 150°C, ILOAD = 30mA; 5.5V < VSUP < 9.0V(27)
Output Current Limitation(28) ILIMHS1 mA

0V < VOUT < VSUP - 2.0V 60 120 250
(29)
Open Load Current Detection IOLHS1 – 5.0 7.5 mA
Leakage Current ILEAK µA
-0.2V < VHS1 < VS2 + 0.2V – – 10
Short-circuit Detection Threshold(30) VTHSC V

5.5V < VSUP < 27V VSUP -2 – –
Over-temperature Shutdown(31), (36) THSSD 150 165 180 °C

Over-temperature Shutdown Hysteresis(36) THSSD_HYS – 10 – °C
LOW SIDE OUTPUTS LS1 AND LS2 PINS (LS1, LS2)
Output Drain-to-Source On resistance RDS(ON) Ω

TJ = 25°C, ILOAD = 150mA, VSUP > 9.0V – – 2.5
TJ = 125°C, ILOAD = 150mA, VSUP > 9.0V – – 4.5
TJ = 125°C, ILOAD = 120mA, 5.5V < VSUP < 9.0V – – 10
Output Current Limitation (32) ILIMLSX mA

2.0V < VOUT < VSUP 160 275 350
Open Load Current Detection(33) IOLLSX – 8.0 12 mA

Leakage Current ILEAK µA
-0.2V < VOUT < VS1 – – 10
Active Output Energy Clamp VCLAMP V

IOUT = 150mA VSUP +2 – VSUP +5
Short-circuit Detection Threshold(34) VTHSC V

5.5V < VSUP < 27V 2.0 – –
Over-temperature Shutdown(35), (36) TLSSD 150 165 180 °C

(36)
Over-temperature Shutdown Hysteresis TLSSD_HYS – 10 – °C
Notes
27. This parameter is production tested up to TA = 125°C and guaranteed by process monitoring up to TJ = 150°C.
28. When over-current occurs, the High Side stays ON with limited current capability and the HS1CL flag is set in the HSSR.
29. When open Load occurs, the flag (HS1OP) is set in the HSSR.
30. When short-circuit occurs and if the HVSE flag is enabled, HS1 automatically shut down.
31. When over-temperature Shutdown occurs, the High Side is turned off. All flags in HSSR are set.
32. When over-current occurs, the corresponding Low Side stays ON with limited current capability and the LSxCL flag is set in the LSSR.
33. When open load occurs, the flag (LSxOP) is set in the LSSR.
34. When short-circuit occurs and if the HVSE flag is enabled, both LS automatically shut down.
35. When over-temperature shutdown occurs, both Low Sides are turned off. All flags in LSSR are set.
36. Guaranteed by characterization but not production tested
33911


L1 AND L2 INPUT PINS (L1, L2)
Low Detection Threshold VTHL V
5.5V < VSUP < 27V 2.0 2.5 3.0
High Detection Threshold VTHH V

5.5V < VSUP < 27V 3.0 3.5 4.0
Hysteresis VHYS V
5.5V < VSUP < 27V 0.5 1.0 1.5
Input Current(37) IIN µA

-0.2V < VIN < VS1 -10 – 10
Analog Input Impedance(38) RLxIN 800 1550 – kΩ

Analog Input Divider Ratio (RATIOLx = VLx / VADOUT0) RATIOLx
LXDS (Lx Divider Select) = 0 0.95 1.0 1.05
LXDS (Lx Divider Select) = 1 3.42 3.6 3.78
Analog Output offset Ratio VRATIOLx- mV
LXDS (Lx Divider Select) = 0 OFFSET -80 0.0 80
LXDS (Lx Divider Select) = 1 -22 0.0 22
Analog Inputs Matching LxMATCHING %
LXDS (Lx Divider Select) = 0 96 100 104
LXDS (Lx Divider Select) = 1 96 100 104
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
External Resistor Range REXT 20 – 200 kΩ

Watchdog Period Accuracy with External Resistor (Excluding Resistor WDACC -15 – 15 %
Accuracy)(39)
ANALOG MULTIPLEXER
Internal Chip Temperature Sense Gain STTOV – 10.5 – mV/K
VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0) RATIOVSENSE
5.5V < VSUP < 27V 5.0 5.25 5.5
VSENSE Output Related Offset OFFSETVSENSE -30 – 30 mV

-40°C < TA < -20°C -45 – 45
ANALOG OUTPUT (ADOUT0)
Maximum Output Voltage VOUT_MAX V

-5mA < IO < 5mA VDD -0.35 – VDD
Minimum Output Voltage VOUT_MIN V

-5mA < IO < 5mA 0.0 – 0.35
Notes
37. Analog Multiplexer input disconnected from Lx input pin.
38. Analog Multiplexer input connected to Lx input pin.
39. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)
33911


RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)
IOUT = 1.5mA 0.0 – 0.8

TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)

Pin Pull-up Current, 0V < VIN < 3.5V IPUIN 10 20 30 µA
LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(40)

Output Current Limitation IBUSLIM mA
Dominant State, VBUS = 18V 40 120 200
Leakage Output Current to GND

Dominant State; VBUS = 0V; VBAT = 12V IBUS_PAS_DOM -1.0 – – mA
Recessive State; 8V < VBAT < 18V; 8V < VBUS < 18V; VBUS ≥ VBAT IBUS_PAS_REC – – 20 µA
GND Disconnected; GNDDEVICE = VSUP; VBAT = 12V; 0V < VBUS < 18V IBUS_NO_GND -1.0 – 1.0 mA
IBUS – – 100 µA
VBAT Disconnected; VSUP_DEVICE = GND; 0V < VBUS < 18V
Receiver Input Voltages VSUP

Receiver Dominant State VBUSDOM – – 0.4
Receiver Recessive State VBUSREC 0.6 – –
Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VBUS_CNT 0.475 0.5 0.525
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) VHYS – – 0.175
LIN Transceiver Output Voltage V
Recessive State, TXD HIGH, IOUT = 1.0 µA VLIN_REC VSUP-1 – –
Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS = 0 VLIN_DOM_0 – 1.1 1.4
Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS = 1 VLIN_DOM_1 – 1.7 2
LIN Pull-up Resistor to VSUP RSLAVE 20 30 60 kΩ
Over-temperature Shutdown(41) TLINSD 150 165 180 °C
Over-temperature Shutdown Hysteresis TLINSD_HYS – 10 – °C
Notes
40. Parameters guaranteed for 7.0V ≤ VSUP ≤ 18V.
41. When over-temperature shutdown occurs, the LIN bus goes into a recessive state and the flag LINOT in the LINSR is set.
33911

DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics

34911, otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions,
unless otherwise noted.
SPI INTERFACE TIMING (see Figure 13, page 19)
SPI Operating Frequency f SPIOP – – 4.0 MHz

SCLK Clock Period tPSCLK 250 – N/A ns
SCLK Clock High Time(42) tWSCLKH 110 – N/A ns
SCLK Clock Low Time(42) tWSCLKL 110 – N/A ns
Falling Edge of CS to Rising Edge of SCLK(42) tLEAD 100 – N/A ns
Falling Edge of SCLK to CS Rising Edge(42) tLAG 100 – N/A ns
MOSI to Falling Edge of SCLK(42) tSISU 40 – N/A ns
Falling Edge of SCLK to MOSI(42) tSIH 40 – N/A ns
MISO Rise Time(42) tRSO ns
CL = 220pF – 40 –
MISO Fall Time(42) tFSO ns

CL = 220pF – 40 –
Time from Falling or Rising Edges of CS to:(42) ns

- MISO Low-impedance tSOEN 0.0 – 50
- MISO High -impedance tSODIS 0.0 – 50
Time from Rising Edge of SCLK to MISO Data Valid(42) tVALID ns
0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100pF 0.0 – 75
RST OUTPUT PIN
Reset Low-Level Duration after VDD High (see Figure 12, page 19) t RST 0.65 1.0 1.35 ms
Reset Deglitch Filter Time t RSTDF 350 600 900 ns
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period (43) t PWD ms

External Resistor REXT = 20kΩ (1%) 8.5 10 11.5
External Resistor REXT = 200kΩ (1%) 79 94 108
Without External Resistor REXT (WDCONF pin open) 110 150 205
Notes
43. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)
33911

Table 4. Dynamic Electrical Characteristics (continued)

L1 AND L2 INPUTS
Wake-Up Filter Time t WUF 8.0 20 38 µs
STATE MACHINE TIMING

Delay Between CS LOW-to-HIGH Transition (at the End of a SPI Stop t STOP µs
Command) and Stop Mode Activation(44) – – 5.0
Normal Request Mode Timeout (see Figure 12, page 19) t NR TOUT 110 150 205 ms
Delay Between SPI Command and HS /LS Turn On(45) t S-ON µs
9V < VSUP < 27V – – 10
Delay Between SPI Command and HS /LS Turn Off(45) t S-OFF µs

9V < VSUP < 27V – – 10
Delay Between Normal Request and Normal Mode After a Watchdog Trigger t SNR2N µs
Command (Normal Request Mode)(44)
– – 10
Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and: µs
Normal Request Mode, VDD ON and RST HIGH t WUCS 9.0 15 80
First Accepted SPI Command t WUSPI 90 — N/A
Minimum Time Between Rising and Falling Edge on the CS t 2CS 4.0 — — µs
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC(46), (47)
Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50µs D1

7.0V ≤ VSUP ≤ 18V 0.396 — —
Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50µs D2

7.6V ≤ VSUP ≤ 18V — — 0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC(46), (48)
Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96µs D3 µs

7.0V ≤ VSUP ≤ 18V 0.417 — —
Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96µs D4 µs

7.6V ≤ VSUP ≤ 18V — — 0.590
Notes
45. Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to an external load.
46. Bus load RBUS and CBUS 1.0nF / 1.0kΩ, 6.8nF / 660Ω, 10nF / 500Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold
defined at each parameter. See Figure 6, page 17.
47. See Figure 7, page 17.
48. See Figure 8, page 17.
33911

Table 4. Dynamic Electrical Characteristics (continued)

LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode) SRFAST — 20 — V / µs
(49)
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS
Propagation Delay and Symmetry(50) µs
Propagation Delay Receiver, tREC_PD = max (tREC_PDR, tREC_PDF) t REC_PD — 3.0 6.0
Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR t REC_SYM - 2.0 — 2.0
Bus Wake-up Deglitcher (Sleep and Stop Modes)(51) t PROPWL 42 70 95 µs

Bus Wake-up Event Reported µs
(52) t WAKE — — 1500
From Sleep Mode
From Stop Mode(53) t WAKE 9.0 13 17
TXD Permanent Dominant State Delay t TXDDOM 0.65 1.0 1.35 s

PULSE WIDTH MODULATION INPUT PIN (PWMIN)
PWMIN pin(54) fPWMIN kHz

Max. frequency to drive HS and LS output pins 10
Notes
49. VSUP from 7.0V to 18V, bus load RBUS and CBUS 1.0nF / 1.0kΩ, 6.8nF / 660Ω, 10nF / 500Ω. Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 6, page 17.
50. See Figure 9, page 18
51. See Figure 10, page 18 for Sleep and Figure 11, page 18 for Stop Mode.
52. The measurement is done with 1µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when VDD reaches 3.0V.
See Figure 10, page 18. The delay depends of the load and capacitor on VDD.
53. In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,
page 18.
33911

TIMING DIAGRAMS
TIMING DIAGRAMS
33911
1.0nF TRANSIENT PULSE

GENERATOR
LIN (NOTE)
GND
PGND LGND AGND
Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.

Figure 4. Test Circuit for Transient Test Pulses (LIN)
33911
1.0nF TRANSIENT PULSE

GENERATOR
L1, L2 (NOTE)
10kΩ
GND
PGND LGND AGND
NOTE: Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 5. Test Circuit for Transient Test Pulses (Lx)

VSUP
R0
TXD LIN
RXD R0 AND C0 COMBINATIONS:

• 1.0KΩ and 1.0nF
C0 • 660Ω and 6.8nF
• 500Ω and 10nF
Figure 6. Test Circuit for LIN Timing Measurements
33911

TIMING DIAGRAMS
TXD
tBIT tBIT
tBUS_DOM (MAX) tBUS_REC (MIN)

VLIN_REC
tREC - MAX tDOM - MIN
tDOM - MIN 74.4% VSUP
58.1% VSUP 60.0% VSUP 58.1% VSUP

LIN 40.0% VSUP 40.0% VSUP
28.4% VSUP 28.4% VSUP

42.2% VSUP
tDOM - MAX tREC - MIN tBUS_DOM (MIN)

tBUS_REC (MAX)
RXD
tRDOM tRREC
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD
tBIT tBIT
tBUS_DOM (MAX) tBUS_REC (MIN)

VLIN_REC
tREC - MAX tDOM - MIN
tDOM - MIN 77.8% VSUP
61.6% VSUP 60.0% VSUP 61.6% VSUP

LIN
40.0% VSUP 40.0% VSUP
25.1% VSUP 25.1% VSUP

38.9% VSUP
tDOM - MAX tREC - MIN tBUS_DOM (MIN)

tBUS_REC (MAX)
RXD
tRDOM tRREC
Figure 8. LIN Timing Measurements for Slow Slew Rate
33911

TIMING DIAGRAMS
VLIN_REC
VBUSrec
VSUP
LIN BUS SIGNAL
VBUSdom
RXD
tRX_PDF tRX_PDR
Figure 9. LIN Receiver Timing
VLIN_REC
LIN
0.4 VSUP
DOMINANT LEVEL
VDD
tPROPWL tWAKE
Figure 10. LIN Wake-Up Sleep Mode Timing
VLIN_REC
Vrec
LIN
0.4VSUP
0.4 VSUP
Dominant Level
Dominant level
IRQ
t PROPWL
TpropWL
t WAKE
Twake
Figure 11. LIN Wake-Up Stop Mode Timing
33911

TIMING DIAGRAMS
VSUP
VDD
RST
tNRTOUT
tRST
Figure 12. Power On Reset and Normal Request timeout Timing
tPSCLK
CS
tLEAD tWSCLKH
tLAG
SCLK
tWSCLKL
tSISU tSIH
MOSI UNDEFINED D0 DON’T CARE D7 DON’T CARE
tVALID
tSODIS
tSOEN
MISO
D0 DON’T CARE D7
Figure 13. SPI Timing Characteristics
33911

FUNCTIONAL DESCRIPTION
INTRODUCTION
INTRODUCTION
The 33911 was designed and developed as a highly which include a voltage sense port and two wake-up capable
integrated and cost-effective solution for automotive and pins. An internal voltage regulator provides power to a MCU
industrial applications. For automotive body electronics, the device.
33911 is well suited to perform relay control in applications Also included in this device is a LIN physical layer, which
like window lift, sunroof, etc. via a LIN bus. communicates using a single wire. This enables this device
Power switches are provided on the device configured as to be compatible with 3-wire bus systems, where one wire is
high side and low side outputs. Other ports are also provided, used for communication, one for battery, and one for ground.
FUNCTIONAL PIN DESCRIPTION
See Figure 1, 33911 Simplified Application Diagram, microcontroller. Data on this output pin changes on the
page 1, for a graphic representation of the various pins negative edge of the SCLK. When CS is High, this pin will
referred to in the following paragraphs. Also, see the pin remain in high-impedance state.
diagram on page 3 for a description of the pin locations in the
package. CHIP SELECT (CS)
CS is an active low digital input. It must remain low during
RECEIVER OUTPUT (RXD) a valid SPI communication and allow for several devices to
The RXD pin is a digital output. It is the receiver output of be connected in the same SPI bus without contention. A
the LIN interface and reports the state of the bus voltage: rising edge on CS signals the end of the transmission and the
RXD Low when LIN bus is dominant, RXD High when LIN bus moment the data shifted in is latched. A valid transmission
is recessive. must consist of 8 bits only.
While in STOP Mode a low-to-high level transition on this
TRANSMITTER INPUT (TXD) pin will generate a wake-up condition.
The TXD pin is a digital input. It is the transmitter input of
the LIN interface and controls the state of the bus output ANALOG MULTIPLEXER (ADOUT0)
(dominant when TXD is Low, recessive when TXD is High). The ADOUT0 pin can be configured via the SPI to allow
This pin has an internal pull-up to force recessive state in the MCU A/D converter to read the several inputs of the
case the input is left floating. Analog Multiplexer, including the VSENSE, L1, L2 input
voltages and the internal junction temperature.
LIN BUS (LIN)
The LIN pin represents the single-wire bus transmitter and PWM INPUT CONTROL (PWMIN)
receiver. It is suited for automotive bus systems and is This digital input can control the high side and low side
compliant to the LIN bus specification 2.0. drivers in Normal Request and Normal Mode.
The LIN interface is only active during Normal and Normal To enable PWM control, the MCU must perform a write
Request Modes. operation to the High Side Control Register (HSCR), or the
Low Side Control Register (LSCR).
SERIAL DATA CLOCK (SCLK) This pin has an internal 20µA current pull-up.
The SCLK pin is the SPI clock input pin. MISO data
changes on the negative transition of the SCLK. MOSI is RESET (RST)
sampled on the positive edge of the SCLK. This bidirectional pin is used to reset the MCU in case the
33911 detects a reset condition, or to inform the 33911 that
MASTER OUT SLAVE IN (MOSI) the MCU was just reset. After release of the RST pin Normal
The MOSI digital pin receives SPI data from the MCU. This Request Mode is entered.
data input is sampled on the positive edge of SCLK. The RST pin is an active low filtered input and output
formed by a weak pull-up and a switchable pull-down
MASTER IN SLAVE OUT (MISO) structure, which allows this pin to be shorted either to VDD or
The MISO pin sends data to a SPI-enabled MCU. It is a to GND during software development without the risk of
digital tri-state output used to shift serial data to the destroying the driver.
33911

FUNCTIONAL PIN DESCRIPTION
INTERRUPT (IRQ) divider and can be routed to the ADOUT0 output through the
The IRQ pin is a digital output used to signal events or analog multiplexer.
faults to the MCU while in Normal and Normal Request Mode Note: If an Lx input is selected in the analog multiplexer, it
or to signal a wake-up from Stop Mode. This active low output will be disabled as a digital input and remains disabled in low-
will transition high only after the interrupt is acknowledged by power mode. No wake-up feature is available in that
a SPI read of the respective status bits. condition.
When an Lx input is not selected in the analog multiplexer,
WATCHDOG CONFIGURATION (WDCONF) the voltage divider is disconnected from that input.
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure HIGH SIDE OUTPUT (HS1)
the window watchdog period. When connected directly to This high side switch is able to drive loads such as relays
ground, the watchdog will be disabled. When this pin is left or lamps. Its structure is connected to the VS2 supply pin.
open, the watchdog period is fixed to its lower precision The pin is short-circuit protected and also protected against
internal default value (150ms, typical). overheating.
HS1 is controlled by SPI and can respond to a signal
GROUND CONNECTIONS (AGND, PGND, LGND) applied to the PWMIN input pin.
The AGND, PGND and LGND pins are the Analog and The HS1 output can also be used during low-power mode
Power ground pins. for the cyclic-sense of the wake inputs.
The AGND pin is the ground reference of the voltage
regulator. POWER SUPPLIES (VS1 AND VS2)
The PGND and LGND pins are used for high-current load These are the battery level voltage supply pins. In
return as in the relay-drivers and LIN interface pin. application, VS1 and VS2 pins must be protected against a
Note: PGND, AGND and LGND pins must be connected reverse battery connection and negative transient voltages
together. with external components. These pins sustain standard
automotive voltage conditions such as a load dump at 40V.
LOW SIDES (LS1 AND LS2) The high side switch (HS1) is supplied by the VS2 pin, all
LS1 and LS2 are the low side driver outputs. Those other internal blocks are supplied by the VS1 pin.
outputs are short-circuit protected and include active clamp
circuitry to drive inductive loads. Due to the energy clamp VOLTAGE SENSE (VSENSE)
voltage on this pin, it can raise above the battery level when This input can be connected directly to the battery line. It
switched off. The switches are controlled through the SPI and is protected against a battery reverse connection. The
can be configured to respond to a signal applied to the voltage present on this input is scaled down by an internal
PWMIN input pin. voltage divider, and can be routed to the ADOUT0 output pin
Both low side switches are protected against overheating. and used by the MCU to read the battery voltage.
The ESD structure on this pin allows for excursion up to
DIGITAL/ANALOGS (L1 AND L2) +40V and down to -27V, allowing this pin to be connected
The Lx pins are multi purpose inputs. They can be used as directly to the battery line. It is strongly recommended to
digital inputs, which can be sampled by reading the SPI and connect a 10kohm resistor in series with this pin for protection
used for wake-up when 33911 is in low-power mode or used purposes.
as analog inputs for the analog multiplexer. When used to
sense voltage outside the module, a 33kohm series resistor +5V MAIN REGULATOR OUTPUT (VDD)
must be used on each input. An external capacitor must be placed on the VDD pin to
When used as wake-up inputs L1 and L2 can be stabilize the regulated output voltage. The VDD pin is
configured to operate in cyclic sense mode. In this mode, the intended to supply a microcontroller. The pin is current limited
high side switch is configured to be periodically turned on and against shorts to GND and over-temperature protected.
sample the wake-up inputs. If a state change is detected During Stop Mode, the voltage regulator does not operate
between two cycles, a wake-up is initiated. The 33911 can with its full drive capabilities and the output current is limited.
also wake-up from Stop or Sleep by a simple state change on During Sleep Mode the regulator output is completely shut
L1 and L2. down.
When used as an analog input, the voltage present on the
Lx pins are scaled down by a selectable internal voltage
33911

FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33911 - Functional Block Diagram
Integrated Supply
Voltage Regulator VDD
Analog Circuitry
High Side Driver
Window Watchdog Wake-Up
HS1
Digital / Analog Input
Low Side Drivers
Voltage & Temperature Sense LS1 - LS2
MCU Interface and Output Control LIN Physical Layer

Interface
SPI Interface Reset & IRQ Logic
LIN Interface / Control LS/HS - PWM Control
Analog Output 0
Integrated Supply MCU Interface and Output Control

Analog Circuitry Drivers
Figure 14. Functional Internal Block Diagram
ANALOG CIRCUITRY MCU INTERFACE

The 33911 is designed to operate under automotive The 33911 is providing its control and status information
operating conditions. A fully configurable window watchdog through a standard 8-Bit SPI interface. Critical system events
circuit will reset the connected MCU in case of an overflow. such as low or high-voltage/temperature conditions as well as
Two low-power modes are available with several different over-current conditions in any of the driver stages can be
wake-up sources to reactivate the device. Two analog / digital reported to the connected MCU via IRQ or RST.
inputs can be sensed or used as the wake-up source. Both low side and both high side driver outputs can be
The device is capable of sensing the supply voltage controlled via the SPI register as well as PWMIN input.
(VSENSE), the internal chip temperature (CTEMP) as well as The integrated LIN physical layer interface can be
the motor current using an external sense resistor.) configured via the SPI register and its communication is
driven through the RXD and TXD device pin.
HIGH SIDE DRIVER All internal analog sources are multiplexed to the ANOUT0
One current and temperature protected high side driver pin.
with PWM capability is provided to drive small loads such as
status LED’s or small lamps. VOLTAGE REGULATOR OUTPUTS
The driver can be configured for periodic sense during low- One voltage regulators is implemented on the 33911. The
power modes. VDD main regulator output is designed to supply an MCU
with a precise 5V.
LOW SIDE DRIVERS
Two current and temperature protected low side LIN PHYSICAL LAYER INTERFACE
drivers with PWM capability are provided to drive H- The 33911 provides a LIN 2.0 compatible LIN physical
Bridge type relays for power motor applications. layer interface with selectable slew rate and various
diagnostic features.
33911

FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
OPERATIONAL MODES
INTRODUCTION The VDD regulator is ON and delivers its full current

The 33911 offers three main operating modes: Normal capability.
(Run), Stop, and Sleep (Low-power). In Normal Mode, the If an external resistor is connected between the WDCONF
device is active and operating under normal application pin and the Ground, the window watchdog function will be
conditions. The Stop and Sleep Modes are low-power modes enabled.
with wake-up capabilities. The wake-up inputs (L1 and L2) can be read as digital
In Stop Mode, the voltage regulator still supplies the MCU inputs or have its voltage routed through the analog
with VDD (limited current capability), and in Sleep Mode the multiplexer.
voltage regulator is turned off (VDD = 0V). The LIN interface has slew rate and timing compatible with
Wake-up from Stop Mode is initiated by a wake-up the LIN protocol specification 2.0. The LIN bus can transmit
interrupt. Wake-up from Sleep Mode is done by a reset and and receive information.
the voltage regulator is turned back on. The high side and the low side switches are active and
The selection of the different modes is controlled by the have PWM capability according to the SPI configuration.
MOD1:2 bits in the Mode Control Register (MCR). The interrupts are generated to report failures for VSUP
Figure 15 describes how transitions are done between the over/under-voltage, thermal shutdown or thermal shutdown
different operating modes, and Table 5, 25, gives an prewarning on the main regulator.
overview of the operating modes.
SLEEP MODE
RESET MODE The Sleep Mode is a low-power mode. From Normal
The 33911 enters the Reset Mode after a power up. In this Mode, the device enters the Sleep Mode by sending one SPI
mode, the RST pin is low for 1ms (typical value). After this command through the MCR. All blocks are in their lowest
delay, the 33911 enters the Normal Request Mode and the power consumption condition. Only some wake-up sources
RST pin is driven high. (wake-up inputs with or without cyclic sense, forced wake-up,
The Reset Mode is entered if a reset condition occurs (VDD and LIN receiver) are active. The 5V regulator is OFF. The
low, Watchdog trigger fail, after a wake-up from Sleep Mode, internal low-power oscillator may be active if the IC is
or a Normal Request Mode timeout). configured for cyclic sense. In this condition, the high side
switches are turned on periodically and the wake-up inputs
NORMAL REQUEST MODE are sampled.
This is a temporary mode automatically accessed by the Wake-up from Sleep Mode is similar to a power-up. The
device after the Reset Mode, or after a wake-up from Stop device goes into Reset Mode except that the SPI will report
Mode. the wake-up source, and the BATFAIL flag is not set.
In Normal Request Mode, the VDD regulator is ON, the
STOP MODE
Reset pin is high and the LIN is operating in RX Only Mode.
The Stop Mode is the second low-power mode, but in this
As soon as the device enters the Normal Request Mode,
case the 5V regulator is ON with limited current drive
an internal timer is started for 150ms (typical value). During
capability. The application MCU is always supplied while the
these 150ms, the MCU must configure the Timing Control
33911 is operating in Stop Mode.
Register (TIMCR) and the MCR with MOD2 and MOD1 bits
set = 0, to enter in Normal Mode. If within the 150ms timeout The device can enter the Stop Mode only by sending a SPI
the MCU does not command the 33911 to Normal Mode, it command. When the application is in this mode, it can wake-
will enter in Reset Mode. If the WDCONF pin is grounded in up from the 33911 side (for example: cyclic sense, force
order to disable the watchdog function, the 33911 goes wake-up, LIN bus, wake inputs) or the MCU side (CS, RST
directly in Normal Mode after the Reset Mode. If the pins). Wake-up from Stop Mode will transition the 33911 to
WDCONF pin is open, the 33911 stays typically for 150ms in Normal Request Mode and generate an interrupt, except if
Normal Request before entering in Normal Mode. the wake-up event is a low to high transition on the CS pin or
comes from the RST pin.
NORMAL MODE
In Normal Mode, all 33911 functions are active and can be
controlled by the SPI interface and the PWMIN pin.
33911

OPERATIONAL MODES
Normal Request Timeout Expired (t NRTOUT)
VDD LOW
VDD HIGH AND

POWER Power Up RESET DELAY (t RST) EXPIRED NORMAL
DOWN RESET REQUEST
WD DISABLED
WD TRIGGER
WAKE-UP (INTERRUPT)
VDD LOW
NORMAL
WD FAILED
STOP COMMAND
VDD LOW (>t NRTOUT) EXPIRED
AND VSUV = 0 SLEEP COMMAND
WAKE-UP (RESET)
SLEEP STOP
VDD LOW
Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF pin connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via SPI
Sleep Command: Sleep command sent via SPI
wake-up from Stop Mode: Lx state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
wake-up from Sleep Mode: Lx state change, LIN bus wake-up, Periodic wake-up.
Figure 15. Operating Modes and Transitions
33911

OPERATIONAL MODES
Table 5. Operating Modes Overview

Normal
Function Reset Mode Normal Request Mode Stop Mode Sleep Mode
Mode
VDD Full Full Full Stop -

(55)
LSx - SPI/PWM SPI/PWM - -
HS1 - SPI/PWM(55) SPI/PWM Note(56) Note(57)
Analog Mux - SPI SPI - -
Lx - Inputs Inputs Wake-up Wake-up

LIN - Rx-Only full/Rx-Only Rx-Only/Wake-up Wake-up
Watchdog - 150ms (typ.) timeout On (58)/Off - -
VSENSE On On On VDD -
Notes
55. Operation can be controlled by the PWMIN input.
56. HS switch can be configured for cyclic sense operation in Stop Mode.
57. HS switch can be configured for cyclic sense operation in Sleep Mode.
58. Windowing operation when enabled by an external resistor.
INTERRUPTS High-voltage Interrupt

Interrupts are used to signal a microcontroller that a The high-voltage interrupt signals when the supply line
peripheral needs to be serviced. The interrupts which can be (VS1) voltage increases above the VSOV threshold (VSOV).
generated change according to the operating mode. While in
Normal and Normal Request Modes, the 33911 signals Over-temperature Prewarning
through interrupts special conditions which may require a Over-temperature prewarning signals when the 33911
MCU software action. Interrupts are not generated until all temperature has reached the pre-shutdown warning
pending wake-up sources are read in the Interrupt Source threshold. It is used to warn the MCU that an over-
Register (ISR). temperature shutdown in the main 5V regulator is imminent.
While in Stop Mode, interrupts are used to signal wake-up
events. Sleep Mode does not use interrupts, wake-up is LIN Over-current Shutdown / Over-temperature
performed by powering-up the MCU. In Normal and Normal Shutdown / TXD Stuck At Dominant / RXD Short-Circuit
Request mode the wake-up source can be read by the SPI.
These signal fault conditions within the LIN interface will
The interrupts are signaled to the MCU by a low logic level cause the LIN driver to be disabled, except for the LIN over-
of the IRQ pin, which will remain low until the interrupt is current. In order to restart an operation, the fault must be
acknowledged by a SPI read. The IRQ pin will then be driven removed and must be acknowledged by reading the SPI.
high.
The LINOC bit functionality in the LIN Status Register
Interrupts are only asserted while in Normal, Normal (LINSR) is to indicate that an LIN over-current occurred and
Request and Stop mode. Interrupts are not generated while the driver stays enabled.
the RST pin is low.
Following is a list of the interrupt sources in Normal and High Side Over-temperature Shutdown
Normal Request Modes, some of those can be masked by
The high side over-temperature shutdown signals a
writing to the SPI-Interrupt Mask Register (IMR).
shutdown in the high side output.
Low-voltage Interrupt
Low Side Over-temperature Shutdown
The low-voltage interrupt signals when the supply line
The low side over-temperature shutdown signals a
(VS1) voltage drops below the VSUV threshold (VSUV).
shutdown in the low side outputs.
33911

OPERATIONAL MODES
RESET In order to select and activate direct wake-up from Lx

To reset an MCU, the 33911 drives the RST pin low for the inputs, the Wake-up Control Register (WUCR) must be
time the reset condition lasts. configured with appropriate LxWE inputs enabled or
disabled. The wake-up inputs state are read through the
After the reset source has been removed, the state
Wake-up Status Register (WUSR).
machine will drive the RST output low for at least 1ms (typical
value) before driving it high. Lx inputs are also used to perform cyclic sense wake-up.
In the 33911 four main reset sources exist: Note: Selecting an Lx input in the analog multiplexer
before entering low-power mode will disable the wake-up
5V Regulator Low-voltage-Reset (VRSTTH) capability of the Lx input.
The 5V regulator output VDD is continuously monitored Wake-up from Wake-up inputs (L1-L2) with cyclic sense
against brown outs. If the supply monitor detects that the timer enabled
voltage at the VDD pin has dropped below the reset threshold
VRSTTH the 33911 will issue a reset. In case of an over- The SBCLIN can wake-up at the end of a cyclic sense
temperature, the voltage regulator will be disabled and the period if on one of the two wake-up input lines (L1-L2), a state
voltage monitoring will issue a VDDOT Flag independently of change occurs. The HS1 switch is activated in Sleep or Stop
the VDD voltage. Modes from an internal timer. Cyclic sense and force wake-
up are exclusive. If cyclic sense is enabled, the force wake-
Window Watchdog Overflow up can not be enabled.
In order to select and activate the cyclic sense wake-up
If the watchdog counter is not properly serviced while its
from Lx inputs, before entering in low-power modes (Stop or
window is open, the 33911 will detect an MCU software run-
Sleep Modes), the following SPI set-up has to be performed:
away and will reset the microcontroller.
• In WUCR: select the Lx input to WU-enable.
Wake-Up From Sleep Mode • In HSCR: enable HS1.
• In TIMCR: select the CS/WD bit and determine the
During Sleep Mode, the 5V regulator is not active. Hence,
cyclic sense period with CYSTx bits.
all wake-up requests from Sleep Mode require a power-up/
reset sequence. • Perform Goto Sleep/Stop command.
External Reset Forced Wake-up
The 33911 has a bidirectional reset pin which drives the The 33911 can wake-up automatically after a
device to a safe state (same as Reset Mode) for as long as predetermined time spent in Sleep or Stop Mode. Cyclic
this pin is held low. The RST pin must be held low long sense and forced wake-up are exclusive. If forced wake-up is
enough to pass the internal glitch filter and get recognized by enabled, the cyclic sense can not be enabled.
the internal reset circuit. This functionality is also active in To determine the wake-up period, the following SPI set-up
Stop Mode. has to be sent before entering in low-power modes:
After the RST pin is released, there is no extra t RST to be • In TIMCR: select the CS/WD bit and determine the low-
considered. power mode period with CYSTx bits.
• In HSCR: the HS1 bit must be disabled.
WAKE-UP CAPABILITIES
CS Wake-up
Once entered into one of the low-power modes (Sleep or
Stop) only wake-up sources can bring the device into Normal While in Stop Mode, a rising edge on the CS will cause a
Mode operation. wake-up. The CS wake-up does not generate an interrupt
In Stop Mode, a wake-up is signaled to the MCU as an and is not reported on the SPI.
interrupt, while in Sleep Mode, the wake-up is performed by
activating the 5V regulator and resetting the MCU. In both LIN Wake-up
cases, the MCU can detect the wake-up source by accessing While in the low-power mode the 33911 monitors the
the SPI registers. There is no specific SPI register bit to signal activity on the LIN bus. A dominant pulse larger than t PROPWL
a CS wake-up or external reset. If necessary, this condition is followed by a dominant to recessive transition will cause a
detected by excluding all other possible wake-up sources. LIN wake-up. This behavior protects the system from a short-
to ground bus condition.
Wake-up from Wake-up inputs (L1-L2) with cyclic sense
disabled
The wake-up lines are dedicated to sense state changes
of external switches, and wake-up the MCU (in Sleep or Stop
Mode).
33911

OPERATIONAL MODES
RST Wake-up To disable the watchdog function in Normal Mode, the

While in Stop Mode, the 33911 can wake-up when the user must connect the WDCONF pin to ground. This
RST pin is held low long enough to pass the internal glitch measure effectively disables Normal Request Mode. The
filter. Then, it will change to Normal Request or Normal WDOFF bit in the Watchdog Status Register (WDSR) will be
Modes depending on the WDCONF pin configuration. The set. This condition is only detected during Reset Mode.
RST wake-up does not generate an interrupt and is not If neither a resistor nor a connection to ground is detected,
reported via the SPI. the watchdog falls back to the internal lower precision
From Stop Mode, the following wake-up events can be timebase of 150ms (typ.) and signals the faulty condition
configured: through the WDSR.
• Wake-up from Lx inputs without cyclic sense The watchdog timebase can be further divided by a
prescaler which can be configured by the Timing Control
• Cyclic sense wake-up inputs
Register (TIMCR). During Normal Request Mode, the
• Force wake-up
window watchdog is not active but there is a 150ms (typ.)
• CS wake-up timeout for leaving the Normal Request Mode. In case of a
• LIN wake-up timeout, the 33911 will enter into Reset Mode, resetting the
• RST wake-up microcontroller before entering again into Normal Request
From Sleep Mode, the following wake-up events can be Mode.
configured:
• Wake-up from Lx inputs without cyclic sense HIGH SIDE OUTPUT PIN HS1
• Cyclic sense wake-up inputs This output is one high side driver intended to drive small
• Force wake-up resistive loads or LEDs incorporating the following features:
• LIN wake-up • PWM capability (software maskable)
• Open-load detection
WINDOW WATCHDOG • Current limitation
The 33911 includes a configurable window watchdog • Over-temperature shutdown (with maskable interrupt)
which is active in Normal Mode. The watchdog can be • High-voltage shutdown (software maskable)
configured by an external resistor connected to the WDCONF • Cyclic sense
pin. The resistor is used to achieve higher precision in the The high side switch is controlled by the HS1 bit in the High
timebase used for the watchdog. Side Control Register (HSCR).
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR). PWM Capability (direct access)
During the first half of the SPI timeout, watchdog clears are The high side driver offers additional (to the SPI control)
not allowed, but after the first half of the SPI timeout window, direct control via the PWMIN pin.
the clear operation opens. If a clear operation is performed
If the HS1 bit and PWMHS1 is set in the HSCR, then the
outside the window, the 33911 will reset the MCU, in the
HS1 driver is turned on if the PWMIN pin is high, and turned
same way as when the watchdog overflows.
off if the PWMIN pin is low.
WINDOW CLOSED WINDOW OPEN

NO WATCHDOG CLEAR FOR WATCHDOG
ALLOWED CLEAR
WD TIMING X 50% WD TIMING X 50%
WD PERIOD (tPWD)
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
Figure 16. Window Watchdog Operation
33911

OPERATIONAL MODES
Interrupt
HVSE Control VDD
Module VDD
High Voltage Shutdown

PWMIN
High-Side Interrupt
PWMHS1
VS2
MOD1:2 High Side - Driver

on/off
charge pump
HS1
open load detection
Control
HS1OP current limitation
Status
overtemperture shutdown (interrupt maskable)
HS1CL high voltage shutdown (maskable)
HS1
Cyclic Sense
Wakeup
Module
Figure 17. High Side Driver HS1
Open Load Detection Module. The shutdown is indicated as an HS Interrupt in the

The high side driver signals an open-load condition if the Interrupt Source Register (ISR).
current through the high side is below the open-load current A thermal shutdown of the high side driver is indicated by
threshold. setting the HS1OP and HS1CL bits simultaneously.
The open-load condition is indicated with the HS1OP bits If the bit HSM is set in the Interrupt Mask Register (IMR)
in the High Side Status Register (HSSR). than an interrupt (IRQ) is generated.
A write to the High Side Control Register (HSCR), when
Current Limitation the over-temperature condition is gone, will re-enable the
The high side driver has an output current limitation. In high side driver.
combination with the over-temperature shutdown, the high
side driver is protected against over-current and short-circuit High-voltage Shutdown
failures. In case of a high-voltage condition, and if the high-voltage
When the driver operates in the current limitation area, it is shutdown is enabled (bit HVSE in the Mode Control Register
indicated with the bit HS1CL in the HSSR. (MCR) is set), the high side driver is shut down.
Note: If the driver is operating in current limitation mode A write to the HSCR, when the high-voltage condition is
excessive power might be dissipated. gone, will re-enable the high side driver.
Over-temperature Protection (HS Interrupt) Sleep And Stop Mode

The high side driver is protected against over-temperature. The high side driver can be enabled to operate in Sleep
In case of an over-temperature condition, the high side driver and Stop Mode for cyclic sensing. Also see Table 5,
is shut down and the event is latched in the Interrupt Control Operating Modes Overview.
33911

OPERATIONAL MODES
LOW SIDE OUTPUT PINS LS1 AND LS2 To protect the device against over-voltage when an
These outputs are two low side drivers intended to drive inductive load (relay) is turned off, an active clamp will re-
relays incorporating the following features: enable the low side FET if the voltage on the LS1 or LS2 pin
exceeds a certain level.
• PWM capability (software maskable)
• Open load detection PWM Capability (direct access)
• Current limitation
Each low side driver offers additional (to the SPI control)
• Over-temperature shutdown (with maskable interrupt)
direct control via the PWMIN pin.
• Active clamp (for driving relays)
• High-voltage shutdown (software maskable) If both the LS1 and PWMLS1 bits are set in the LSCR, then
the LS1 driver is turned on if the PWMIN pin is high, and
The low side switches are controlled by the bit LS1:2 in the turned off if the PWMIN pin is low. The same applies to the
Low Side Control Register (LSCR). LS2 and PWMLS2 bits for the LS2 driver.
VDD
Interrupt
VDD
HVSE Control
Module
PWMIN
High-voltage Shutdown
Low Side Interrupt
PWMLSx
active
clamp
LSx
MOD1:2 Low Side - Driver

on/off
(active clamp)
LSx
Open-load Detection
Control
LSxOP Status
Current Limitation
Over-temperture Shutdown (interrupt maskable)
LSxCL High-voltage Shutdown (maskable)
PGND
Figure 18. Low Side Drivers LS1 and LS2
Open Load Detection low side drivers are shut down and the event is latched in the
Each low side driver signals an open-load condition if the Interrupt Control Module. The shutdown is indicated as an LS
current through the low side is below the open-load current Interrupt in the Interrupt Source Register (ISR).
threshold. If the bit LSM is set in the Interrupt Mask Register (IMR),
The open-load condition is indicated with the bit LS1OP then an Interrupt (IRQ) is generated.
and LS2OP in the Low Side Status Register (LSSR). A write to the Low Side Control Register (LSCR), when the
over-temperature condition is gone, will re-enable the low
Current Limitation side drivers.
Each low side driver has a current limitation. In
High-voltage Shutdown
combination with the over-temperature shutdown, the low
side drivers are protected against over-current and short- In case of a high voltage condition, and if the high-voltage
circuit failures. shutdown is enabed (bit HVSE in the Mode Control Register
When the drivers operate in current limitation, this is (MCR) is set), both low side drivers are shut down.
indicated with the LS1CL and LS2CL bits in the LSSR. A write to the LSCR, when the high-voltage condition is
Note: If the drivers are operating in current limitation mode gone, will re-enable the low side drivers.
excessive power might be dissipated.
Sleep And Stop Mode
Over-temperature Protection (LS Interrupt) The low side drivers are disabled in Sleep and Stop Mode.
Both low side drivers are protected against over- Also see Table 5, Operating Modes Overview.
temperature. In case of an over-temperature condition both
33911

OPERATIONAL MODES
LIN PHYSICAL LAYER • LIN dominant voltage level selection

The LIN bus pin provides a physical layer for single-wire The LIN driver is a low side MOSFET with over-current
communication in automotive applications. The LIN physical and thermal shutdown. An internal pull-up resistor with a
layer is designed to meet the LIN physical layer specification serial diode structure is integrated, so no external pull-up
and has the following features: components are required for the application in a slave node.
• LIN physical layer 2.0 compliant The fall time from dominant to recessive and the rise time
from recessive to dominant is controlled. The symmetry
• Slew rate selection
between both slopes is guaranteed.
• Over-current shutdown
• Over-temperature shutdown
LIN Pin
• LIN pull-up disable in Stop and Sleep Modes
• Advanced diagnostics The LIN pin offers a high susceptibility immunity level from
external disturbance, guaranteeing communication.
INTERRUPT
CONTROL WAKE-UP
MODULE MODULE
High-voltage High Side LIN

Shutdown Interrupt Wake-up
MOD1:2
LSR0:1
VS1
LINPE
LIN – DRIVER
LDVS
RXONLY Slope and Slew Rate Control
Over-current Shutdown (interrupt maskable)
RXSHORT Over-temperature Shutdown (interrupt maskable)
TXDOM
LINOT
LINOC
30K
LIN
TXD
SLOPE
CONTROL
LGND
WAKE-UP
FILTER
RXD
RECEIVER
Figure 19. LIN Interface
Slew Rate Selection LIN pin can be disconnected by clearing the LINPE bit in the
The slew rate can be selected for optimized operation at Mode Control Register (MCR). The bit LINPE also changes
10.4 and 20kBit/s as well as a fast baud rate for test and the Bus wake-up threshold (VBUSWU).
programming. The slew rate can be adapted with the LSR1:0 This feature will reduce the current consumption in STOP
bits in the LIN Control Register (LINCR). The initial slew rate and SLEEP Modes. It also improves performance and safe
is optimized for 20kBit/s. operation.
LIN Pull-up Disable In Stop And Sleep Modes Current Limit (LIN Interrupt)
In case of a LIN bus short to GND or LIN bus leakage The output low side FET is protected against over-current
during low-power mode, the internal pull-up resistor on the conditions. If an over-current condition occurs (e.g. LIN bus
33911

OPERATIONAL MODES
short to VBAT), the transmitter will not be shut down. The bit A read of the LINSR with the TXD pin is high will clear the
LINOC in the LIN Status Register (LINSR) is set. bit TXDOM.
If the LINM bit is set in the Interrupt Mask Register (IMR)
an Interrupt IRQ will be generated. LIN Dominant Voltage Level Selection
The LIN dominant voltage level can be selected by the
Over-temperature Shutdown (LIN Interrupt) LDVS bit in the LIN Control Register (LINCR).
The output low side FET is protected against over-
temperature conditions. If an over-temperature condition LIN Receiver Operation Only
occurs, the transmitter will be shut down and the LINOT bit in While in Normal Mode, the activation of the RXONLY bit
the LINSR is set. disables the LIN TXD driver. If a LIN error condition occurs,
If the LINM bit is set in the IMR an Interrupt IRQ will be this bit is automatically set. Ifa low-power mode is selected
generated. with this bit set, the LIN wake-up functionality is disabled.
The transmitter is automatically re-enabled once the Then in STOP mode, the RXD pin will reflect the state of the
condition is gone and TXD is high. LIN bus.
A read of the LINSR with the TXD pin high will re-enable
STOP Mode And Wake-up Feature
the transmitter.
During Stop Mode operation, the transmitter of the
RXD Short-circuit Detection (LIN Interrupt) physical layer is disabled. If the LIN-PU bit was set in the Stop
Mode sequence, the internal pull-up resistor is disconnected
The LIN transceiver has a short-circuit detection for the
from VSUP and a small current source keeps the LIN pin in
RXD output pin. In case of a short-circuit condition, either 5V
the recessive state. The receiver is still active and able to
or Ground, the RXSHORT bit in the LINSR is set and the
detect wake-up events on the LIN bus line.
transmitter is shutdown.
A dominant level longer than tPROPWL followed by a rising
If the LINM bit is set in the IMR an Interrupt IRQ will be
edge will generate a wake-up interrupt and will be reported in
generated.
the Interrupt Source Register (ISR). Also see Figure 11,
The transmitter is automatically re-enabled once the page 18.
condition is gone (transition on RXD) and TXD is high.
A read of the LINSR without the RXD pin short-circuit SLEEP Mode And Wake-Up Feature
condition will clear the RXSHORT bit. During Sleep Mode operation, the transmitter of the
physical layer is disabled. If the LIN-PU bit was set in the
TXD Dominant Detection (LIN Interrupt) Sleep Mode sequence, the internal pull-up resistor is
The LIN transceiver monitors the TXD input pin to detect disconnected from VSUP and a small current source keeps
stuck-in-dominant (0V) condition. If a stuck condition occurs the LIN pin in recessive state. The receiver must still active to
(TXD pin 0V for more than 1 second (typ.), the transmitter is detect wake-up events on the LIN bus line.
shut down and the TXDOM bit in the LINSR is set. A dominant level longer than tPROPWL followed by a rising
If the bit LINM is set in the IMR an Interrupt IRQ will be edge will generate a system wake-up (Reset), and will be
generated. reported in the ISR. Also see Figure 10, page 18.
The transmitter is automatically re-enabled once TXD is
high.
33911

LOGIC COMMANDS AND REGISTERS
33911 SPI INTERFACE AND CONFIGURATION • MISO — Master-In Slave-Out

The serial peripheral interface creates the communication • SCLK— Serial Clock
link between a microcontroller (master) and the 33911. A complete data transfer via the SPI consists of 1 byte.
The interface consists of four pins (see Figure 20): The master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
• CS — Chip Select
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
• MOSI — Master-Out Slave-In
information (S3:S0).
CS
Register Write Data
MOSI A3 A2 A1 A0 C3 C2 C1 C0
Register Read Data
MISO VMS LINS HSS LSS S3 S2 S1 S0
SCLK
Read Data Latch Write Data Latch
Rising Edge of SCLK Falling Edge of SCLK

Change MISO/MISO Output Sample MISO/MISO Input
Figure 20. SPI Protocol
During the inactive phase of the CS (HIGH), the new data The rising edge of the Chip Select (CS) indicates the end
transfer is prepared. of the transfer and latches the write data (MOSI) into the
The falling edge of the CS indicates the start of a new data register. The CS high forces MISO to the high impedance
transfer and puts the MISO in the low-impedance state and state.
latches the analog status data (Register read data). Register reset values are described along with the reset
With the rising edge of the SPI clock (SCLK), the data is condition. Reset condition is the condition causing the bit to
moved to MISO/MOSI pins. With the falling edge of the SPI be set to its reset value. The main reset conditions are:
clock (SCLK), the data is sampled by the receiver. - Power-On Reset (POR): level at which the logic is reset
The data transfer is only valid if exactly 8 sample clock and BATFAIL flag sets.
edges are present during the active (low) phase of CS. - Reset Mode
- Reset done by the RST pin (ext_reset)
33911

SPI REGISTER OVERVIEW
Table 6. System Status Register

BIT
Adress(A3:A0) Register Name / Read / Write Information
7 6 5 4
$0 - $F SYSSR - System Status Register R VMS LINS HSS LSS
Table 7 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 7. SPI Register Overview
BIT
Adress(A3:A0) Register Name / Read / Write Information
3 2 1 0
MCR - Mode Control Register W HVSE LINPE MOD2 MOD1

$0
VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL
$1 VSR - Voltage Status Register R VSOV VSUV VDDOT BATFAIL
WUCR - Wake-up Control Register W - - L2WE L1WE

$2
WUSR - Wake-up Status Register R - - L2 L1
$3 WUSR - Wake-up Status Register R - - L2 L1
LINCR - LIN Control Register W LDVS RXONLY LSR1 LSR0

$4
LINSR - LIN Status Register R RXSHORT TXDOM LINOT LINOC
$5 LINSR - LIN Status Register R RXSHORT TXDOM LINOT LINOC
HSCR - High Side Control Register W - PWMHS1 - HS1

$6
HSSR - High Side Status Register R - - HS1OP HS1CL
$7 HSSR - High Side Status Register R - - HS1OP HS1CL
LSCR - Low Side Control Register W PWMLS2 PWMLS1 LS2 LS1

$8
LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL
$9 LSSR - Low Side Status Register R LS2OP LS2CL LS1OP LS1CL
WD2 WD1 WD0

TIMCR - Timing Control Register W CS/WD
$A CYST2 CYST1 CYST0
WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO
$B WDSR - Watchdog Status Register R WDTO WDERR WDOFF WDWO
$C AMUXCR - Analog Multiplexer Control Register W LXDS MX2 MX1 MX0
$D CFR - Configuration Register W - CYSX8 - -
IMR - Interrupt Mask Register W HSM LSM LINM VMM

$E
ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0
$F ISR - Interrupt Source Register R ISR3 ISR2 ISR1 ISR0
33911

REGISTER DEFINITIONS
System Status Register - SYSSR

HS1CL
The System Status Register (SYSSR) is always HSS
HS1OP
transferred with every SPI transmission and gives a quick
system status overview. It summarizes the status of the
Voltage Status Register (VSR), LIN Status Register (LINSR),
High Side Status Register (HSSR), and the Low Side Status Figure 23. High Side Status
Register (LSSR).
LSS - Low Side Switch Status
Table 8. System Status Register This read-only bit indicates that one or more bits in the
LSSR are set.
S7 S6 S5 S4
1 = Low Side Status bit set
Read VMS LINS HSS LSS 0 = None
VMS - Voltage Monitor Status

This read-only bit indicates that one or more bits in the LS1CL
VSR are set. LS1OP
LSS
1 = Voltage Monitor bit set LS2CL
0 = None LS2OP
Figure 24. Low Side Status

BATFAIL
VDDOT Mode Control Register - MCR
VMS
VSUV The Mode Control Register (MCR) allows to switch
between the operation modes and to configure the 33911.
VSOV
Writing the MCR will return the VSR.
Figure 21. Voltage Monitor Status Table 9. Mode Control Register - $0
LINS - LIN Status C3 C2 C1 C0
This read-only bit indicates that one or more bits in the Write HVSE LINPE MOD2 MOD1
LINSR are set.
Reset
1 = LIN Status bit set Value
1 1 - -
0 = None
Reset
POR POR - -
Condition
LINOC HVSE - High-Voltage Shutdown Enable

LINOT This write-only bit enables/disables automatic shutdown of
LINS
TXDOM the high side and the low side drivers during a high-voltage
RXSHORT VSOV condition.
1 = automatic shutdown enabled
Figure 22. LIN Status 0 = automatic shutdown disabled
HSS - High Side Switch Status LINPE - LIN pull-up enable.

This read-only bit indicates that one or more bits in the This write-only bit enables/disables the 30kΩ LIN pull-up
HSSR are set. resistor in STOP and SLEEP modes. This bit also controls
1 = High Side Status bit set the LIN bus wake-up threshold.
0 = None 1 = LIN pull-up resistor enabled
0 = LIN pull-up resistor disabled
33911

MOD2, MOD1 - Mode Control Bits 1 = POR Reset has occurred

These write-only bits select the operating mode and allow 0 = POR Reset has not occurred
to clear the watchdog in accordance with Table 12 Mode
Control Bits. Wake-up Control Register - WUCR
This register is used to control the digital wake-up inputs.
Table 10. Mode Control Bits Writing the Wake-up Control Register (WUCR) will return the
MOD2 MOD1 Description Wake-up Status Register (WUSR).
0 0 Normal Mode
0 1 Stop Mode
Table 12. Wake-up Control Register - $2
1 0 Sleep Mode
C3 C2 C1 C0
1 1 Normal Mode + watchdog Clear
Write 0 0 L2WE L1WE
Voltage Status Register - VSR
Reset
1 1 1 1
Returns the status of the several voltage monitors. This Value
register is also returned when writing to the Mode Control
Register (MCR). Reset
POR, Reset Mode or ext_reset
Condition
Table 11. Voltage Status Register - $0/$1

LxWE - Wake-up Input x Enable
S3 S2 S1 S0
This write-only bit enables/disables which Lx inputs are
Read VSOV VSUV VDDOT BATFAIL enabled. In Stop and Sleep mode the LxWE bit determines
which wake inputs are active for wake-up. If one of the Lx
VSOV - VSUP Over-voltage inputs is selected on the analog multiplexer, the
corresponding LxWE is masked to 0.
This read-only bit indicates an over-voltage condition on
the VS1 pin. 1 = Wake-up Input x enabled.
1 = Over-voltage condition. 0 = Wake-up Input x disabled.
0 = Normal condition.
Wake-up Status Register - WUSR
VSUV - VSUP Under-voltage This register is used to monitor the digital wake-up inputs
and is also returned when writing to the WUCR.
This read-only bit indicates an under-voltage condition on
the VS1 pin. Table 13. Wake-Up Status Register - $2/$3
1 = Under-voltage condition.
S3 S2 S1 S0
0 = Normal condition.
Read - - L2 L1
VDDOT - Main Voltage Regulator Over-temperature
Warning
Lx - Wake-up input x
This read-only bit indicates that the main voltage regulator
This read-only bit indicates the status of the corresponding
temperature reached the Over-temperature Prewarning
Lx input. If the Lx input is not enabled then the according
Threshold.
Wake-Up status will return 0.
1 = Over-temperature Prewarning
After a wake-up form Stop or Sleep Mode these bits also
0 = Normal allow to determine which input has caused the wake-up, by
first reading the Interrupt Status Register (ISR) and then
BATFAIL - Battery Fail Flag. reading the WUSR.
This read-only bit is set during power-up and indicates that 1 = Lx Wake-up.
the 33911 had a Power On Reset (POR). 0 = Lx Wake-up disabled or selected as analog input.
Any access to the MCR or Voltage Status Register (VSR)
will clear the BATFAIL flag.
33911

LIN Control Register - LINCR LIN Status Register - LINSR

This register controls the LIN physical interface block. This register returns the status of the LIN physical
Writing the LIN Control Register (LINCR) returns the LIN interface block and is also returned when writing to the LIN
Status Register (LINSR). Control Register (LINCR).
Table 14. LIN Control Register - $4
Table 16. LIN Status Register - $4/$5
C3 C2 C1 C0
S3 S2 S1 S0
Write LDVS RXONLY LSR1 LSR0
Read RXSHORT TXDOM LINOT LINOC
Reset
0 0 0 0
Value
RXSHORT - RXD Short-circuit
POR, Reset
Reset
POR, Reset
Mode, ext_reset
This read-only bit indicates a short-circuit condition on
Mode or POR RXD (shorted either to 5.0V or to Ground). The short-circuit
Condition or LIN failure
ext_reset
gone* delay must be 8µs worst case to be detected and to shutdown
the driver. To clear this bit, it must be read after the condition
* LIN failure gone: if LIN failure (overtemp, TxD/RxD short) was set, the flag is gone (transition detected on RXD). The LIN driver is
resets automatically when the failure is gone.
automatically re-enabled once the condition is gone.
LDVS - LIN Dominant Voltage Select 1 = RxD short-circuit condition.
This write-only bit controls the LIN Dominant voltage: 0 = None.
1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7V typ)
TXDOM - TXD Permanent Dominant
0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1V typ)
This read-only bit signals the detection of a TXD pin stuck
at dominant (Ground) condition and the resultant shutdown in
RXONLY - LIN Receiver Operation Only.
the LIN transmitter. This condition is detected after the TXD
This write-only bit controls the behavior of the LIN pin remains in dominant state for more than 1 second typical
transmitter. value.
In Normal mode the activation of the RXONLY bit disables To clear this bit, it must be read after TXD has gone high.
the LIN transmitter. In case of a LIN error condition this bit is The LIN driver is automatically re-enabled once TXD goes
automatically set. high.
In Stop Mode this bit disables the LIN wake-up 1 = TXD stuck at dominant fault detected.
functionality and the RXD pin will reflect the state of the LIN
0 = None.
bus.
1 = only LIN receiver active (Normal Mode) or LIN wake- LINOT - LIN Driver Over-temperature Shutdown
up disabled (Stop Mode).
This read-only bit signals that the LIN transceiver was
0 = LIN fully enabled. shut-down due to over-temperature. The transmitter is
automatically re-enabled after the over-temperature
LSRx - LIN Slew-Rate condition is gone and TXD is high. The LINOT bit is cleared
This write-only bit controls the LIN driver slew-rate in after SPI read once the condition is gone.
accordance with Table 15. 1 = LIN over-temperature shutdown
0 = None
Table 15. LIN Slew-Rate Control
LSR1 LSR0 Description LINOC - LIN Driver Over-current Shutdown
0 0 Normal Slew-Rate (up to 20kb/s) This read-only bit signals an over-current condition
0 1 Slow Slew-Rate (up to 10kb/s) occurred on the LIN pin. The LIN driver is not shut down but
1 0 Fast Slew-Rate (up to 100kb/s) an IRQ is generated. To clear this bit, it must be read after the
condition is gone.
1 1 Reserved
1 = LIN over-current shutdown
0 = None
33911

High Side Control Register - HSCR Low Side Control Register - LSCR
This register controls the operation of the high side driver. This register controls the operation of the low side drivers.
Writing to this register returns the High Side Status Register Writing the Low Side Control Register (LSCR) will also return
(HSSR). the Low Side Status Register (LSSR).
Table 17. High Side Control Register - $6 Table 19. Low Side Control Register - $8
C3 C2 C1 C0 C3 C2 C1 C0
Write 0 PWMHS1 0 HS1 Write PWMLS2 PWMLS1 LS2 LS1
Reset Reset
0 0 0 0 0 0 0 0
Value Value
Reset POR, Reset Mode, ext_reset, HS1 Reset POR, Reset Mode, ext_reset, LSx
POR POR
Condition overtemp or (VSOV & HVSE) Condition overtemp or (VSOV & HVSE)
PWMHS1 - PWM Input Control Enable. PWMLx - PWM input control enable.
This write-only bit enables/disables the PWMIN input pin This write-only bit enables/disables the PWMIN input pin
to control the high side switch. The high side switch must be to control the respective low side switch. The corresponding
enabled (HS1 bit). low side switch must be enabled (LSx bit).
1 = PWMIN input controls HS1 output. 1 = PWMIN input controls LSx.
0 = HS1 is controlled only by SPI. 0 = LSx is controlled only by SPI.
HS1 - High Side Switch Control. LSx - LSx switch control.

This write-only bit enables/disables the high side switch. This write-only bit enables/disables the corresponding low
1 = HS1 switch on. side switch.
0 = HS1 switch off. 1 = LSx switch on.
0 = LSx switch off.
High Side Status Register - HSSR
This register returns the status of the high side switch and Low Side Status Register - LSSR
is also returned when writing to the High Side Control This register returns the status of the low side switches
Register (HSCR). and is also returned when writing to the LSCR.
Table 18. High Side Status Register - $6/$7
Table 20. Low Side Status Register - $8/$9
S3 S2 S1 S0
C3 C2 C1 C0
Read - - HS1OP HS1CL
Read LS2OP LS2CL LS1OP LS1CL
High Side thermal shutdown
A thermal shutdown of the high side drivers is indicated by Low Side thermal shutdown
setting the HS1OP and HS1CL bits simultaneously. A thermal shutdown of the low side drivers is indicated by
setting all LSxOP and LSxCL bits simultaneously.
HS1OP - High Side Switch Open-Load Detection
This read-only bit signals that the high side switch is LSxOP - Low Side Switch Open-Load Detection
conducting current below a certain threshold indicating This read-only bit signals that the low side switches are
possible load disconnection. conducting current below a certain threshold indicating
1 = HS1 Open Load detected (or thermal shutdown) possible load disconnection.
0 = Normal 1 = LSx Open-load detected (or thermal shutdown)
0 = Normal
HS1CL - High Side Current Limitation
This read-only bit indicates that the high side switch is LSxCL - Low Side Current Limitation
operating in current limitation mode. This read-only bit indicates that the respective low side
1 = HS1 in current limitation (or thermal shutdown) switch is operating in current limitation mode.
0 = Normal 1 = LSx in current limitation (or thermal shutdown)
0 = Normal
33911

Timing Control Register - TIMCR This option is only active if the high side switch is enabled
This register is a double purpose register which allows to when entering in Stop or Sleep Mode. Otherwise a timed
configure the watchdog and the cyclic sense periods. Writing wake-up is performed after the period shown in Table 23.
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR). Table 23. Cyclic Sense Interval
CYSX8(59) CYST2 CYST1 CYST0 Interval
Table 21. Timing Control Register - $A X 0 0 0 No cyclic sense
C3 C2 C1 C0 0 0 0 1 20ms
0 0 1 0 40ms
WD2 WD1 WD0
Write CS/WD 0 0 1 1 60ms
CYST2 CYST1 CYST0
0 1 0 0 80ms
Reset 0 1 0 1 100ms
- 0 0 0
Value
0 1 1 0 120ms
Reset 0 1 1 1 140ms
- POR
Condition
1 0 0 1 160ms
CS/WD - Cyclic Sense or Watchdog prescaler select. 1 0 1 0 320ms

1 0 1 1 480ms
This write-only bit selects which prescaler is being written
to, the Cyclic Sense prescaler or the watchdog prescaler. 1 1 0 0 640ms
1 = Cyclic Sense Prescaler selected 1 1 0 1 800ms
0 = watchdog Prescaler select 1 1 1 0 960ms
1 1 1 1 1120ms
WDx - Watchdog Prescaler
Notes
This write-only bits selects the divider for the watchdog 59. bit CYSX8 is located in Configuration Register (CFR)
prescaler and therefore selects the watchdog period in
accordance with Table 22. This configuration is valid only if Watchdog Status Register - WDSR
windowing watchdog is active.
This register returns the watchdog status information and
is also returned when writing to the TIMCR.
Table 22. Watchdog Prescaler
WD2 WD1 WD0 Prescaler Divider Table 24. Watchdog Status Register - $A/$B
0 0 0 1
S3 S2 S1 S0
0 0 1 2
Read WDTO WDERR WDOFF WDWO
0 1 0 4
0 1 1 6
WDTO - Watchdog Timeout
1 0 0 8
This read-only bit signals the last reset was caused by
1 0 1 10
either a watchdog timeout or by an attempt to clear the
1 1 0 12 watchdog within the window closed.
1 1 1 14 Any access to this register or the TIMCR will clear the
WDTO bit.
CYSTx - Cyclic Sense Period Prescaler Select 1 = Last reset caused by watchdog timeout
This write-only bits selects the interval for the wake-up 0 = None
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 39).
33911

WDERR - Watchdog Error MXx - Analog Multiplexer Input Select

This read-only bit signals the detection of a missing These write-only bits selects which analog input is
watchdog resistor. In this condition the watchdog is using the multiplexed to the ADOUT0 pin according to Table 26.
internal, lower precision timebase. The Windowing function is When disabled or when in Stop or Sleep Mode, the output
disabled. buffer is not powered and the ADOUT0 output is left floating
1 = WDCONF pin resistor missing to achieve lower current consumption.
0 = WDCONF pin resistor not floating
WDOFF - Watchdog Off Table 26. Analog Multiplexer Channel Select

This read-only bit signals that the watchdog pin connected MX2 MX1 MX0 Meaning
to Ground and therefore disabled. In this case watchdog 0 0 0 Disabled
timeouts are disabled and the device automatically enters
0 0 1 Reserved
Normal Mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory. 0 1 0 Die Temperature Sensor
1 = Watchdog is disabled 0 1 1 VSENSE input
0 = Watchdog is enabled 1 0 0 L1 input

1 0 1 L2 input
WDWO - Watchdog Window Open 1 1 0 Reserved
This read-only bit signals when the watchdog window is 1 1 1 Reserved
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
Configuration Register - CFR
1 = Watchdog window open
This register controls the cyclic sense timing multiplier.
0 = Watchdog window closed
Table 27. Configuration Register - $D
Analog Multiplexer Control Register - MUXCR
This register controls the analog multiplexer and selects C3 C2 C1 C0
the divider ration for the Lx input divider. Write 0 CYSX8 0 0
Table 25. Analog Multiplexer Control Register -$C Reset

0 0 0 0
Value
C3 C2 C1 C0
POR, Reset
Reset
Write LXDS MX2 MX1 MX0 Mode or POR POR POR
Condition
ext_reset
Reset
1 0 0 0
Value
CYSX8 - Cyclic Sense Timing x 8.
Reset This write-only bit influences the cyclic sense period as
POR POR, Reset Mode or ext_reset
Condition
shown in Table 23.
1 = Multiplier enabled
LXDS - Lx Analog Input Divider Select
0 = None
This write-only bit selects the resistor divider for the Lx
analog inputs. Voltage is internally clamped to VDD.
0 = Lx Analog divider: 1
1 = Lx Analog divider: 3.6 (typ.)
33911

Interrupt Mask Register - IMR LINM - LIN Interrupts Mask

This register allow to mask some of interrupt sources. The This write-only bit enables/disables interrupts generated in
respective flags within the Interrupt Source Register (ISR) will the LIN block.
continue to work but will not generate interrupts to the MCU. 1 = LIN Interrupts Enabled
The 5V Regulator over-temperature prewarning interrupt and
0 = LIN Interrupts Disabled
Under Voltage (VSUV) interrupts can not be masked and will
always cause an interrupt.
VMM - Voltage Monitor Interrupt Mask
Writing to the Interrupt Mask Register (IMR) will return the
ISR. This write-only bit enables/disables interrupts generated in
the Voltage Monitor block. The only maskable interrupt in the
Table 28. Interrupt Mask Register - $E Voltage Monitor Block is the VSUP over-voltage interrupt.
1 = Interrupts Enabled
C3 C2 C1 C0
0 = Interrupts Disabled
Write HSM LSM LINM VMM
Interrupt Source Register - ISR
Reset
1 1 1 1 This register allows the MCU to determine the source of
Value
the last interrupt or wake-up respectively. A read of the
Reset register acknowledges the interrupt and leads IRQ pin to
POR
Condition
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
HSM - High Side Interrupt Mask then be driven low again.
This write-only bit enables/disables interrupts generated in This register is also returned when writing to the IMR.
the high side block.
1 = HS Interrupts Enabled Table 29. Interrupt Source Register - $E/$F
0 = HS Interrupts Disabled S3 S2 S1 S0
LSM - Low Side Interrupt Mask Read ISR3 ISR2 ISR1 ISR0
This write-only bit enables/disables interrupts generated in

the low side block. ISRx - Interrupt Source Register
1 = LS Interrupts Enabled These read-only bits indicate the interrupt source following
Table 30. If no interrupt is pending than all bits are 0.
0 = LS Interrupts Disabled
In case more than one interrupt is pending, than the
interrupt sources are handled sequentially multiplex.
Table 30. Interrupt Sources

Interrupt Source Priority
ISR3 ISR2 ISR1 ISR0 none maskable maskable
0 0 0 0 no interrupt no interrupt none
0 0 0 1 Lx Wake-up from Stop Mode- highest
0 0 1 0 - HS Interrupt (Over-temperature)
0 0 1 1 - LS Interrupt (Over-temperature)
0 1 0 0 LIN Interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN Wake-up
0 1 0 1 Voltage Monitor Interrupt Voltage Monitor Interrupt
(Low-voltage and VDD over-temperature) (High-voltage)
0 1 1 0 - Forced Wake-up lowest
33911

TYPICAL APPLICATION
TYPICAL APPLICATION
The 33911 can be configured in several applications. The figure below shows the 33911 in the typical Slave Node Application.
V BAT
D1
VS1
VS2
C2 C1
VDD
Internal
Bus
Interrupt
IRQ Voltage Regulator
C4 C3 Control Module
LVI, HVI, HTI, OCI
AGND
VDD Reset
RST LS1
Control Module
IRQ LVR, HVR, HTR, WD,
Low Side Control HB Type Relay
Module LS2
RST PGND
Window
PWMIN Watchdog Module Motor Output R1
TIMER
High Side Control
Module
HS1
MISO
MOSI Chip Temp Sense Module

SPI
SPI &
SCLK CONTROL
Analog Multiplexer
VBAT Sense Module

VSENSE
CS
MCU
R2
L1
Analog Input Module

R3
A/D ADOUT0 L2
Wake Up Module
Digital Input Module
RXD
SCI LIN Physical Layer LIN LIN

TXD
C5
WDCONF
PGND
AGND
LGND
Typical Component Values:

R4 C1 = 47µF; C2 = C4 = 100nF; C3 = 10µF; C5 = 220pF
R1 = 10kΩ; R2 = R3 = 10kΩ; R4 = 20kΩ-200kΩ
Recommended Configuration of the not Connected Pins (NC):

Pin 15, 16, 20, 21 = GND
Pin 11, 30 = open (floating)
Pin 24 = open (floating) or VS2
Pin 28 = this pin is not internally connected and may be used for PCB routing
optimization.
33911

PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under
Available Documentation column select Packaging Information.
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33911

IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK-
AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTATION,
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33911

REVISION HISTORY
PACKAGE DIMENSIONS
REVISION HISTORY
Revision Date Description of Changes
3.0 9/2007 • Initial Release
4.0 2/2008 • Changed Functional Block Diagram on page 22.

• Corrected typo for Outline drawing number (98A...).
33911

How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:

Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7 Information in this document is provided solely to enable system and software
81829 Muenchen, Germany implementers to use Freescale Semiconductor products. There are no express or
+44 1296 380 456 (English) implied copyright licenses granted hereunder to design or fabricate any integrated
+46 8 52200080 (English) circuits or integrated circuits based on the information in this document.
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
Japan: guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor Japan Ltd. Freescale Semiconductor assume any liability arising out of the application or use of any
Headquarters product or circuit, and specifically disclaims any and all liability, including without
ARCO Tower 15F limitation consequential or incidental damages. “Typical” parameters that may be
1-8-1, Shimo-Meguro, Meguro-ku,
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
Tokyo 153-0064
Japan in different applications and actual performance may vary over time. All operating
0120 191014 or +81 3 5437 9125 parameters, including “Typicals”, must be validated for each customer application by
support.japan@freescale.com customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
Asia/Pacific: not designed, intended, or authorized for use as components in systems intended for
Freescale Semiconductor Hong Kong Ltd. surgical implant into the body, or other applications intended to support or sustain life,
Technical Information Center or for any other application in which the failure of the Freescale Semiconductor product
2 Dai King Street could create a situation where personal injury or death may occur. Should Buyer
Tai Po Industrial Estate purchase or use Freescale Semiconductor products for any such unintended or
Tai Po, N.T., Hong Kong
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
+800 2666 8080
support.asia@freescale.com its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
For Literature Requests Only: directly or indirectly, any claim of personal injury or death associated with such
Freescale Semiconductor Literature Distribution Center unintended or unauthorized use, even if such claim alleges that Freescale
P.O. Box 5405 Semiconductor was negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
LDCForFreescaleSemiconductor@hibbertgroup.com All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
MC33911
Rev. 4.0
2/2008

LIN System Basis Chip With DC Motor Pre-Driver: Advance Information

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

LIN System Basis Chip With DC Motor Pre-Driver: Advance Information

Uploaded by

Copyright:

Available Formats

Freescale Semiconductor Document Number: MC33911

Advance Information Rev. 4.0, 2/2008

LIN System Basis Chip with DC

Figure 1. 33911 Simplified Application Diagram

* This document contains certain information on a new product.

INTERNAL BLOCK DIAGRAM

RST IRQ VS2 VS1 VDD

RXD DIGITAL INPUT MODULE L2

Figure 2. 33911 Simplified Internal Block Diagram

Analog Integrated Circuit Device Data

CS 6 * Special Configuration Recommended / 19 LS1

Figure 3. 33911 Pin Connections

Table 1. 33911 Pin Definitions

4 MOSI SPI Input SPI (Serial Peripheral Interface) data input.

5 SCLK SPI Clock SPI (Serial Peripheral Interface) clock Input.

7 ADOUT0 Analog Output Pin 0 Analog Multiplexer Output.

Analog Integrated Circuit Device Data

Table 1. 33911 Pin Definitions

25 HS1 High Side Output High side switch output.

29 VSENSE Voltage Sense Pin Battery voltage sense input. (3)

Analog Integrated Circuit Device Data

Table 2. Maximum Ratings

Supply Voltage at VS1 and VS2 V

Supply Voltage at VDD VDD -0.3 to 5.5 V

Interrupt Pin (IRQ)(6)

VSENSE Pin Voltage (DC) VVSENSE -27 to 40 V

VDD output current IVDD Internally Limited A

Analog Integrated Circuit Device Data

Table 2. Maximum Ratings (continued)

Operating Ambient Temperature(11) TA °C

Analog Integrated Circuit Device Data

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Nominal Operating Voltage VSUP 5.5 – 18 V

Functional Operating Voltage(18) VSUPOP – – 27 V

SUPPLY CURRENT RANGE (VSUP = 13.5V)

Sleep Mode, VDD OFF, LIN Recessive State(19), (21) ISLEEP µA

Cyclic Sense Supply Current Adder(22) ICYCLIC – 10 – µA

Power-On Reset (BATFAIL)(23) V

VSUP Under-voltage Detection (VSUV Flag) (Normal and Normal Request

Analog Integrated Circuit Device Data

Table 3. Static Electrical Characteristics (continued)

Normal Mode Output Current Limitation IVDDRUN 60 110 200 mA

Stop Mode Output Voltage VDDSTOP V

Stop Mode Output Current Limitation IVDDSTOP 6.0 12 36 mA

Over-temperature Prewarning (Junction)(26) TPRE °C

Analog Integrated Circuit Device Data

Table 3. Static Electrical Characteristics (continued)

MISO SPI OUTPUT PIN (MISO)

Low-state Output Voltage VOL V

High-state Output Voltage VOH V

Tri-state Leakage Current ITRIMISO µA

SPI INPUT PINS (MOSI, SCLK, CS)

CS Pull-up Current IPUCS µA

INTERRUPT OUTPUT PIN (IRQ)

High-state Output Voltage VOH V

Leakage Current VOH mA

PULSE WIDTH MODULATION INPUT PIN (PWMIN)

Low-state Input Voltage VIL -0.3 – 0.3 x VDD V

Analog Integrated Circuit Device Data

Table 3. Static Electrical Characteristics (continued)

Output Current Limitation(28) ILIMHS1 mA

Short-circuit Detection Threshold(30) VTHSC V