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    The document provides instructions for implementing a 4-bit synchronous counter circuit in Verilog. It specifies using pins 47-51 for the 4-bit input D, pin 60 for the load signal S, pin 62 for the clear signal CLR, and pin 63 for the clock signal CLK. The output of the 4-bit counter should be displayed on LEDs. Understanding how the counter circuit works will make implementing the Verilog code straightforward.

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    The document provides instructions for implementing a 4-bit synchronous counter circuit in Verilog. It specifies using pins 47-51 for the 4-bit input D, pin 60 for the load signal S, pin 62 for the clear signal CLR, and pin 63 for the clock signal CLK. The output of the 4-bit counter should be displayed on LEDs. Understanding how the counter circuit works will make implementing the Verilog code straightforward.

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    28 views1 page

    Eee 304 B1 A PDF

    Uploaded by

    ronyiut
    The document provides instructions for implementing a 4-bit synchronous counter circuit in Verilog. It specifies using pins 47-51 for the 4-bit input D, pin 60 for the load signal S, pin 62 for the clear signal CLR, and pin 63 for the clock signal CLK. The output of the 4-bit counter should be displayed on LEDs. Understanding how the counter circuit works will make implementing the Verilog code straightforward.

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    EEE 304

    Lab test (Set-A)

    Implement the following circuit in Verilog. S, CLR, CLK, and 4 bit D is input. 4 bit Q is output. Show the output results on LED.
    Use pin (47,48,49,51) for D, 60 for S, 62 for CLR, and 63 for CLK.
    Note: Try to understand the operation of the circuit. The code will not take time once you understand how it works.

    CLR
    S

    D[3] D[2] D[1] D[0]


    0 0 0 0 0 0 0 0 0 0 0 0

    1 D Q 1 1 D Q 1 1 D Q 1 1 D Q 1 Q[0]
    Q[3] Q[2] Q[1]

    Q Q Q Q

    CLK

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