Experiment 8 : Sequence detector  

19.03.2018 
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Shubham Jain-2016EE30512 
State diagram 
 

 
 
State table 
 

 
 
K-map 
 

 
 

 
 
 
 
 
 
 
 
 
Logic Diagram 
 

 
 
CPLD implementation 

 
  

 
 
Conclusion 
The given problem statement can be solved by using ​6 state Finite State Machine​(initially 7 states that can be reduced 
to 6 after state reduction). To achieve these 6 states we have used ​3 DFF’s​. After writing the state table for this FSM we 
assign the states in binary. From this state table we can deduce the dependence of next states of the FF’s and output of 
FSM on the present states and the input. We could clearly see that the output depend on both input and present states, 
we can call it a ​Moore Machine​. After finding the logic function for all the next states and output we made the logic 
diagram as given above. Finally we simulate the logic diagram semantically on Quartus Altera and run it on CPLD board.